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sys/powerpc/powerpc/cpu.c
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1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 /*- 36 * Copyright (C) 2003 Benno Rice. 37 * All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $ 60 * $FreeBSD$ 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/bus.h> 66 #include <sys/conf.h> 67 #include <sys/cpu.h> 68 #include <sys/kernel.h> 69 #include <sys/proc.h> 70 #include <sys/sysctl.h> 71 #include <sys/sched.h> 72 #include <sys/smp.h> 73 74 #include <machine/bus.h> 75 #include <machine/cpu.h> 76 #include <machine/hid.h> 77 #include <machine/md_var.h> 78 #include <machine/smp.h> 79 #include <machine/spr.h> 80 81 #include <dev/ofw/openfirm.h> 82 83 static void cpu_6xx_setup(int cpuid, uint16_t vers); 84 static void cpu_970_setup(int cpuid, uint16_t vers); 85 static void cpu_booke_setup(int cpuid, uint16_t vers); 86 static void cpu_powerx_setup(int cpuid, uint16_t vers); 87 88 int powerpc_pow_enabled; 89 void (*cpu_idle_hook)(sbintime_t) = NULL; 90 static void cpu_idle_60x(sbintime_t); 91 static void cpu_idle_booke(sbintime_t); 92 #ifdef BOOKE_E500 93 static void cpu_idle_e500mc(sbintime_t sbt); 94 #endif 95 #if defined(__powerpc64__) && defined(AIM) 96 static void cpu_idle_powerx(sbintime_t); 97 static void cpu_idle_power9(sbintime_t); 98 #endif 99 100 struct cputab { 101 const char *name; 102 uint16_t version; 103 uint16_t revfmt; 104 int features; /* Do not include PPC_FEATURE_32 or 105 * PPC_FEATURE_HAS_MMU */ 106 int features2; 107 void (*cpu_setup)(int cpuid, uint16_t vers); 108 }; 109 #define REVFMT_MAJMIN 1 /* %u.%u */ 110 #define REVFMT_HEX 2 /* 0x%04x */ 111 #define REVFMT_DEC 3 /* %u */ 112 static const struct cputab models[] = { 113 { "Motorola PowerPC 601", MPC601, REVFMT_DEC, 114 PPC_FEATURE_HAS_FPU | PPC_FEATURE_UNIFIED_CACHE, 0, cpu_6xx_setup }, 115 { "Motorola PowerPC 602", MPC602, REVFMT_DEC, 116 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 117 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN, 118 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 119 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN, 120 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 121 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN, 122 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 123 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN, 124 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 125 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN, 126 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 127 { "Motorola PowerPC 620", MPC620, REVFMT_HEX, 128 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU, 0, NULL }, 129 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN, 130 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 131 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN, 132 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 133 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN, 134 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 135 0, cpu_970_setup }, 136 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN, 137 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 138 0, cpu_970_setup }, 139 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN, 140 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 141 0, cpu_970_setup }, 142 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN, 143 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 144 0, cpu_970_setup }, 145 { "IBM POWER4", IBMPOWER4, REVFMT_MAJMIN, 146 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL }, 147 { "IBM POWER4+", IBMPOWER4PLUS, REVFMT_MAJMIN, 148 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4, 0, NULL }, 149 { "IBM POWER5", IBMPOWER5, REVFMT_MAJMIN, 150 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER4 | 151 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL }, 152 { "IBM POWER5+", IBMPOWER5PLUS, REVFMT_MAJMIN, 153 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_POWER5_PLUS | 154 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP, 0, NULL }, 155 { "IBM POWER6", IBMPOWER6, REVFMT_MAJMIN, 156 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 157 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 | 158 PPC_FEATURE_TRUE_LE, 0, NULL }, 159 { "IBM POWER7", IBMPOWER7, REVFMT_MAJMIN, 160 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 161 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 | 162 PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE, PPC_FEATURE2_DSCR, NULL }, 163 { "IBM POWER7+", IBMPOWER7PLUS, REVFMT_MAJMIN, 164 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 165 PPC_FEATURE_SMT | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06 | 166 PPC_FEATURE_HAS_VSX, PPC_FEATURE2_DSCR, NULL }, 167 { "IBM POWER8E", IBMPOWER8E, REVFMT_MAJMIN, 168 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 169 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 | 170 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE, 171 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR | 172 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO | 173 PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup }, 174 { "IBM POWER8NVL", IBMPOWER8NVL, REVFMT_MAJMIN, 175 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 176 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 | 177 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE, 178 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR | 179 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO | 180 PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup }, 181 { "IBM POWER8", IBMPOWER8, REVFMT_MAJMIN, 182 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 183 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 | 184 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE, 185 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR | 186 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO | 187 PPC_FEATURE2_HTM_NOSC, cpu_powerx_setup }, 188 { "IBM POWER9", IBMPOWER9, REVFMT_MAJMIN, 189 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 190 PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | PPC_FEATURE_ARCH_2_05 | 191 PPC_FEATURE_ARCH_2_06 | PPC_FEATURE_HAS_VSX | PPC_FEATURE_TRUE_LE, 192 PPC_FEATURE2_ARCH_2_07 | PPC_FEATURE2_HTM | PPC_FEATURE2_DSCR | 193 PPC_FEATURE2_ISEL | PPC_FEATURE2_TAR | PPC_FEATURE2_HAS_VEC_CRYPTO | 194 PPC_FEATURE2_ARCH_3_00 | PPC_FEATURE2_HAS_IEEE128 | 195 PPC_FEATURE2_DARN, cpu_powerx_setup }, 196 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN, 197 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 198 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN, 199 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 200 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN, 201 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 202 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN, 203 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 204 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN, 205 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 206 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN, 207 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 208 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN, 209 PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 210 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN, 211 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 212 { "Motorola PowerPC 8245", MPC8245, REVFMT_MAJMIN, 213 PPC_FEATURE_HAS_FPU, 0, cpu_6xx_setup }, 214 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN, 215 PPC_FEATURE_HAS_SPE | PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_BOOKE, 216 PPC_FEATURE2_ISEL, cpu_booke_setup }, 217 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN, 218 PPC_FEATURE_HAS_SPE | PPC_FEATURE_BOOKE | 219 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE, 220 PPC_FEATURE2_ISEL, cpu_booke_setup }, 221 { "Freescale e500mc core", FSL_E500mc, REVFMT_MAJMIN, 222 PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 | 223 PPC_FEATURE_ARCH_2_06, PPC_FEATURE2_ISEL, 224 cpu_booke_setup }, 225 { "Freescale e5500 core", FSL_E5500, REVFMT_MAJMIN, 226 PPC_FEATURE_64 | PPC_FEATURE_HAS_FPU | PPC_FEATURE_BOOKE | 227 PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06, 228 PPC_FEATURE2_ISEL, cpu_booke_setup }, 229 { "Freescale e6500 core", FSL_E6500, REVFMT_MAJMIN, 230 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 231 PPC_FEATURE_BOOKE | PPC_FEATURE_ARCH_2_05 | PPC_FEATURE_ARCH_2_06, 232 PPC_FEATURE2_ISEL, cpu_booke_setup }, 233 { "IBM Cell Broadband Engine", IBMCELLBE, REVFMT_MAJMIN, 234 PPC_FEATURE_64 | PPC_FEATURE_HAS_ALTIVEC | PPC_FEATURE_HAS_FPU | 235 PPC_FEATURE_CELL | PPC_FEATURE_SMT, 0, NULL}, 236 { "Unknown PowerPC CPU", 0, REVFMT_HEX, 0, 0, NULL }, 237 }; 238 239 static void cpu_6xx_print_cacheinfo(u_int, uint16_t); 240 static int cpu_feature_bit(SYSCTL_HANDLER_ARGS); 241 242 static char model[64]; 243 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, ""); 244 245 static const struct cputab *cput; 246 247 u_long cpu_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU; 248 u_long cpu_features2 = 0; 249 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features, CTLFLAG_RD, 250 &cpu_features, sizeof(cpu_features), "LX", "PowerPC CPU features"); 251 SYSCTL_OPAQUE(_hw, OID_AUTO, cpu_features2, CTLFLAG_RD, 252 &cpu_features2, sizeof(cpu_features2), "LX", "PowerPC CPU features 2"); 253 254 #ifdef __powerpc64__ 255 register_t lpcr = LPCR_LPES; 256 #endif 257 258 /* Provide some user-friendly aliases for bits in cpu_features */ 259 SYSCTL_PROC(_hw, OID_AUTO, floatingpoint, CTLTYPE_INT | CTLFLAG_RD, 260 0, PPC_FEATURE_HAS_FPU, cpu_feature_bit, "I", 261 "Floating point instructions executed in hardware"); 262 SYSCTL_PROC(_hw, OID_AUTO, altivec, CTLTYPE_INT | CTLFLAG_RD, 263 0, PPC_FEATURE_HAS_ALTIVEC, cpu_feature_bit, "I", "CPU supports Altivec"); 264 265 /* 266 * Phase 1 (early) CPU setup. Setup the cpu_features/cpu_features2 variables, 267 * so they can be used during platform and MMU bringup. 268 */ 269 void 270 cpu_feature_setup() 271 { 272 u_int pvr; 273 uint16_t vers; 274 const struct cputab *cp; 275 276 pvr = mfpvr(); 277 vers = pvr >> 16; 278 for (cp = models; cp->version != 0; cp++) { 279 if (cp->version == vers) 280 break; 281 } 282 283 cput = cp; 284 cpu_features |= cp->features; 285 cpu_features2 |= cp->features2; 286 } 287 288 289 void 290 cpu_setup(u_int cpuid) 291 { 292 uint64_t cps; 293 const char *name; 294 u_int maj, min, pvr; 295 uint16_t rev, revfmt, vers; 296 297 pvr = mfpvr(); 298 vers = pvr >> 16; 299 rev = pvr; 300 switch (vers) { 301 case MPC7410: 302 min = (pvr >> 0) & 0xff; 303 maj = min <= 4 ? 1 : 2; 304 break; 305 case FSL_E500v1: 306 case FSL_E500v2: 307 case FSL_E500mc: 308 case FSL_E5500: 309 maj = (pvr >> 4) & 0xf; 310 min = (pvr >> 0) & 0xf; 311 break; 312 default: 313 maj = (pvr >> 8) & 0xf; 314 min = (pvr >> 0) & 0xf; 315 } 316 317 revfmt = cput->revfmt; 318 name = cput->name; 319 if (rev == MPC750 && pvr == 15) { 320 name = "Motorola MPC755"; 321 revfmt = REVFMT_HEX; 322 } 323 strncpy(model, name, sizeof(model) - 1); 324 325 printf("cpu%d: %s revision ", cpuid, name); 326 327 switch (revfmt) { 328 case REVFMT_MAJMIN: 329 printf("%u.%u", maj, min); 330 break; 331 case REVFMT_HEX: 332 printf("0x%04x", rev); 333 break; 334 case REVFMT_DEC: 335 printf("%u", rev); 336 break; 337 } 338 339 if (cpu_est_clockrate(0, &cps) == 0) 340 printf(", %jd.%02jd MHz", cps / 1000000, (cps / 10000) % 100); 341 printf("\n"); 342 343 printf("cpu%d: Features %b\n", cpuid, (int)cpu_features, 344 PPC_FEATURE_BITMASK); 345 if (cpu_features2 != 0) 346 printf("cpu%d: Features2 %b\n", cpuid, (int)cpu_features2, 347 PPC_FEATURE2_BITMASK); 348 349 /* 350 * Configure CPU 351 */ 352 if (cput->cpu_setup != NULL) 353 cput->cpu_setup(cpuid, vers); 354 } 355 356 /* Get current clock frequency for the given cpu id. */ 357 int 358 cpu_est_clockrate(int cpu_id, uint64_t *cps) 359 { 360 uint16_t vers; 361 register_t msr; 362 phandle_t cpu, dev, root; 363 int res = 0; 364 char buf[8]; 365 366 vers = mfpvr() >> 16; 367 msr = mfmsr(); 368 mtmsr(msr & ~PSL_EE); 369 370 switch (vers) { 371 case MPC7450: 372 case MPC7455: 373 case MPC7457: 374 case MPC750: 375 case IBM750FX: 376 case MPC7400: 377 case MPC7410: 378 case MPC7447A: 379 case MPC7448: 380 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 381 mtspr(SPR_PMC1, 0); 382 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); 383 DELAY(1000); 384 *cps = (mfspr(SPR_PMC1) * 1000) + 4999; 385 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 386 387 mtmsr(msr); 388 return (0); 389 case IBM970: 390 case IBM970FX: 391 case IBM970MP: 392 isync(); 393 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); 394 isync(); 395 mtspr(SPR_970MMCR1, 0); 396 mtspr(SPR_970MMCRA, 0); 397 mtspr(SPR_970PMC1, 0); 398 mtspr(SPR_970MMCR0, 399 SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES)); 400 isync(); 401 DELAY(1000); 402 powerpc_sync(); 403 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); 404 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999; 405 406 mtmsr(msr); 407 return (0); 408 409 default: 410 root = OF_peer(0); 411 if (root == 0) 412 return (ENXIO); 413 414 dev = OF_child(root); 415 while (dev != 0) { 416 res = OF_getprop(dev, "name", buf, sizeof(buf)); 417 if (res > 0 && strcmp(buf, "cpus") == 0) 418 break; 419 dev = OF_peer(dev); 420 } 421 cpu = OF_child(dev); 422 while (cpu != 0) { 423 res = OF_getprop(cpu, "device_type", buf, 424 sizeof(buf)); 425 if (res > 0 && strcmp(buf, "cpu") == 0) 426 break; 427 cpu = OF_peer(cpu); 428 } 429 if (cpu == 0) 430 return (ENOENT); 431 if (OF_getprop(cpu, "ibm,extended-clock-frequency", 432 cps, sizeof(*cps)) >= 0) { 433 return (0); 434 } else if (OF_getprop(cpu, "clock-frequency", cps, 435 sizeof(cell_t)) >= 0) { 436 *cps >>= 32; 437 return (0); 438 } else { 439 return (ENOENT); 440 } 441 } 442 } 443 444 void 445 cpu_6xx_setup(int cpuid, uint16_t vers) 446 { 447 register_t hid0, pvr; 448 const char *bitmask; 449 450 hid0 = mfspr(SPR_HID0); 451 pvr = mfpvr(); 452 453 /* 454 * Configure power-saving mode. 455 */ 456 switch (vers) { 457 case MPC603: 458 case MPC603e: 459 case MPC603ev: 460 case MPC604ev: 461 case MPC750: 462 case IBM750FX: 463 case MPC7400: 464 case MPC7410: 465 case MPC8240: 466 case MPC8245: 467 /* Select DOZE mode. */ 468 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 469 hid0 |= HID0_DOZE | HID0_DPM; 470 powerpc_pow_enabled = 1; 471 break; 472 473 case MPC7448: 474 case MPC7447A: 475 case MPC7457: 476 case MPC7455: 477 case MPC7450: 478 /* Enable the 7450 branch caches */ 479 hid0 |= HID0_SGE | HID0_BTIC; 480 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 481 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */ 482 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 483 || (pvr >> 16) == MPC7457) 484 hid0 &= ~HID0_BTIC; 485 /* Select NAP mode. */ 486 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 487 hid0 |= HID0_NAP | HID0_DPM; 488 powerpc_pow_enabled = 1; 489 break; 490 491 default: 492 /* No power-saving mode is available. */ ; 493 } 494 495 switch (vers) { 496 case IBM750FX: 497 case MPC750: 498 hid0 &= ~HID0_DBP; /* XXX correct? */ 499 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 500 break; 501 502 case MPC7400: 503 case MPC7410: 504 hid0 &= ~HID0_SPD; 505 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 506 hid0 |= HID0_EIEC; 507 break; 508 509 } 510 511 mtspr(SPR_HID0, hid0); 512 513 if (bootverbose) 514 cpu_6xx_print_cacheinfo(cpuid, vers); 515 516 switch (vers) { 517 case MPC7447A: 518 case MPC7448: 519 case MPC7450: 520 case MPC7455: 521 case MPC7457: 522 bitmask = HID0_7450_BITMASK; 523 break; 524 default: 525 bitmask = HID0_BITMASK; 526 break; 527 } 528 529 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask); 530 531 if (cpu_idle_hook == NULL) 532 cpu_idle_hook = cpu_idle_60x; 533 } 534 535 536 static void 537 cpu_6xx_print_cacheinfo(u_int cpuid, uint16_t vers) 538 { 539 register_t hid; 540 541 hid = mfspr(SPR_HID0); 542 printf("cpu%u: ", cpuid); 543 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis"); 544 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis"); 545 546 printf("cpu%u: ", cpuid); 547 if (mfspr(SPR_L2CR) & L2CR_L2E) { 548 switch (vers) { 549 case MPC7450: 550 case MPC7455: 551 case MPC7457: 552 printf("256KB L2 cache, "); 553 if (mfspr(SPR_L3CR) & L3CR_L3E) 554 printf("%cMB L3 backside cache", 555 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1'); 556 else 557 printf("L3 cache disabled"); 558 printf("\n"); 559 break; 560 case IBM750FX: 561 printf("512KB L2 cache\n"); 562 break; 563 default: 564 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) { 565 case L2SIZ_256K: 566 printf("256KB "); 567 break; 568 case L2SIZ_512K: 569 printf("512KB "); 570 break; 571 case L2SIZ_1M: 572 printf("1MB "); 573 break; 574 } 575 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT) 576 ? "through" : "back"); 577 if (mfspr(SPR_L2CR) & L2CR_L2PE) 578 printf(", with parity"); 579 printf(" backside cache\n"); 580 break; 581 } 582 } else 583 printf("L2 cache disabled\n"); 584 } 585 586 static void 587 cpu_booke_setup(int cpuid, uint16_t vers) 588 { 589 #ifdef BOOKE_E500 590 register_t hid0; 591 const char *bitmask; 592 593 hid0 = mfspr(SPR_HID0); 594 595 switch (vers) { 596 case FSL_E500mc: 597 bitmask = HID0_E500MC_BITMASK; 598 cpu_idle_hook = cpu_idle_e500mc; 599 break; 600 case FSL_E5500: 601 case FSL_E6500: 602 bitmask = HID0_E5500_BITMASK; 603 cpu_idle_hook = cpu_idle_e500mc; 604 break; 605 case FSL_E500v1: 606 case FSL_E500v2: 607 /* Only e500v1/v2 support HID0 power management setup. */ 608 609 /* Program power-management mode. */ 610 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 611 hid0 |= HID0_DOZE; 612 613 mtspr(SPR_HID0, hid0); 614 default: 615 bitmask = HID0_E500_BITMASK; 616 break; 617 } 618 printf("cpu%d: HID0 %b\n", cpuid, (int)hid0, bitmask); 619 #endif 620 621 if (cpu_idle_hook == NULL) 622 cpu_idle_hook = cpu_idle_booke; 623 } 624 625 static void 626 cpu_970_setup(int cpuid, uint16_t vers) 627 { 628 #ifdef AIM 629 uint32_t hid0_hi, hid0_lo; 630 631 __asm __volatile ("mfspr %0,%2; clrldi %1,%0,32; srdi %0,%0,32;" 632 : "=r" (hid0_hi), "=r" (hid0_lo) : "K" (SPR_HID0)); 633 634 /* Configure power-saving mode */ 635 switch (vers) { 636 case IBM970MP: 637 hid0_hi |= (HID0_DEEPNAP | HID0_NAP | HID0_DPM); 638 hid0_hi &= ~HID0_DOZE; 639 break; 640 default: 641 hid0_hi |= (HID0_NAP | HID0_DPM); 642 hid0_hi &= ~(HID0_DOZE | HID0_DEEPNAP); 643 break; 644 } 645 powerpc_pow_enabled = 1; 646 647 __asm __volatile (" \ 648 sync; isync; \ 649 sldi %0,%0,32; or %0,%0,%1; \ 650 mtspr %2, %0; \ 651 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \ 652 mfspr %0, %2; mfspr %0, %2; mfspr %0, %2; \ 653 sync; isync" 654 :: "r" (hid0_hi), "r"(hid0_lo), "K" (SPR_HID0)); 655 656 __asm __volatile ("mfspr %0,%1; srdi %0,%0,32;" 657 : "=r" (hid0_hi) : "K" (SPR_HID0)); 658 printf("cpu%d: HID0 %b\n", cpuid, (int)(hid0_hi), HID0_970_BITMASK); 659 #endif 660 661 cpu_idle_hook = cpu_idle_60x; 662 } 663 664 static void 665 cpu_powerx_setup(int cpuid, uint16_t vers) 666 { 667 668 #if defined(__powerpc64__) && defined(AIM) 669 if ((mfmsr() & PSL_HV) == 0) 670 return; 671 672 /* Configure power-saving */ 673 switch (vers) { 674 case IBMPOWER8: 675 case IBMPOWER8E: 676 case IBMPOWER8NVL: 677 cpu_idle_hook = cpu_idle_powerx; 678 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET); 679 isync(); 680 break; 681 case IBMPOWER9: 682 cpu_idle_hook = cpu_idle_power9; 683 mtspr(SPR_LPCR, mfspr(SPR_LPCR) | LPCR_PECE_WAKESET); 684 isync(); 685 break; 686 default: 687 return; 688 } 689 690 #endif 691 } 692 693 static int 694 cpu_feature_bit(SYSCTL_HANDLER_ARGS) 695 { 696 int result; 697 698 result = (cpu_features & arg2) ? 1 : 0; 699 700 return (sysctl_handle_int(oidp, &result, 0, req)); 701 } 702 703 void 704 cpu_idle(int busy) 705 { 706 sbintime_t sbt = -1; 707 708 #ifdef INVARIANTS 709 if ((mfmsr() & PSL_EE) != PSL_EE) { 710 struct thread *td = curthread; 711 printf("td msr %#lx\n", (u_long)td->td_md.md_saved_msr); 712 panic("ints disabled in idleproc!"); 713 } 714 #endif 715 716 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 717 busy, curcpu); 718 719 if (cpu_idle_hook != NULL) { 720 if (!busy) { 721 critical_enter(); 722 sbt = cpu_idleclock(); 723 } 724 cpu_idle_hook(sbt); 725 if (!busy) { 726 cpu_activeclock(); 727 critical_exit(); 728 } 729 } 730 731 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 732 busy, curcpu); 733 } 734 735 static void 736 cpu_idle_60x(sbintime_t sbt) 737 { 738 register_t msr; 739 uint16_t vers; 740 741 if (!powerpc_pow_enabled) 742 return; 743 744 msr = mfmsr(); 745 vers = mfpvr() >> 16; 746 747 #ifdef AIM 748 switch (vers) { 749 case IBM970: 750 case IBM970FX: 751 case IBM970MP: 752 case MPC7447A: 753 case MPC7448: 754 case MPC7450: 755 case MPC7455: 756 case MPC7457: 757 __asm __volatile("\ 758 dssall; sync; mtmsr %0; isync" 759 :: "r"(msr | PSL_POW)); 760 break; 761 default: 762 powerpc_sync(); 763 mtmsr(msr | PSL_POW); 764 break; 765 } 766 #endif 767 } 768 769 #ifdef BOOKE_E500 770 static void 771 cpu_idle_e500mc(sbintime_t sbt) 772 { 773 /* 774 * Base binutils doesn't know what the 'wait' instruction is, so 775 * use the opcode encoding here. 776 */ 777 __asm __volatile(".long 0x7c00007c"); 778 } 779 #endif 780 781 static void 782 cpu_idle_booke(sbintime_t sbt) 783 { 784 register_t msr; 785 786 msr = mfmsr(); 787 788 #ifdef BOOKE_E500 789 powerpc_sync(); 790 mtmsr(msr | PSL_WE); 791 #endif 792 } 793 794 #if defined(__powerpc64__) && defined(AIM) 795 static void 796 cpu_idle_powerx(sbintime_t sbt) 797 { 798 799 /* Sleeping when running on one cpu gives no advantages - avoid it */ 800 if (smp_started == 0) 801 return; 802 803 spinlock_enter(); 804 if (sched_runnable()) { 805 spinlock_exit(); 806 return; 807 } 808 809 if (can_wakeup == 0) 810 can_wakeup = 1; 811 mb(); 812 813 enter_idle_powerx(); 814 spinlock_exit(); 815 } 816 817 static void 818 cpu_idle_power9(sbintime_t sbt) 819 { 820 register_t msr; 821 822 msr = mfmsr(); 823 824 /* Suspend external interrupts until stop instruction completes. */ 825 mtmsr(msr & ~PSL_EE); 826 /* Set the stop state to lowest latency, wake up to next instruction */ 827 mtspr(SPR_PSSCR, 0); 828 /* "stop" instruction (PowerISA 3.0) */ 829 __asm __volatile (".long 0x4c0002e4"); 830 /* 831 * Re-enable external interrupts to capture the interrupt that caused 832 * the wake up. 833 */ 834 mtmsr(msr); 835 836 } 837 #endif 838 839 int 840 cpu_idle_wakeup(int cpu) 841 { 842 843 return (0); 844 }
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