Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/powerpc/powerpc/cpu.c
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1 /*- 2 * Copyright (c) 2001 Matt Thomas. 3 * Copyright (c) 2001 Tsubai Masanari. 4 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by 18 * Internet Research Institute, Inc. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (C) 2003 Benno Rice. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 51 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 52 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 53 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 54 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 55 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 * 57 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $ 58 * $FreeBSD$ 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/bus.h> 64 #include <sys/conf.h> 65 #include <sys/kernel.h> 66 #include <sys/sysctl.h> 67 68 #include <machine/bus.h> 69 #include <machine/hid.h> 70 #include <machine/md_var.h> 71 #include <machine/spr.h> 72 73 struct cputab { 74 const char *name; 75 uint16_t version; 76 uint16_t revfmt; 77 }; 78 #define REVFMT_MAJMIN 1 /* %u.%u */ 79 #define REVFMT_HEX 2 /* 0x%04x */ 80 #define REVFMT_DEC 3 /* %u */ 81 static const struct cputab models[] = { 82 { "Motorola PowerPC 601", MPC601, REVFMT_DEC }, 83 { "Motorola PowerPC 602", MPC602, REVFMT_DEC }, 84 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN }, 85 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN }, 86 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN }, 87 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN }, 88 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN }, 89 { "Motorola PowerPC 620", MPC620, REVFMT_HEX }, 90 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN }, 91 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN }, 92 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN }, 93 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN }, 94 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN }, 95 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN }, 96 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN }, 97 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN }, 98 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN }, 99 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN }, 100 { "Unknown PowerPC CPU", 0, REVFMT_HEX } 101 }; 102 103 static char model[64]; 104 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, ""); 105 106 static register_t l2cr_config = 0; 107 108 static void cpu_print_speed(void); 109 static void cpu_config_l2cr(u_int, uint16_t); 110 111 void 112 cpu_setup(u_int cpuid) 113 { 114 u_int pvr, maj, min, hid0; 115 uint16_t vers, rev, revfmt; 116 const struct cputab *cp; 117 const char *name; 118 char *bitmask; 119 120 pvr = mfpvr(); 121 vers = pvr >> 16; 122 rev = pvr; 123 switch (vers) { 124 case MPC7410: 125 min = (pvr >> 0) & 0xff; 126 maj = min <= 4 ? 1 : 2; 127 break; 128 default: 129 maj = (pvr >> 8) & 0xf; 130 min = (pvr >> 0) & 0xf; 131 } 132 133 for (cp = models; cp->version != 0; cp++) { 134 if (cp->version == vers) 135 break; 136 } 137 138 revfmt = cp->revfmt; 139 name = cp->name; 140 if (rev == MPC750 && pvr == 15) { 141 name = "Motorola MPC755"; 142 revfmt = REVFMT_HEX; 143 } 144 strncpy(model, name, sizeof(model) - 1); 145 146 printf("cpu%d: %s revision ", cpuid, name); 147 148 switch (revfmt) { 149 case REVFMT_MAJMIN: 150 printf("%u.%u", maj, min); 151 break; 152 case REVFMT_HEX: 153 printf("0x%04x", rev); 154 break; 155 case REVFMT_DEC: 156 printf("%u", rev); 157 break; 158 } 159 160 hid0 = mfspr(SPR_HID0); 161 162 /* 163 * Configure power-saving mode. 164 */ 165 switch (vers) { 166 case MPC603: 167 case MPC603e: 168 case MPC603ev: 169 case MPC604ev: 170 case MPC750: 171 case IBM750FX: 172 case MPC7400: 173 case MPC7410: 174 case MPC8240: 175 case MPC8245: 176 /* Select DOZE mode. */ 177 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 178 hid0 |= HID0_DOZE | HID0_DPM; 179 #ifdef notyet 180 powersave = 1; 181 #endif 182 break; 183 184 case MPC7448: 185 case MPC7447A: 186 case MPC7457: 187 case MPC7455: 188 case MPC7450: 189 /* Enable the 7450 branch caches */ 190 hid0 |= HID0_SGE | HID0_BTIC; 191 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 192 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */ 193 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 194 || (pvr >> 16) == MPC7457) 195 hid0 &= ~HID0_BTIC; 196 /* Select NAP mode. */ 197 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 198 hid0 |= HID0_NAP | HID0_DPM; 199 #ifdef notyet 200 powersave = 0; /* but don't use it */ 201 #endif 202 break; 203 204 default: 205 /* No power-saving mode is available. */ ; 206 } 207 208 switch (vers) { 209 case IBM750FX: 210 case MPC750: 211 hid0 &= ~HID0_DBP; /* XXX correct? */ 212 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 213 break; 214 215 case MPC7400: 216 case MPC7410: 217 hid0 &= ~HID0_SPD; 218 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 219 hid0 |= HID0_EIEC; 220 break; 221 } 222 223 mtspr(SPR_HID0, hid0); 224 225 switch (vers) { 226 case MPC7447A: 227 case MPC7448: 228 case MPC7450: 229 case MPC7455: 230 case MPC7457: 231 bitmask = HID0_7450_BITMASK; 232 break; 233 default: 234 bitmask = HID0_BITMASK; 235 break; 236 } 237 238 switch (vers) { 239 case MPC750: 240 case IBM750FX: 241 case MPC7400: 242 case MPC7410: 243 case MPC7447A: 244 case MPC7448: 245 case MPC7450: 246 case MPC7455: 247 case MPC7457: 248 cpu_print_speed(); 249 printf("\n"); 250 cpu_config_l2cr(cpuid, vers); 251 break; 252 253 default: 254 printf("\n"); 255 break; 256 } 257 258 printf("cpu%d: HID0 %b\n", cpuid, hid0, bitmask); 259 } 260 261 void 262 cpu_print_speed(void) 263 { 264 uint64_t cps; 265 266 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 267 mtspr(SPR_PMC1, 0); 268 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); 269 DELAY(100000); 270 cps = (mfspr(SPR_PMC1) * 10) + 4999; 271 printf(", %lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100); 272 } 273 274 void 275 cpu_config_l2cr(u_int cpuid, uint16_t vers) 276 { 277 u_int l2cr, x, msr; 278 279 l2cr = mfspr(SPR_L2CR); 280 281 /* 282 * For MP systems, the firmware may only configure the L2 cache 283 * on the first CPU. In this case, assume that the other CPUs 284 * should use the same value for L2CR. 285 */ 286 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 287 l2cr_config = l2cr; 288 } 289 290 /* 291 * Configure L2 cache if not enabled. 292 */ 293 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 294 l2cr = l2cr_config; 295 296 /* Disable interrupts and set the cache config bits. */ 297 msr = mfmsr(); 298 mtmsr(msr & ~PSL_EE); 299 #ifdef ALTIVEC 300 if (cpu_altivec) 301 __asm __volatile("dssall"); 302 #endif 303 __asm __volatile("sync"); 304 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 305 __asm __volatile("sync"); 306 307 /* Wait for L2 clock to be stable (640 L2 clocks). */ 308 DELAY(100); 309 310 /* Invalidate all L2 contents. */ 311 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 312 do { 313 x = mfspr(SPR_L2CR); 314 } while (x & L2CR_L2IP); 315 316 /* Enable L2 cache. */ 317 l2cr |= L2CR_L2E; 318 mtspr(SPR_L2CR, l2cr); 319 mtmsr(msr); 320 } 321 322 if (!bootverbose) 323 return; 324 325 printf("cpu%d: ", cpuid); 326 327 if (l2cr & L2CR_L2E) { 328 if (vers == MPC7450 || 329 vers == MPC7455 || 330 vers == MPC7457) { 331 u_int l3cr; 332 333 printf("256KB L2 cache"); 334 335 l3cr = mfspr(SPR_L3CR); 336 if (l3cr & L3CR_L3E) 337 printf(", %cMB L3 backside cache", 338 l3cr & L3CR_L3SIZ ? '2' : '1'); 339 printf("\n"); 340 return; 341 } 342 if (vers == IBM750FX) { 343 printf("512KB L2 cache\n"); 344 return; 345 } 346 switch (l2cr & L2CR_L2SIZ) { 347 case L2SIZ_256K: 348 printf("256KB"); 349 break; 350 case L2SIZ_512K: 351 printf("512KB"); 352 break; 353 case L2SIZ_1M: 354 printf("1MB"); 355 break; 356 default: 357 printf("unknown size"); 358 } 359 if (l2cr & L2CR_L2WT) { 360 printf(" write-through"); 361 } else { 362 printf(" write-back"); 363 } 364 switch (l2cr & L2CR_L2RAM) { 365 case L2RAM_FLOWTHRU_BURST: 366 printf(" flow-through synchronous burst SRAM"); 367 break; 368 case L2RAM_PIPELINE_BURST: 369 printf(" pipelined synchronous burst SRAM"); 370 break; 371 case L2RAM_PIPELINE_LATE: 372 printf(" pipelined synchronous late-write SRAM"); 373 break; 374 default: 375 printf(" unknown type"); 376 } 377 378 if (l2cr & L2CR_L2PE) 379 printf(" with parity"); 380 printf(" backside cache"); 381 } else 382 printf("L2 cache not enabled"); 383 384 printf("\n"); 385 }
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