Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/powerpc/powerpc/cpu.c
Version:
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1 /*- 2 * Copyright (c) 2001 Matt Thomas. 3 * Copyright (c) 2001 Tsubai Masanari. 4 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by 18 * Internet Research Institute, Inc. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (C) 2003 Benno Rice. 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 46 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR 47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 48 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 49 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 50 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 51 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 52 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 53 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 54 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 55 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 56 * 57 * from $NetBSD: cpu_subr.c,v 1.1 2003/02/03 17:10:09 matt Exp $ 58 * $FreeBSD: releng/8.0/sys/powerpc/powerpc/cpu.c 194374 2009-06-17 16:34:40Z nwhitehorn $ 59 */ 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/bus.h> 64 #include <sys/conf.h> 65 #include <sys/cpu.h> 66 #include <sys/kernel.h> 67 #include <sys/sysctl.h> 68 69 #include <machine/bus.h> 70 #include <machine/hid.h> 71 #include <machine/md_var.h> 72 #include <machine/spr.h> 73 74 int powerpc_pow_enabled; 75 76 struct cputab { 77 const char *name; 78 uint16_t version; 79 uint16_t revfmt; 80 }; 81 #define REVFMT_MAJMIN 1 /* %u.%u */ 82 #define REVFMT_HEX 2 /* 0x%04x */ 83 #define REVFMT_DEC 3 /* %u */ 84 static const struct cputab models[] = { 85 { "Motorola PowerPC 601", MPC601, REVFMT_DEC }, 86 { "Motorola PowerPC 602", MPC602, REVFMT_DEC }, 87 { "Motorola PowerPC 603", MPC603, REVFMT_MAJMIN }, 88 { "Motorola PowerPC 603e", MPC603e, REVFMT_MAJMIN }, 89 { "Motorola PowerPC 603ev", MPC603ev, REVFMT_MAJMIN }, 90 { "Motorola PowerPC 604", MPC604, REVFMT_MAJMIN }, 91 { "Motorola PowerPC 604ev", MPC604ev, REVFMT_MAJMIN }, 92 { "Motorola PowerPC 620", MPC620, REVFMT_HEX }, 93 { "Motorola PowerPC 750", MPC750, REVFMT_MAJMIN }, 94 { "IBM PowerPC 750FX", IBM750FX, REVFMT_MAJMIN }, 95 { "IBM PowerPC 970", IBM970, REVFMT_MAJMIN }, 96 { "IBM PowerPC 970FX", IBM970FX, REVFMT_MAJMIN }, 97 { "IBM PowerPC 970GX", IBM970GX, REVFMT_MAJMIN }, 98 { "IBM PowerPC 970MP", IBM970MP, REVFMT_MAJMIN }, 99 { "Motorola PowerPC 7400", MPC7400, REVFMT_MAJMIN }, 100 { "Motorola PowerPC 7410", MPC7410, REVFMT_MAJMIN }, 101 { "Motorola PowerPC 7450", MPC7450, REVFMT_MAJMIN }, 102 { "Motorola PowerPC 7455", MPC7455, REVFMT_MAJMIN }, 103 { "Motorola PowerPC 7457", MPC7457, REVFMT_MAJMIN }, 104 { "Motorola PowerPC 7447A", MPC7447A, REVFMT_MAJMIN }, 105 { "Motorola PowerPC 7448", MPC7448, REVFMT_MAJMIN }, 106 { "Motorola PowerPC 8240", MPC8240, REVFMT_MAJMIN }, 107 { "Freescale e500v1 core", FSL_E500v1, REVFMT_MAJMIN }, 108 { "Freescale e500v2 core", FSL_E500v2, REVFMT_MAJMIN }, 109 { "Unknown PowerPC CPU", 0, REVFMT_HEX } 110 }; 111 112 static char model[64]; 113 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, model, 0, ""); 114 115 register_t l2cr_config = 0; 116 register_t l3cr_config = 0; 117 118 static void cpu_print_speed(void); 119 static void cpu_print_cacheinfo(u_int, uint16_t); 120 121 void 122 cpu_setup(u_int cpuid) 123 { 124 u_int pvr, maj, min, hid0; 125 uint16_t vers, rev, revfmt; 126 const struct cputab *cp; 127 const char *name; 128 char *bitmask; 129 130 pvr = mfpvr(); 131 vers = pvr >> 16; 132 rev = pvr; 133 switch (vers) { 134 case MPC7410: 135 min = (pvr >> 0) & 0xff; 136 maj = min <= 4 ? 1 : 2; 137 break; 138 case FSL_E500v1: 139 case FSL_E500v2: 140 maj = (pvr >> 4) & 0xf; 141 min = (pvr >> 0) & 0xf; 142 break; 143 default: 144 maj = (pvr >> 8) & 0xf; 145 min = (pvr >> 0) & 0xf; 146 } 147 148 for (cp = models; cp->version != 0; cp++) { 149 if (cp->version == vers) 150 break; 151 } 152 153 revfmt = cp->revfmt; 154 name = cp->name; 155 if (rev == MPC750 && pvr == 15) { 156 name = "Motorola MPC755"; 157 revfmt = REVFMT_HEX; 158 } 159 strncpy(model, name, sizeof(model) - 1); 160 161 printf("cpu%d: %s revision ", cpuid, name); 162 163 switch (revfmt) { 164 case REVFMT_MAJMIN: 165 printf("%u.%u", maj, min); 166 break; 167 case REVFMT_HEX: 168 printf("0x%04x", rev); 169 break; 170 case REVFMT_DEC: 171 printf("%u", rev); 172 break; 173 } 174 175 hid0 = mfspr(SPR_HID0); 176 177 /* 178 * Configure power-saving mode. 179 */ 180 switch (vers) { 181 case MPC603: 182 case MPC603e: 183 case MPC603ev: 184 case MPC604ev: 185 case MPC750: 186 case IBM750FX: 187 case MPC7400: 188 case MPC7410: 189 case MPC8240: 190 case MPC8245: 191 /* Select DOZE mode. */ 192 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 193 hid0 |= HID0_DOZE | HID0_DPM; 194 powerpc_pow_enabled = 1; 195 break; 196 197 case MPC7448: 198 case MPC7447A: 199 case MPC7457: 200 case MPC7455: 201 case MPC7450: 202 /* Enable the 7450 branch caches */ 203 hid0 |= HID0_SGE | HID0_BTIC; 204 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 205 /* Disable BTIC on 7450 Rev 2.0 or earlier and on 7457 */ 206 if (((pvr >> 16) == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 207 || (pvr >> 16) == MPC7457) 208 hid0 &= ~HID0_BTIC; 209 /* Select NAP mode. */ 210 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 211 hid0 |= HID0_NAP | HID0_DPM; 212 powerpc_pow_enabled = 1; 213 break; 214 215 default: 216 /* No power-saving mode is available. */ ; 217 } 218 219 switch (vers) { 220 case IBM750FX: 221 case MPC750: 222 hid0 &= ~HID0_DBP; /* XXX correct? */ 223 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 224 break; 225 226 case MPC7400: 227 case MPC7410: 228 hid0 &= ~HID0_SPD; 229 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 230 hid0 |= HID0_EIEC; 231 break; 232 233 case FSL_E500v1: 234 case FSL_E500v2: 235 break; 236 } 237 238 mtspr(SPR_HID0, hid0); 239 240 switch (vers) { 241 case MPC7447A: 242 case MPC7448: 243 case MPC7450: 244 case MPC7455: 245 case MPC7457: 246 bitmask = HID0_7450_BITMASK; 247 break; 248 case FSL_E500v1: 249 case FSL_E500v2: 250 bitmask = HID0_E500_BITMASK; 251 break; 252 default: 253 bitmask = HID0_BITMASK; 254 break; 255 } 256 257 switch (vers) { 258 case MPC7450: 259 case MPC7455: 260 case MPC7457: 261 /* Only MPC745x CPUs have an L3 cache. */ 262 263 l3cr_config = mfspr(SPR_L3CR); 264 265 /* Fallthrough */ 266 case MPC750: 267 case IBM750FX: 268 case MPC7400: 269 case MPC7410: 270 case MPC7447A: 271 case MPC7448: 272 cpu_print_speed(); 273 printf("\n"); 274 275 l2cr_config = mfspr(SPR_L2CR); 276 277 if (bootverbose) 278 cpu_print_cacheinfo(cpuid, vers); 279 break; 280 case IBM970: 281 case IBM970FX: 282 case IBM970MP: 283 cpu_print_speed(); 284 printf("\n"); 285 break; 286 default: 287 printf("\n"); 288 break; 289 } 290 291 printf("cpu%d: HID0 %b\n", cpuid, hid0, bitmask); 292 } 293 294 void 295 cpu_print_speed(void) 296 { 297 uint64_t cps; 298 299 if (cpu_est_clockrate(0, &cps) == 0) 300 printf(", %lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100); 301 } 302 303 /* Get current clock frequency for the given cpu id. */ 304 int 305 cpu_est_clockrate(int cpu_id, uint64_t *cps) 306 { 307 uint16_t vers; 308 register_t msr; 309 310 vers = mfpvr() >> 16; 311 msr = mfmsr(); 312 mtmsr(msr & ~PSL_EE); 313 314 switch (vers) { 315 case MPC7450: 316 case MPC7455: 317 case MPC7457: 318 case MPC750: 319 case IBM750FX: 320 case MPC7400: 321 case MPC7410: 322 case MPC7447A: 323 case MPC7448: 324 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 325 mtspr(SPR_PMC1, 0); 326 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); 327 DELAY(1000); 328 *cps = (mfspr(SPR_PMC1) * 1000) + 4999; 329 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 330 331 mtmsr(msr); 332 return (0); 333 case IBM970: 334 case IBM970FX: 335 case IBM970MP: 336 isync(); 337 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); 338 isync(); 339 mtspr(SPR_970MMCR1, 0); 340 mtspr(SPR_970MMCRA, 0); 341 mtspr(SPR_970PMC1, 0); 342 mtspr(SPR_970MMCR0, 343 SPR_970MMCR0_PMC1SEL(PMC970N_CYCLES)); 344 isync(); 345 DELAY(1000); 346 powerpc_sync(); 347 mtspr(SPR_970MMCR0, SPR_MMCR0_FC); 348 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999; 349 350 mtmsr(msr); 351 return (0); 352 } 353 354 return (ENXIO); 355 } 356 357 void 358 cpu_print_cacheinfo(u_int cpuid, uint16_t vers) 359 { 360 uint32_t hid; 361 362 363 hid = mfspr(SPR_HID0); 364 printf("cpu%u: ", cpuid); 365 printf("L1 I-cache %sabled, ", (hid & HID0_ICE) ? "en" : "dis"); 366 printf("L1 D-cache %sabled\n", (hid & HID0_DCE) ? "en" : "dis"); 367 368 printf("cpu%u: ", cpuid); 369 if (l2cr_config & L2CR_L2E) { 370 switch (vers) { 371 case MPC7450: 372 case MPC7455: 373 case MPC7457: 374 printf("256KB L2 cache, "); 375 if (l3cr_config & L3CR_L3E) 376 printf("%cMB L3 backside cache", 377 l3cr_config & L3CR_L3SIZ ? '2' : '1'); 378 else 379 printf("L3 cache disabled"); 380 printf("\n"); 381 break; 382 case IBM750FX: 383 printf("512KB L2 cache\n"); 384 break; 385 default: 386 switch (l2cr_config & L2CR_L2SIZ) { 387 case L2SIZ_256K: 388 printf("256KB "); 389 break; 390 case L2SIZ_512K: 391 printf("512KB "); 392 break; 393 case L2SIZ_1M: 394 printf("1MB "); 395 break; 396 } 397 printf("write-%s", (l2cr_config & L2CR_L2WT) 398 ? "through" : "back"); 399 if (l2cr_config & L2CR_L2PE) 400 printf(", with parity"); 401 printf(" backside cache\n"); 402 break; 403 } 404 } else 405 printf("L2 cache disabled\n"); 406 }
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