1 /* $NetBSD: db_disasm.c,v 1.28 2013/07/04 23:00:23 joerg Exp $ */
2 /* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */
3
4 #include <sys/cdefs.h>
5 __FBSDID("$FreeBSD$");
6
7 #include <sys/param.h>
8 #include <sys/proc.h>
9 #include <sys/systm.h>
10
11 #include <machine/db_machdep.h>
12
13 #include <ddb/ddb.h>
14 #include <ddb/db_access.h>
15 #include <ddb/db_sym.h>
16 #include <ddb/db_variables.h>
17 #include <ddb/db_output.h>
18
19 enum function_mask {
20 Op_A = 0x00000001,
21 Op_B = 0x00000002,
22 Op_BI = 0x00000004,
23 Op_BO = 0x00000008,
24 Op_BC = Op_BI | Op_BO,
25 Op_CRM = 0x00000010,
26 Op_D = 0x00000020,
27 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */
28 Op_S = 0x00000040, /* S-field is swapped with A-field */
29 Op_FM = Op_D | Op_S, /* kludge (reduce Op_s) */
30 Op_dA = 0x00000080,
31 Op_LK = 0x00000100,
32 Op_Rc = 0x00000200,
33 Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */
34 Op_LKM = Op_AA,
35 Op_RcM = Op_AA,
36 Op_OE = 0x00000400,
37 Op_SR = 0x00000800,
38 Op_TO = 0x00001000,
39 Op_sign = 0x00002000,
40 Op_const = 0x00004000,
41 Op_SIMM = Op_const | Op_sign,
42 Op_UIMM = Op_const,
43 Op_crbA = 0x00008000,
44 Op_crbB = 0x00010000,
45 Op_WS = Op_crbB, /* kludge, same field as crbB */
46 Op_rSH = Op_crbB, /* kludge, same field as crbB */
47 Op_crbD = 0x00020000,
48 Op_crfD = 0x00040000,
49 Op_crfS = 0x00080000,
50 Op_ds = 0x00100000,
51 Op_me = 0x00200000,
52 Op_spr = 0x00400000,
53 Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */
54 Op_tbr = 0x00800000,
55
56 Op_BP = 0x01000000,
57 Op_BD = 0x02000000,
58 Op_LI = 0x04000000,
59 Op_C = 0x08000000,
60
61 Op_NB = 0x10000000,
62
63 Op_sh_mb_sh = 0x20000000,
64 Op_sh = 0x40000000,
65 Op_SH = Op_sh | Op_sh_mb_sh,
66 Op_mb = 0x80000000,
67 Op_MB = Op_mb | Op_sh_mb_sh,
68 Op_ME = Op_MB,
69
70 };
71
72 struct opcode {
73 const char *name;
74 u_int32_t mask;
75 u_int32_t code;
76 enum function_mask func;
77 };
78
79 typedef u_int32_t instr_t;
80 typedef void (op_class_func) (instr_t, vm_offset_t);
81
82 u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width);
83 void disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc,
84 char *disasm_str, size_t slen);
85 void dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc);
86
87 op_class_func op_ill, op_base;
88 op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f;
89 op_class_func op_cl_x3a, op_cl_x3b;
90 op_class_func op_cl_x3e, op_cl_x3f;
91
92 op_class_func *opcodes_base[] = {
93 /*x00*/ op_ill, op_ill, op_base, op_ill,
94 /*x04*/ op_ill, op_ill, op_ill, op_base,
95 /*x08*/ op_base, op_base, op_base, op_base,
96 /*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/,
97 /*x10*/ op_base, op_base, op_base, op_cl_x13,
98 /*x14*/ op_base, op_base, op_ill, op_base,
99 /*x18*/ op_base, op_base, op_base, op_base,
100 /*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f,
101 /*x20*/ op_base, op_base, op_base, op_base,
102 /*x24*/ op_base, op_base, op_base, op_base,
103 /*x28*/ op_base, op_base, op_base, op_base,
104 /*x2C*/ op_base, op_base, op_base, op_base,
105 /*x30*/ op_base, op_base, op_base, op_base,
106 /*x34*/ op_base, op_base, op_base, op_base,
107 /*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b,
108 /*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f
109 };
110
111
112 /* This table could be modified to make significant the "reserved" fields
113 * of the opcodes, But I didn't feel like it when typing in the table,
114 * I would recommend that this table be looked over for errors,
115 * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD)
116 * PowerPC Microprocessor Family: The Programming Environments
117 */
118
119 const struct opcode opcodes[] = {
120 { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM },
121 { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM },
122 { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM },
123 { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM },
124 { "cmplwi", 0xfc200000, 0x28000000, Op_crfD | Op_A | Op_SIMM },
125 { "cmpldi", 0xfc200000, 0x28200000, Op_crfD | Op_A | Op_SIMM },
126 { "cmpwi", 0xfc200000, 0x2c000000, Op_crfD | Op_A | Op_SIMM },
127 { "cmpdi", 0xfc200000, 0x2c200000, Op_crfD | Op_A | Op_SIMM },
128 { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM },
129 { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM },
130 { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM },
131 { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM },
132 { "b", 0xfc000000, 0x40000000, Op_BC | Op_BD | Op_AA | Op_LK }, /* bc */
133 { "sc", 0xffffffff, 0x44000002, 0 },
134 { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK },
135
136 { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc },
137 { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc },
138 { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc },
139
140 { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM },
141 { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM },
142 { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM },
143 { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM },
144
145 { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM },
146 { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM },
147
148 { "lwz", 0xfc000000, 0x80000000, Op_D | Op_dA },
149 { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_dA },
150 { "lbz", 0xfc000000, 0x88000000, Op_D | Op_dA },
151 { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_dA },
152 { "stw", 0xfc000000, 0x90000000, Op_ST | Op_dA },
153 { "stwu", 0xfc000000, 0x94000000, Op_ST | Op_dA },
154 { "stb", 0xfc000000, 0x98000000, Op_ST | Op_dA },
155 { "stbu", 0xfc000000, 0x9c000000, Op_ST | Op_dA },
156
157 { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_dA },
158 { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_dA },
159 { "lha", 0xfc000000, 0xa8000000, Op_D | Op_dA },
160 { "lhau", 0xfc000000, 0xac000000, Op_D | Op_dA },
161 { "sth", 0xfc000000, 0xb0000000, Op_ST | Op_dA },
162 { "sthu", 0xfc000000, 0xb4000000, Op_ST | Op_dA },
163 { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_dA },
164 { "stmw", 0xfc000000, 0xbc000000, Op_ST | Op_dA },
165
166 { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_dA },
167 { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_dA },
168 { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_dA },
169 { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_dA },
170
171 { "stfs", 0xfc000000, 0xd0000000, Op_ST | Op_dA },
172 { "stfsu", 0xfc000000, 0xd4000000, Op_ST | Op_dA },
173 { "stfd", 0xfc000000, 0xd8000000, Op_ST | Op_dA },
174 { "stfdu", 0xfc000000, 0xdc000000, Op_ST | Op_dA },
175 { "", 0x0, 0x0, 0 }
176
177 };
178 /* 13 * 4 = 4c */
179 const struct opcode opcodes_13[] = {
180 /* 0x13 << 2 */
181 { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS },
182 { "b", 0xfc0007fe, 0x4c000020, Op_BC | Op_LK }, /* bclr */
183 { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB },
184 { "rfi", 0xfc0007fe, 0x4c000064, 0 },
185 { "crandc", 0xfc0007fe, 0x4c000102, Op_crbD | Op_crbA | Op_crbB },
186 { "isync", 0xfc0007fe, 0x4c00012c, 0 },
187 { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB },
188 { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB },
189 { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB },
190 { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB },
191 { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB },
192 { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB },
193 { "b", 0xfc0007fe, 0x4c000420, Op_BC | Op_LK }, /* bcctr */
194 { "", 0x0, 0x0, 0 }
195 };
196
197 /* 1e * 4 = 78 */
198 const struct opcode opcodes_1e[] = {
199 { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc },
200 { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc },
201 { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc },
202 { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc },
203 { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc },
204 { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc },
205 { "", 0x0, 0x0, 0 }
206 };
207
208 /* 1f * 4 = 7c */
209 const struct opcode opcodes_1f[] = {
210 /* 1f << 2 */
211 { "cmpw", 0xfc2007fe, 0x7c000000, Op_crfD | Op_A | Op_B },
212 { "cmpd", 0xfc2007fe, 0x7c200000, Op_crfD | Op_A | Op_B },
213 { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B },
214 { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
215 { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc },
216 { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
217 { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc },
218 { "isellt", 0xfc0007ff, 0x7c00001e, Op_D | Op_A | Op_B },
219 { "iselgt", 0xfc0007ff, 0x7c00005e, Op_D | Op_A | Op_B },
220 { "iseleq", 0xfc0007ff, 0x7c00009e, Op_D | Op_A | Op_B },
221
222 { "mfcr", 0xfc0007fe, 0x7c000026, Op_D },
223 { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B },
224 { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B },
225 { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B },
226 { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc },
227 { "cntlzw", 0xfc0007fe, 0x7c000034, Op_D | Op_A | Op_Rc },
228 { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc },
229 { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc },
230 { "cmplw", 0xfc2007fe, 0x7c000040, Op_crfD | Op_A | Op_B },
231 { "cmpld", 0xfc2007fe, 0x7c200040, Op_crfD | Op_A | Op_B },
232 { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
233 { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B },
234 { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B },
235 { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B },
236 { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc },
237 { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc },
238 { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B },
239 { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc },
240 { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc },
241 { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D },
242 { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B },
243 { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B },
244 { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B },
245 { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc },
246 { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B },
247 { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc },
248 { "wrtee", 0xfc0003ff, 0x7c000106, Op_S },
249 { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
250 { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
251 { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM },
252 { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S },
253 { "stdx", 0xfc0007fe, 0x7c00012a, Op_ST | Op_A | Op_B },
254 { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_ST | Op_A | Op_B },
255 { "stwx", 0xfc0007fe, 0x7c00012e, Op_ST | Op_A | Op_B },
256 { "wrteei", 0xfc0003fe, 0x7c000146, 0 }, /* XXX: out of flags! */
257 { "stdux", 0xfc0007fe, 0x7c00016a, Op_ST | Op_A | Op_B },
258 { "stwux", 0xfc0007fe, 0x7c00016e, Op_ST | Op_A | Op_B },
259 { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc },
260 { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc },
261 { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR },
262 { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_ST | Op_A | Op_B },
263 { "stbx", 0xfc0007fe, 0x7c0001ae, Op_ST | Op_A | Op_B },
264 { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc },
265 { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
266 { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc },
267 { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
268 { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B },
269 { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B },
270 { "stbux", 0xfc0007fe, 0x7c0001ee, Op_ST | Op_A | Op_B },
271 { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
272 { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B },
273 { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B },
274 { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc },
275 { "tlbie", 0xfc0007fe, 0x7c000264, Op_B },
276 { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B },
277 { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B },
278 { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc },
279 { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr },
280 { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr },
281 { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B },
282 { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B },
283 { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 },
284 { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr },
285 { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B },
286 { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B },
287 { "sthx", 0xfc0007fe, 0x7c00032e, Op_ST | Op_A | Op_B },
288 { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc },
289 { "ecowx", 0xfc0007fe, 0x7c00036c, Op_ST | Op_A | Op_B | Op_Rc },
290 { "slbie", 0xfc0007fc, 0x7c000364, Op_B },
291 { "sthux", 0xfc0007fe, 0x7c00036e, Op_ST | Op_A | Op_B },
292 { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc },
293 { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr },
294 { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
295 { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
296 { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr },
297 { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B },
298 { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc },
299 { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B },
300 { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc },
301 { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc },
302 { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc },
303 { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD },
304 { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B },
305 { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B },
306 { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B },
307 { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc },
308 { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc },
309 { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 },
310 { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B },
311 { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR },
312 { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB },
313 { "sync", 0xfc0007fe, 0x7c0004ac, 0 },
314 { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B },
315 { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B },
316 { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B },
317 { "stswx", 0xfc0007fe, 0x7c00052a, Op_ST | Op_A | Op_B },
318 { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_ST | Op_A | Op_B },
319 { "stfsx", 0xfc0007fe, 0x7c00052e, Op_ST | Op_A | Op_B },
320 { "stfsux", 0xfc0007fe, 0x7c00056e, Op_ST | Op_A | Op_B },
321 { "stswi", 0xfc0007fe, 0x7c0005aa, Op_ST | Op_A | Op_NB },
322 { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_ST | Op_A | Op_B },
323 { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_ST | Op_A | Op_B },
324 { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B },
325 { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B },
326 { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc },
327 { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_rSH | Op_Rc },
328 { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh },
329 { "eieio", 0xfc0007fe, 0x7c0006ac, 0 },
330 { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc },
331 { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_ST | Op_A | Op_B },
332 { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_Rc },
333 { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS },
334 { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc },
335 { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B },
336 { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS },
337 { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_ST | Op_A | Op_B },
338 { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc },
339 { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B },
340 { "", 0x0, 0x0, 0 }
341 };
342
343 /* 3a * 4 = e8 */
344 const struct opcode opcodes_3a[] = {
345 { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds },
346 { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds },
347 { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds },
348 { "", 0x0, 0x0, 0 }
349 };
350 /* 3b * 4 = ec */
351 const struct opcode opcodes_3b[] = {
352 { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc },
353 { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc },
354
355 { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc },
356 { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc },
357 { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc },
358 { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc },
359 { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc },
360 { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc },
361 { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc },
362 { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc },
363 { "", 0x0, 0x0, 0 }
364 };
365 /* 3e * 4 = f8 */
366 const struct opcode opcodes_3e[] = {
367 { "std", 0xfc000003, 0xf8000000, Op_ST | Op_A | Op_ds },
368 { "stdu", 0xfc000003, 0xf8000001, Op_ST | Op_A | Op_ds },
369 { "", 0x0, 0x0, 0 }
370 };
371
372 /* 3f * 4 = fc */
373 const struct opcode opcodes_3f[] = {
374 { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B },
375 { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc },
376 { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc },
377 { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc },
378
379 { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc },
380 { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc },
381 { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc },
382 { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc },
383 { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc },
384 { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc },
385 { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc },
386 { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc },
387 { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc },
388 { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc },
389 { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc },
390
391 { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B },
392 { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc },
393 { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc },
394 { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc },
395 { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc },
396 { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc },
397 { "mtfsfi", 0xfc0007fe, 0xfc00010c, 0 }, /* XXX: out of flags! */
398
399 { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc },
400 { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc },
401 { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc },
402 { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc },
403 { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc },
404 { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc },
405 { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc },
406 { "", 0x0, 0x0, 0 }
407 };
408
409
410 struct specialreg {
411 int reg;
412 const char *name;
413 };
414
415 const struct specialreg sprregs[] = {
416 { 0x000, "mq" },
417 { 0x001, "xer" },
418 { 0x008, "lr" },
419 { 0x009, "ctr" },
420 { 0x012, "dsisr" },
421 { 0x013, "dar" },
422 { 0x016, "dec" },
423 { 0x019, "sdr1" },
424 { 0x01a, "srr0" },
425 { 0x01b, "srr1" },
426 #ifdef BOOKE_PPC4XX
427 { 0x100, "usprg0" },
428 #else
429 { 0x100, "vrsave" },
430 #endif
431 { 0x110, "sprg0" },
432 { 0x111, "sprg1" },
433 { 0x112, "sprg2" },
434 { 0x113, "sprg3" },
435 { 0x114, "sprg4" },
436 { 0x115, "sprg5" },
437 { 0x116, "sprg6" },
438 { 0x117, "sprg7" },
439 { 0x118, "asr" },
440 { 0x11a, "aer" },
441 { 0x11c, "tbl" },
442 { 0x11d, "tbu" },
443 { 0x11f, "pvr" },
444 { 0x210, "ibat0u" },
445 { 0x211, "ibat0l" },
446 { 0x212, "ibat1u" },
447 { 0x213, "ibat1l" },
448 { 0x214, "ibat2u" },
449 { 0x215, "ibat2l" },
450 { 0x216, "ibat3u" },
451 { 0x217, "ibat3l" },
452 { 0x218, "dbat0u" },
453 { 0x219, "dbat0l" },
454 { 0x21a, "dbat1u" },
455 { 0x21b, "dbat1l" },
456 { 0x21c, "dbat2u" },
457 { 0x21d, "dbat2l" },
458 { 0x21e, "dbat3u" },
459 { 0x21f, "dbat3l" },
460 { 0x230, "ibat4u" },
461 { 0x231, "ibat4l" },
462 { 0x232, "ibat5u" },
463 { 0x233, "ibat5l" },
464 { 0x234, "ibat6u" },
465 { 0x235, "ibat6l" },
466 { 0x236, "ibat7u" },
467 { 0x237, "ibat7l" },
468 { 0x238, "dbat4u" },
469 { 0x239, "dbat4l" },
470 { 0x23a, "dbat5u" },
471 { 0x23b, "dbat5l" },
472 { 0x23c, "dbat6u" },
473 { 0x23d, "dbat6l" },
474 { 0x23e, "dbat7u" },
475 { 0x23f, "dbat7l" },
476 { 0x3b0, "zpr" },
477 { 0x3b1, "pid" },
478 { 0x3b3, "ccr0" },
479 { 0x3b4, "iac3" },
480 { 0x3b5, "iac4" },
481 { 0x3b6, "dvc1" },
482 { 0x3b7, "dvc2" },
483 { 0x3b9, "sgr" },
484 { 0x3ba, "dcwr" },
485 { 0x3bb, "sler" },
486 { 0x3bc, "su0r" },
487 { 0x3bd, "dbcr1" },
488 { 0x3d3, "icdbdr" },
489 { 0x3d4, "esr" },
490 { 0x3d5, "dear" },
491 { 0x3d6, "evpr" },
492 { 0x3d8, "tsr" },
493 { 0x3da, "tcr" },
494 { 0x3db, "pit" },
495 { 0x3de, "srr2" },
496 { 0x3df, "srr3" },
497 #ifdef BOOKE_PPC4XX
498 { 0x3f0, "dbsr" },
499 { 0x3f2, "dbcr0" },
500 { 0x3f4, "iac1" },
501 { 0x3f5, "iac2" },
502 { 0x3f6, "dac1" },
503 { 0x3f7, "dac2" },
504 #else
505 { 0x3f0, "hid0" },
506 { 0x3f1, "hid1" },
507 { 0x3f2, "iabr" },
508 { 0x3f3, "hid2" },
509 { 0x3f5, "dabr" },
510 { 0x3f6, "msscr0" },
511 { 0x3f7, "msscr1" },
512 #endif
513 { 0x3f9, "l2cr" },
514 { 0x3fa, "dccr" },
515 { 0x3fb, "iccr" },
516 { 0x3ff, "pir" },
517 { 0, NULL }
518 };
519
520 const struct specialreg dcrregs[] = {
521 { 0x010, "sdram0_cfgaddr" },
522 { 0x011, "sdram0_cfgdata" },
523 { 0x012, "ebc0_cfgaddr" },
524 { 0x013, "ebc0_cfgdata" },
525 { 0x014, "dcp0_cfgaddr" },
526 { 0x015, "dcp0_cfgdata" },
527 { 0x018, "ocm0_isarc" },
528 { 0x019, "ocm0_iscntl" },
529 { 0x01a, "ocm0_dsarc" },
530 { 0x01b, "ocm0_dscntl" },
531 { 0x084, "plb0_besr" },
532 { 0x086, "plb0_bear" },
533 { 0x087, "plb0_acr" },
534 { 0x0a0, "pob0_besr0" },
535 { 0x0a2, "pob0_bear" },
536 { 0x0a4, "pob0_besr1" },
537 { 0x0b0, "cpc0_pllmr" },
538 { 0x0b1, "cpc0_cr0" },
539 { 0x0b2, "cpc0_cr1" },
540 { 0x0b4, "cpc0_psr" },
541 { 0x0b5, "cpc0_jtagid" },
542 { 0x0b8, "cpc0_sr" },
543 { 0x0b9, "cpc0_er" },
544 { 0x0ba, "cpc0_fr" },
545 { 0x0c0, "uic0_sr" },
546 { 0x0c2, "uic0_er" },
547 { 0x0c3, "uic0_cr" },
548 { 0x0c4, "uic0_pr" },
549 { 0x0c5, "uic0_tr" },
550 { 0x0c6, "uic0_msr" },
551 { 0x0c7, "uic0_vr" },
552 { 0x0c8, "uic0_vcr" },
553 { 0x100, "dma0_cr0" },
554 { 0x101, "dma0_ct0" },
555 { 0x102, "dma0_da0" },
556 { 0x103, "dma0_sa0" },
557 { 0x104, "dma0_sg0" },
558 { 0x108, "dma0_cr1" },
559 { 0x109, "dma0_ct1" },
560 { 0x10a, "dma0_da1" },
561 { 0x10b, "dma0_sa1" },
562 { 0x10c, "dma0_sg1" },
563 { 0x110, "dma0_cr2" },
564 { 0x111, "dma0_ct2" },
565 { 0x112, "dma0_da2" },
566 { 0x113, "dma0_sa2" },
567 { 0x114, "dma0_sg2" },
568 { 0x118, "dma0_cr3" },
569 { 0x119, "dma0_ct3" },
570 { 0x11a, "dma0_da3" },
571 { 0x11b, "dma0_sa3" },
572 { 0x11c, "dma0_sg3" },
573 { 0x120, "dma0_sr" },
574 { 0x123, "dma0_sgc" },
575 { 0x125, "dma0_slp" },
576 { 0x126, "dma0_pol" },
577 { 0x180, "mal0_cfg" },
578 { 0x181, "mal0_esr" },
579 { 0x182, "mal0_ier" },
580 { 0x184, "mal0_txcasr" },
581 { 0x185, "mal0_txcarr" },
582 { 0x186, "mal0_txeobisr" },
583 { 0x187, "mal0_txdeir" },
584 { 0x190, "mal0_rxcasr" },
585 { 0x191, "mal0_rxcarr" },
586 { 0x192, "mal0_rxeobisr" },
587 { 0x193, "mal0_rxdeir" },
588 { 0x1a0, "mal0_txctp0r" },
589 { 0x1a1, "mal0_txctp1r" },
590 { 0x1a2, "mal0_txctp2r" },
591 { 0x1a3, "mal0_txctp3r" },
592 { 0x1c0, "mal0_rxctp0r" },
593 { 0x1e0, "mal0_rcbs0" },
594 { 0, NULL }
595 };
596
597 static const char *condstr[8] = {
598 "ge", "le", "ne", "ns", "lt", "gt", "eq", "so"
599 };
600
601
602 void
603 op_ill(instr_t instr, vm_offset_t loc)
604 {
605 db_printf("illegal instruction %x\n", instr);
606 }
607
608 u_int32_t
609 extract_field(u_int32_t value, u_int32_t base, u_int32_t width)
610 {
611 u_int32_t mask = (1 << width) - 1;
612 return ((value >> base) & mask);
613 }
614
615 const struct opcode * search_op(const struct opcode *);
616
617 void
618 disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc,
619 char *disasm_str, size_t slen)
620 {
621 char * pstr;
622 enum function_mask func;
623 int len;
624
625 #define ADD_LEN(s) do { \
626 len = (s); \
627 slen -= len; \
628 pstr += len; \
629 } while(0)
630 #define APP_PSTR(fmt, arg) ADD_LEN(snprintf(pstr, slen, (fmt), (arg)))
631 #define APP_PSTRS(fmt) ADD_LEN(snprintf(pstr, slen, "%s", (fmt)))
632
633 pstr = disasm_str;
634
635 func = popcode->func;
636 if (func & Op_BC) {
637 u_int BO, BI;
638 BO = extract_field(instr, 31 - 10, 5);
639 BI = extract_field(instr, 31 - 15, 5);
640 func &= ~Op_BC;
641 if (BO & 4) {
642 /* standard, no decrement */
643 if (BO & 16) {
644 if (popcode->code == 0x40000000) {
645 APP_PSTRS("c");
646 func |= Op_BO | Op_BI;
647 }
648 }
649 else {
650 APP_PSTRS(condstr[((BO & 8) >> 1) + (BI & 3)]);
651 if (BI >= 4)
652 func |= Op_crfS;
653 }
654 }
655 else {
656 /* decrement and branch */
657 if (BO & 2)
658 APP_PSTRS("dz");
659 else
660 APP_PSTRS("dnz");
661 if ((BO & 24) == 0)
662 APP_PSTRS("f");
663 else if ((BO & 24) == 8)
664 APP_PSTRS("t");
665 else
666 func |= Op_BI;
667 }
668 if (popcode->code == 0x4c000020)
669 APP_PSTRS("lr");
670 else if (popcode->code == 0x4c000420)
671 APP_PSTRS("ctr");
672 if ((BO & 20) != 20 && (func & Op_BO) == 0)
673 func |= Op_BP; /* branch prediction hint */
674 }
675 if (func & Op_OE) {
676 u_int OE;
677 OE = extract_field(instr, 31 - 21, 1);
678 if (OE) {
679 APP_PSTRS("o");
680 }
681 func &= ~Op_OE;
682 }
683 switch (func & Op_LKM) {
684 case Op_Rc:
685 if (instr & 0x1)
686 APP_PSTRS(".");
687 break;
688 case Op_AA:
689 if (instr & 0x1)
690 APP_PSTRS("l");
691 if (instr & 0x2) {
692 APP_PSTRS("a");
693 loc = 0; /* Absolute address */
694 }
695 break;
696 case Op_LK:
697 if (instr & 0x1)
698 APP_PSTRS("l");
699 break;
700 default:
701 func &= ~Op_LKM;
702 }
703 if (func & Op_BP) {
704 int y;
705 y = (instr & 0x200000) != 0;
706 if (popcode->code == 0x40000000) {
707 int BD;
708 BD = extract_field(instr, 31 - 29, 14);
709 BD = BD << 18;
710 BD = BD >> 16;
711 BD += loc;
712 if ((vm_offset_t)BD < loc)
713 y ^= 1;
714 }
715 APP_PSTR("%c", y ? '+' : '-');
716 func &= ~Op_BP;
717 }
718 APP_PSTRS("\t");
719
720 /* XXX: special cases here, out of flags in a 32bit word. */
721 if (strcmp(popcode->name, "wrteei") == 0) {
722 int E;
723 E = extract_field(instr, 31 - 16, 5);
724 APP_PSTR("%d", E);
725 return;
726 }
727 else if (strcmp(popcode->name, "mtfsfi") == 0) {
728 u_int UI;
729 UI = extract_field(instr, 31 - 8, 3);
730 APP_PSTR("crf%u, ", UI);
731 UI = extract_field(instr, 31 - 19, 4);
732 APP_PSTR("0x%x", UI);
733 }
734 /* XXX: end of special cases here. */
735
736 if ((func & Op_FM) == Op_FM) {
737 u_int FM;
738 FM = extract_field(instr, 31 - 14, 8);
739 APP_PSTR("0x%x, ", FM);
740 func &= ~Op_FM;
741 }
742 if (func & Op_D) { /* Op_ST is the same */
743 u_int D;
744 D = extract_field(instr, 31 - 10, 5);
745 APP_PSTR("r%d, ", D);
746 func &= ~Op_D;
747 }
748 if (func & Op_crbD) {
749 u_int crbD;
750 crbD = extract_field(instr, 31 - 10, 5);
751 APP_PSTR("crb%d, ", crbD);
752 func &= ~Op_crbD;
753 }
754 if (func & Op_crfD) {
755 u_int crfD;
756 crfD = extract_field(instr, 31 - 8, 3);
757 APP_PSTR("crf%d, ", crfD);
758 func &= ~Op_crfD;
759 }
760 if (func & Op_TO) {
761 u_int TO;
762 TO = extract_field(instr, 31 - 10, 1);
763 APP_PSTR("%d, ", TO);
764 func &= ~Op_TO;
765 }
766 if (func & Op_crfS) {
767 u_int crfS;
768 crfS = extract_field(instr, 31 - 13, 3);
769 APP_PSTR("crf%d, ", crfS);
770 func &= ~Op_crfS;
771 }
772 if (func & Op_CRM) {
773 u_int CRM;
774 CRM = extract_field(instr, 31 - 19, 8);
775 APP_PSTR("0x%x, ", CRM);
776 func &= ~Op_CRM;
777 }
778 if (func & Op_BO) {
779 u_int BO;
780 BO = extract_field(instr, 31 - 10, 5);
781 APP_PSTR("%d, ", BO);
782 func &= ~Op_BO;
783 }
784 if (func & Op_BI) {
785 u_int BI;
786 BI = extract_field(instr, 31 - 15, 5);
787 APP_PSTR("%d, ", BI);
788 func &= ~Op_BI;
789 }
790 if (func & Op_dA) { /* register A indirect with displacement */
791 u_int A;
792 A = extract_field(instr, 31 - 31, 16);
793 if (A & 0x8000) {
794 APP_PSTRS("-");
795 A = 0x10000-A;
796 }
797 APP_PSTR("0x%x", A);
798 A = extract_field(instr, 31 - 15, 5);
799 APP_PSTR("(r%d)", A);
800 func &= ~Op_dA;
801 }
802 if (func & Op_spr) {
803 u_int spr;
804 u_int sprl;
805 u_int sprh;
806 const struct specialreg *regs;
807 int i;
808 sprl = extract_field(instr, 31 - 15, 5);
809 sprh = extract_field(instr, 31 - 20, 5);
810 spr = sprh << 5 | sprl;
811
812 /* ugly hack - out of bitfields in the function mask */
813 if (popcode->name[2] == 'd') /* m.Dcr */
814 regs = dcrregs;
815 else
816 regs = sprregs;
817 for (i = 0; regs[i].name != NULL; i++)
818 if (spr == regs[i].reg)
819 break;
820 if (regs[i].name == NULL)
821 APP_PSTR("[unknown special reg (%d)]", spr);
822 else
823 APP_PSTR("%s", regs[i].name);
824
825 if (popcode->name[1] == 't') /* spr is destination */
826 APP_PSTRS(", ");
827 func &= ~Op_spr;
828 }
829 if (func & Op_SR) {
830 u_int SR;
831 SR = extract_field(instr, 31 - 15, 3);
832 APP_PSTR("sr%d", SR);
833 if (popcode->name[1] == 't') /* SR is destination */
834 APP_PSTRS(", ");
835 func &= ~Op_SR;
836 }
837 if (func & Op_A) {
838 u_int A;
839 A = extract_field(instr, 31 - 15, 5);
840 APP_PSTR("r%d, ", A);
841 func &= ~Op_A;
842 }
843 if (func & Op_S) {
844 u_int D;
845 D = extract_field(instr, 31 - 10, 5);
846 APP_PSTR("r%d, ", D);
847 func &= ~Op_S;
848 }
849 if (func & Op_C) {
850 u_int C;
851 C = extract_field(instr, 31 - 25, 5);
852 APP_PSTR("r%d, ", C);
853 func &= ~Op_C;
854 }
855 if (func & Op_B) {
856 u_int B;
857 B = extract_field(instr, 31 - 20, 5);
858 APP_PSTR("r%d", B);
859 func &= ~Op_B;
860 }
861 if (func & Op_crbA) {
862 u_int crbA;
863 crbA = extract_field(instr, 31 - 15, 5);
864 APP_PSTR("%d, ", crbA);
865 func &= ~Op_crbA;
866 }
867 if (func & Op_crbB) {
868 u_int crbB;
869 crbB = extract_field(instr, 31 - 20, 5);
870 APP_PSTR("%d, ", crbB);
871 func &= ~Op_crbB;
872 }
873 if (func & Op_LI) {
874 int LI;
875 LI = extract_field(instr, 31 - 29, 24);
876 LI = LI << 8;
877 LI = LI >> 6;
878 LI += loc;
879 APP_PSTR("0x%x", LI);
880 func &= ~Op_LI;
881 }
882 switch (func & Op_SIMM) {
883 u_int IMM;
884 case Op_SIMM: /* same as Op_d */
885 IMM = extract_field(instr, 31 - 31, 16);
886 if (IMM & 0x8000) {
887 APP_PSTRS("-");
888 IMM = 0x10000-IMM;
889 }
890 func &= ~Op_SIMM;
891 goto common;
892 case Op_UIMM:
893 IMM = extract_field(instr, 31 - 31, 16);
894 func &= ~Op_UIMM;
895 goto common;
896 common:
897 APP_PSTR("0x%x", IMM);
898 break;
899 default:
900 ;
901 }
902 if (func & Op_BD) {
903 int BD;
904 BD = extract_field(instr, 31 - 29, 14);
905 BD = BD << 18;
906 BD = BD >> 16;
907 BD += loc;
908 /* Need to sign extend and shift up 2, then add addr */
909 APP_PSTR("0x%x", BD);
910 func &= ~Op_BD;
911 }
912 if (func & Op_ds) {
913 u_int ds;
914 ds = extract_field(instr, 31 - 29, 14) << 2;
915 APP_PSTR("0x%x", ds);
916 func &= ~Op_ds;
917 }
918 if (func & Op_me) {
919 u_int me, mel, meh;
920 mel = extract_field(instr, 31 - 25, 4);
921 meh = extract_field(instr, 31 - 26, 1);
922 me = meh << 4 | mel;
923 APP_PSTR(", 0x%x", me);
924 func &= ~Op_me;
925 }
926 if ((func & Op_SH) && (func & Op_sh_mb_sh)) {
927 u_int SH;
928 SH = extract_field(instr, 31 - 20, 5);
929 APP_PSTR("%d", SH);
930 }
931 if ((func & Op_MB) && (func & Op_sh_mb_sh)) {
932 u_int MB;
933 u_int ME;
934 MB = extract_field(instr, 31 - 25, 5);
935 APP_PSTR(", %d", MB);
936 ME = extract_field(instr, 31 - 30, 5);
937 APP_PSTR(", %d", ME);
938 }
939 if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) {
940 u_int sh, shl, shh;
941 shl = extract_field(instr, 31 - 19, 4);
942 shh = extract_field(instr, 31 - 20, 1);
943 sh = shh << 4 | shl;
944 APP_PSTR(", %d", sh);
945 }
946 if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) {
947 u_int mb, mbl, mbh;
948 mbl = extract_field(instr, 31 - 25, 4);
949 mbh = extract_field(instr, 31 - 26, 1);
950 mb = mbh << 4 | mbl;
951 APP_PSTR(", %d", mb);
952 }
953 if ((func & Op_me) && ! (func & Op_sh_mb_sh)) {
954 u_int me, mel, meh;
955 mel = extract_field(instr, 31 - 25, 4);
956 meh = extract_field(instr, 31 - 26, 1);
957 me = meh << 4 | mel;
958 APP_PSTR(", %d", me);
959 }
960 if (func & Op_tbr) {
961 u_int tbr;
962 u_int tbrl;
963 u_int tbrh;
964 const char *reg;
965 tbrl = extract_field(instr, 31 - 15, 5);
966 tbrh = extract_field(instr, 31 - 20, 5);
967 tbr = tbrh << 5 | tbrl;
968
969 switch (tbr) {
970 case 268:
971 reg = "tbl";
972 break;
973 case 269:
974 reg = "tbu";
975 break;
976 default:
977 reg = NULL;
978 }
979 if (reg == NULL)
980 APP_PSTR(", [unknown tbr %d ]", tbr);
981 else
982 APP_PSTR(", %s", reg);
983 func &= ~Op_tbr;
984 }
985 if (func & Op_NB) {
986 u_int NB;
987 NB = extract_field(instr, 31 - 20, 5);
988 if (NB == 0)
989 NB = 32;
990 APP_PSTR(", %d", NB);
991 func &= ~Op_SR;
992 }
993 #undef ADD_LEN
994 #undef APP_PSTR
995 #undef APP_PSTRS
996 }
997
998 void
999 op_base(instr_t instr, vm_offset_t loc)
1000 {
1001 dis_ppc(opcodes, instr, loc);
1002 }
1003
1004 void
1005 op_cl_x13(instr_t instr, vm_offset_t loc)
1006 {
1007 dis_ppc(opcodes_13, instr, loc);
1008 }
1009
1010 void
1011 op_cl_x1e(instr_t instr, vm_offset_t loc)
1012 {
1013 dis_ppc(opcodes_1e, instr, loc);
1014 }
1015
1016 void
1017 op_cl_x1f(instr_t instr, vm_offset_t loc)
1018 {
1019 dis_ppc(opcodes_1f, instr, loc);
1020 }
1021
1022 void
1023 op_cl_x3a(instr_t instr, vm_offset_t loc)
1024 {
1025 dis_ppc(opcodes_3a, instr, loc);
1026 }
1027
1028 void
1029 op_cl_x3b(instr_t instr, vm_offset_t loc)
1030 {
1031 dis_ppc(opcodes_3b, instr, loc);
1032 }
1033
1034 void
1035 op_cl_x3e(instr_t instr, vm_offset_t loc)
1036 {
1037 dis_ppc(opcodes_3e, instr, loc);
1038 }
1039
1040 void
1041 op_cl_x3f(instr_t instr, vm_offset_t loc)
1042 {
1043 dis_ppc(opcodes_3f, instr, loc);
1044 }
1045
1046 void
1047 dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc)
1048 {
1049 const struct opcode *op;
1050 int found = 0;
1051 int i;
1052 char disasm_str[80];
1053
1054 for (i = 0, op = &opcodeset[0];
1055 found == 0 && op->mask != 0;
1056 i++, op = &opcodeset[i]) {
1057 if ((instr & op->mask) == op->code) {
1058 found = 1;
1059 disasm_fields(op, instr, loc, disasm_str,
1060 sizeof disasm_str);
1061 db_printf("%s%s\n", op->name, disasm_str);
1062 return;
1063 }
1064 }
1065 op_ill(instr, loc);
1066 }
1067
1068 db_addr_t
1069 db_disasm(db_addr_t loc, bool extended)
1070 {
1071 int class;
1072 instr_t opcode;
1073 opcode = *(instr_t *)(loc);
1074 class = opcode >> 26;
1075 (opcodes_base[class])(opcode, loc);
1076
1077 return (loc + 4);
1078 }
1079
1080 vm_offset_t opc_disasm(vm_offset_t loc, int);
1081
1082 vm_offset_t
1083 opc_disasm(vm_offset_t loc, int xin)
1084 {
1085 int class;
1086 instr_t opcode;
1087 opcode = xin;
1088 class = opcode >> 26;
1089 (opcodes_base[class])(opcode, loc);
1090
1091 return (loc + 4);
1092 }
Cache object: 3390a6365fe0eefac2fd31eefb7f1637
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