Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/powerpc/powerpc/db_disasm.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: db_disasm.c,v 1.28 2013/07/04 23:00:23 joerg Exp $ */ 2 /* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */ 3 4 #include <sys/cdefs.h> 5 __FBSDID("$FreeBSD: releng/12.0/sys/powerpc/powerpc/db_disasm.c 337562 2018-08-10 03:28:40Z jhibbits $"); 6 7 #include <sys/param.h> 8 #include <sys/proc.h> 9 #include <sys/systm.h> 10 11 #include <machine/db_machdep.h> 12 13 #include <ddb/ddb.h> 14 #include <ddb/db_access.h> 15 #include <ddb/db_sym.h> 16 #include <ddb/db_variables.h> 17 #include <ddb/db_output.h> 18 19 enum function_mask { 20 Op_A = 0x00000001, 21 Op_B = 0x00000002, 22 Op_BI = 0x00000004, 23 Op_BO = 0x00000008, 24 Op_BC = Op_BI | Op_BO, 25 Op_CRM = 0x00000010, 26 Op_D = 0x00000020, 27 Op_ST = 0x00000020, /* Op_S for store-operations, same as D */ 28 Op_S = 0x00000040, /* S-field is swapped with A-field */ 29 Op_FM = Op_D | Op_S, /* kludge (reduce Op_s) */ 30 Op_dA = 0x00000080, 31 Op_LK = 0x00000100, 32 Op_Rc = 0x00000200, 33 Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */ 34 Op_LKM = Op_AA, 35 Op_RcM = Op_AA, 36 Op_OE = 0x00000400, 37 Op_SR = 0x00000800, 38 Op_TO = 0x00001000, 39 Op_sign = 0x00002000, 40 Op_const = 0x00004000, 41 Op_SIMM = Op_const | Op_sign, 42 Op_UIMM = Op_const, 43 Op_crbA = 0x00008000, 44 Op_crbB = 0x00010000, 45 Op_WS = Op_crbB, /* kludge, same field as crbB */ 46 Op_rSH = Op_crbB, /* kludge, same field as crbB */ 47 Op_crbD = 0x00020000, 48 Op_crfD = 0x00040000, 49 Op_crfS = 0x00080000, 50 Op_ds = 0x00100000, 51 Op_me = 0x00200000, 52 Op_spr = 0x00400000, 53 Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */ 54 Op_tbr = 0x00800000, 55 56 Op_BP = 0x01000000, 57 Op_BD = 0x02000000, 58 Op_LI = 0x04000000, 59 Op_C = 0x08000000, 60 61 Op_NB = 0x10000000, 62 63 Op_sh_mb_sh = 0x20000000, 64 Op_sh = 0x40000000, 65 Op_SH = Op_sh | Op_sh_mb_sh, 66 Op_mb = 0x80000000, 67 Op_MB = Op_mb | Op_sh_mb_sh, 68 Op_ME = Op_MB, 69 70 }; 71 72 struct opcode { 73 const char *name; 74 u_int32_t mask; 75 u_int32_t code; 76 enum function_mask func; 77 }; 78 79 typedef u_int32_t instr_t; 80 typedef void (op_class_func) (instr_t, vm_offset_t); 81 82 u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width); 83 void disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 84 char *disasm_str, size_t slen); 85 void dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc); 86 87 op_class_func op_ill, op_base; 88 op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f; 89 op_class_func op_cl_x3a, op_cl_x3b; 90 op_class_func op_cl_x3e, op_cl_x3f; 91 92 op_class_func *opcodes_base[] = { 93 /*x00*/ op_ill, op_ill, op_base, op_ill, 94 /*x04*/ op_ill, op_ill, op_ill, op_base, 95 /*x08*/ op_base, op_base, op_base, op_base, 96 /*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/, 97 /*x10*/ op_base, op_base, op_base, op_cl_x13, 98 /*x14*/ op_base, op_base, op_ill, op_base, 99 /*x18*/ op_base, op_base, op_base, op_base, 100 /*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f, 101 /*x20*/ op_base, op_base, op_base, op_base, 102 /*x24*/ op_base, op_base, op_base, op_base, 103 /*x28*/ op_base, op_base, op_base, op_base, 104 /*x2C*/ op_base, op_base, op_base, op_base, 105 /*x30*/ op_base, op_base, op_base, op_base, 106 /*x34*/ op_base, op_base, op_base, op_base, 107 /*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b, 108 /*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f 109 }; 110 111 112 /* This table could be modified to make significant the "reserved" fields 113 * of the opcodes, But I didn't feel like it when typing in the table, 114 * I would recommend that this table be looked over for errors, 115 * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD) 116 * PowerPC Microprocessor Family: The Programming Environments 117 */ 118 119 const struct opcode opcodes[] = { 120 { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM }, 121 { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM }, 122 { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM }, 123 { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM }, 124 { "cmplwi", 0xfc200000, 0x28000000, Op_crfD | Op_A | Op_SIMM }, 125 { "cmpldi", 0xfc200000, 0x28200000, Op_crfD | Op_A | Op_SIMM }, 126 { "cmpwi", 0xfc200000, 0x2c000000, Op_crfD | Op_A | Op_SIMM }, 127 { "cmpdi", 0xfc200000, 0x2c200000, Op_crfD | Op_A | Op_SIMM }, 128 { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM }, 129 { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM }, 130 { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM }, 131 { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM }, 132 { "b", 0xfc000000, 0x40000000, Op_BC | Op_BD | Op_AA | Op_LK }, /* bc */ 133 { "sc", 0xffffffff, 0x44000002, 0 }, 134 { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK }, 135 136 { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 137 { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 138 { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, 139 140 { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM }, 141 { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM }, 142 { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM }, 143 { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM }, 144 145 { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM }, 146 { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM }, 147 148 { "lwz", 0xfc000000, 0x80000000, Op_D | Op_dA }, 149 { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_dA }, 150 { "lbz", 0xfc000000, 0x88000000, Op_D | Op_dA }, 151 { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_dA }, 152 { "stw", 0xfc000000, 0x90000000, Op_ST | Op_dA }, 153 { "stwu", 0xfc000000, 0x94000000, Op_ST | Op_dA }, 154 { "stb", 0xfc000000, 0x98000000, Op_ST | Op_dA }, 155 { "stbu", 0xfc000000, 0x9c000000, Op_ST | Op_dA }, 156 157 { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_dA }, 158 { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_dA }, 159 { "lha", 0xfc000000, 0xa8000000, Op_D | Op_dA }, 160 { "lhau", 0xfc000000, 0xac000000, Op_D | Op_dA }, 161 { "sth", 0xfc000000, 0xb0000000, Op_ST | Op_dA }, 162 { "sthu", 0xfc000000, 0xb4000000, Op_ST | Op_dA }, 163 { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_dA }, 164 { "stmw", 0xfc000000, 0xbc000000, Op_ST | Op_dA }, 165 166 { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_dA }, 167 { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_dA }, 168 { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_dA }, 169 { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_dA }, 170 171 { "stfs", 0xfc000000, 0xd0000000, Op_ST | Op_dA }, 172 { "stfsu", 0xfc000000, 0xd4000000, Op_ST | Op_dA }, 173 { "stfd", 0xfc000000, 0xd8000000, Op_ST | Op_dA }, 174 { "stfdu", 0xfc000000, 0xdc000000, Op_ST | Op_dA }, 175 { "", 0x0, 0x0, 0 } 176 177 }; 178 /* 13 * 4 = 4c */ 179 const struct opcode opcodes_13[] = { 180 /* 0x13 << 2 */ 181 { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS }, 182 { "b", 0xfc0007fe, 0x4c000020, Op_BC | Op_LK }, /* bclr */ 183 { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB }, 184 { "rfi", 0xfc0007fe, 0x4c000064, 0 }, 185 { "crandc", 0xfc0007fe, 0x4c000102, Op_crbD | Op_crbA | Op_crbB }, 186 { "isync", 0xfc0007fe, 0x4c00012c, 0 }, 187 { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB }, 188 { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB }, 189 { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB }, 190 { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB }, 191 { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB }, 192 { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB }, 193 { "b", 0xfc0007fe, 0x4c000420, Op_BC | Op_LK }, /* bcctr */ 194 { "", 0x0, 0x0, 0 } 195 }; 196 197 /* 1e * 4 = 78 */ 198 const struct opcode opcodes_1e[] = { 199 { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 200 { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc }, 201 { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 202 { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, 203 { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc }, 204 { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc }, 205 { "", 0x0, 0x0, 0 } 206 }; 207 208 /* 1f * 4 = 7c */ 209 const struct opcode opcodes_1f[] = { 210 /* 1f << 2 */ 211 { "cmpw", 0xfc2007fe, 0x7c000000, Op_crfD | Op_A | Op_B }, 212 { "cmpd", 0xfc2007fe, 0x7c200000, Op_crfD | Op_A | Op_B }, 213 { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B }, 214 { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 215 { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc }, 216 { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 217 { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc }, 218 { "isellt", 0xfc0007ff, 0x7c00001e, Op_D | Op_A | Op_B }, 219 { "iselgt", 0xfc0007ff, 0x7c00005e, Op_D | Op_A | Op_B }, 220 { "iseleq", 0xfc0007ff, 0x7c00009e, Op_D | Op_A | Op_B }, 221 222 { "mfcr", 0xfc0007fe, 0x7c000026, Op_D }, 223 { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B }, 224 { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B }, 225 { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B }, 226 { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc }, 227 { "cntlzw", 0xfc0007fe, 0x7c000034, Op_D | Op_A | Op_Rc }, 228 { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc }, 229 { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc }, 230 { "cmplw", 0xfc2007fe, 0x7c000040, Op_crfD | Op_A | Op_B }, 231 { "cmpld", 0xfc2007fe, 0x7c200040, Op_crfD | Op_A | Op_B }, 232 { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 233 { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B }, 234 { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B }, 235 { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B }, 236 { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc }, 237 { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc }, 238 { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B }, 239 { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc }, 240 { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc }, 241 { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D }, 242 { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B }, 243 { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B }, 244 { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B }, 245 { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc }, 246 { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B }, 247 { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc }, 248 { "wrtee", 0xfc0003ff, 0x7c000106, Op_S }, 249 { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 250 { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 251 { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM }, 252 { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S }, 253 { "stdx", 0xfc0007fe, 0x7c00012a, Op_ST | Op_A | Op_B }, 254 { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_ST | Op_A | Op_B }, 255 { "stwx", 0xfc0007fe, 0x7c00012e, Op_ST | Op_A | Op_B }, 256 { "wrteei", 0xfc0003fe, 0x7c000146, 0 }, /* XXX: out of flags! */ 257 { "stdux", 0xfc0007fe, 0x7c00016a, Op_ST | Op_A | Op_B }, 258 { "stwux", 0xfc0007fe, 0x7c00016e, Op_ST | Op_A | Op_B }, 259 { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc }, 260 { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc }, 261 { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR }, 262 { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_ST | Op_A | Op_B }, 263 { "stbx", 0xfc0007fe, 0x7c0001ae, Op_ST | Op_A | Op_B }, 264 { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc }, 265 { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 266 { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc }, 267 { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 268 { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B }, 269 { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B }, 270 { "stbux", 0xfc0007fe, 0x7c0001ee, Op_ST | Op_A | Op_B }, 271 { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 272 { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B }, 273 { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B }, 274 { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc }, 275 { "tlbie", 0xfc0007fe, 0x7c000264, Op_B }, 276 { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B }, 277 { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B }, 278 { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc }, 279 { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr }, 280 { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr }, 281 { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B }, 282 { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B }, 283 { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 }, 284 { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr }, 285 { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B }, 286 { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B }, 287 { "sthx", 0xfc0007fe, 0x7c00032e, Op_ST | Op_A | Op_B }, 288 { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc }, 289 { "ecowx", 0xfc0007fe, 0x7c00036c, Op_ST | Op_A | Op_B | Op_Rc }, 290 { "slbie", 0xfc0007fc, 0x7c000364, Op_B }, 291 { "sthux", 0xfc0007fe, 0x7c00036e, Op_ST | Op_A | Op_B }, 292 { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc }, 293 { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr }, 294 { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 295 { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, 296 { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr }, 297 { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B }, 298 { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc }, 299 { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B }, 300 { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 301 { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 302 { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, 303 { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD }, 304 { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B }, 305 { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B }, 306 { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B }, 307 { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc }, 308 { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc }, 309 { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 }, 310 { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, 311 { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, 312 { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, 313 { "sync", 0xfc6007fe, 0x7c0004ac, 0 }, 314 { "lwsync", 0xfc6007fe, 0x7c2004ac, 0 }, 315 { "ptesync", 0xfc6007fe, 0x7c4004ac, 0 }, 316 { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, 317 { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, 318 { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B }, 319 { "stswx", 0xfc0007fe, 0x7c00052a, Op_ST | Op_A | Op_B }, 320 { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_ST | Op_A | Op_B }, 321 { "stfsx", 0xfc0007fe, 0x7c00052e, Op_ST | Op_A | Op_B }, 322 { "stfsux", 0xfc0007fe, 0x7c00056e, Op_ST | Op_A | Op_B }, 323 { "stswi", 0xfc0007fe, 0x7c0005aa, Op_ST | Op_A | Op_NB }, 324 { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_ST | Op_A | Op_B }, 325 { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_ST | Op_A | Op_B }, 326 { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B }, 327 { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B }, 328 { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc }, 329 { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_rSH | Op_Rc }, 330 { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh }, 331 { "eieio", 0xfc0007fe, 0x7c0006ac, 0 }, 332 { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc }, 333 { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_ST | Op_A | Op_B }, 334 { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_Rc }, 335 { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS }, 336 { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc }, 337 { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B }, 338 { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS }, 339 { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_ST | Op_A | Op_B }, 340 { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc }, 341 { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B }, 342 { "", 0x0, 0x0, 0 } 343 }; 344 345 /* 3a * 4 = e8 */ 346 const struct opcode opcodes_3a[] = { 347 { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds }, 348 { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds }, 349 { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds }, 350 { "", 0x0, 0x0, 0 } 351 }; 352 /* 3b * 4 = ec */ 353 const struct opcode opcodes_3b[] = { 354 { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc }, 355 { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc }, 356 357 { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc }, 358 { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc }, 359 { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc }, 360 { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc }, 361 { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 362 { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 363 { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 364 { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 365 { "", 0x0, 0x0, 0 } 366 }; 367 /* 3e * 4 = f8 */ 368 const struct opcode opcodes_3e[] = { 369 { "std", 0xfc000003, 0xf8000000, Op_ST | Op_A | Op_ds }, 370 { "stdu", 0xfc000003, 0xf8000001, Op_ST | Op_A | Op_ds }, 371 { "", 0x0, 0x0, 0 } 372 }; 373 374 /* 3f * 4 = fc */ 375 const struct opcode opcodes_3f[] = { 376 { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B }, 377 { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc }, 378 { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc }, 379 { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc }, 380 381 { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc }, 382 { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc }, 383 { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc }, 384 { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc }, 385 { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 386 { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc }, 387 { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc }, 388 { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 389 { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 390 { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 391 { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, 392 393 { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B }, 394 { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc }, 395 { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc }, 396 { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc }, 397 { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc }, 398 { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc }, 399 { "mtfsfi", 0xfc0007fe, 0xfc00010c, 0 }, /* XXX: out of flags! */ 400 401 { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc }, 402 { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc }, 403 { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc }, 404 { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc }, 405 { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc }, 406 { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc }, 407 { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc }, 408 { "", 0x0, 0x0, 0 } 409 }; 410 411 412 struct specialreg { 413 int reg; 414 const char *name; 415 }; 416 417 const struct specialreg sprregs[] = { 418 { 0x000, "mq" }, 419 { 0x001, "xer" }, 420 { 0x008, "lr" }, 421 { 0x009, "ctr" }, 422 { 0x012, "dsisr" }, 423 { 0x013, "dar" }, 424 { 0x016, "dec" }, 425 { 0x019, "sdr1" }, 426 { 0x01a, "srr0" }, 427 { 0x01b, "srr1" }, 428 #ifdef BOOKE_PPC4XX 429 { 0x100, "usprg0" }, 430 #else 431 { 0x100, "vrsave" }, 432 #endif 433 { 0x110, "sprg0" }, 434 { 0x111, "sprg1" }, 435 { 0x112, "sprg2" }, 436 { 0x113, "sprg3" }, 437 { 0x114, "sprg4" }, 438 { 0x115, "sprg5" }, 439 { 0x116, "sprg6" }, 440 { 0x117, "sprg7" }, 441 { 0x118, "asr" }, 442 { 0x11a, "aer" }, 443 { 0x11c, "tbl" }, 444 { 0x11d, "tbu" }, 445 { 0x11f, "pvr" }, 446 { 0x210, "ibat0u" }, 447 { 0x211, "ibat0l" }, 448 { 0x212, "ibat1u" }, 449 { 0x213, "ibat1l" }, 450 { 0x214, "ibat2u" }, 451 { 0x215, "ibat2l" }, 452 { 0x216, "ibat3u" }, 453 { 0x217, "ibat3l" }, 454 { 0x218, "dbat0u" }, 455 { 0x219, "dbat0l" }, 456 { 0x21a, "dbat1u" }, 457 { 0x21b, "dbat1l" }, 458 { 0x21c, "dbat2u" }, 459 { 0x21d, "dbat2l" }, 460 { 0x21e, "dbat3u" }, 461 { 0x21f, "dbat3l" }, 462 { 0x230, "ibat4u" }, 463 { 0x231, "ibat4l" }, 464 { 0x232, "ibat5u" }, 465 { 0x233, "ibat5l" }, 466 { 0x234, "ibat6u" }, 467 { 0x235, "ibat6l" }, 468 { 0x236, "ibat7u" }, 469 { 0x237, "ibat7l" }, 470 { 0x238, "dbat4u" }, 471 { 0x239, "dbat4l" }, 472 { 0x23a, "dbat5u" }, 473 { 0x23b, "dbat5l" }, 474 { 0x23c, "dbat6u" }, 475 { 0x23d, "dbat6l" }, 476 { 0x23e, "dbat7u" }, 477 { 0x23f, "dbat7l" }, 478 { 0x3b0, "zpr" }, 479 { 0x3b1, "pid" }, 480 { 0x3b3, "ccr0" }, 481 { 0x3b4, "iac3" }, 482 { 0x3b5, "iac4" }, 483 { 0x3b6, "dvc1" }, 484 { 0x3b7, "dvc2" }, 485 { 0x3b9, "sgr" }, 486 { 0x3ba, "dcwr" }, 487 { 0x3bb, "sler" }, 488 { 0x3bc, "su0r" }, 489 { 0x3bd, "dbcr1" }, 490 { 0x3d3, "icdbdr" }, 491 { 0x3d4, "esr" }, 492 { 0x3d5, "dear" }, 493 { 0x3d6, "evpr" }, 494 { 0x3d8, "tsr" }, 495 { 0x3da, "tcr" }, 496 { 0x3db, "pit" }, 497 { 0x3de, "srr2" }, 498 { 0x3df, "srr3" }, 499 #ifdef BOOKE_PPC4XX 500 { 0x3f0, "dbsr" }, 501 { 0x3f2, "dbcr0" }, 502 { 0x3f4, "iac1" }, 503 { 0x3f5, "iac2" }, 504 { 0x3f6, "dac1" }, 505 { 0x3f7, "dac2" }, 506 #else 507 { 0x3f0, "hid0" }, 508 { 0x3f1, "hid1" }, 509 { 0x3f2, "iabr" }, 510 { 0x3f3, "hid2" }, 511 { 0x3f5, "dabr" }, 512 { 0x3f6, "msscr0" }, 513 { 0x3f7, "msscr1" }, 514 #endif 515 { 0x3f9, "l2cr" }, 516 { 0x3fa, "dccr" }, 517 { 0x3fb, "iccr" }, 518 { 0x3ff, "pir" }, 519 { 0, NULL } 520 }; 521 522 const struct specialreg dcrregs[] = { 523 { 0x010, "sdram0_cfgaddr" }, 524 { 0x011, "sdram0_cfgdata" }, 525 { 0x012, "ebc0_cfgaddr" }, 526 { 0x013, "ebc0_cfgdata" }, 527 { 0x014, "dcp0_cfgaddr" }, 528 { 0x015, "dcp0_cfgdata" }, 529 { 0x018, "ocm0_isarc" }, 530 { 0x019, "ocm0_iscntl" }, 531 { 0x01a, "ocm0_dsarc" }, 532 { 0x01b, "ocm0_dscntl" }, 533 { 0x084, "plb0_besr" }, 534 { 0x086, "plb0_bear" }, 535 { 0x087, "plb0_acr" }, 536 { 0x0a0, "pob0_besr0" }, 537 { 0x0a2, "pob0_bear" }, 538 { 0x0a4, "pob0_besr1" }, 539 { 0x0b0, "cpc0_pllmr" }, 540 { 0x0b1, "cpc0_cr0" }, 541 { 0x0b2, "cpc0_cr1" }, 542 { 0x0b4, "cpc0_psr" }, 543 { 0x0b5, "cpc0_jtagid" }, 544 { 0x0b8, "cpc0_sr" }, 545 { 0x0b9, "cpc0_er" }, 546 { 0x0ba, "cpc0_fr" }, 547 { 0x0c0, "uic0_sr" }, 548 { 0x0c2, "uic0_er" }, 549 { 0x0c3, "uic0_cr" }, 550 { 0x0c4, "uic0_pr" }, 551 { 0x0c5, "uic0_tr" }, 552 { 0x0c6, "uic0_msr" }, 553 { 0x0c7, "uic0_vr" }, 554 { 0x0c8, "uic0_vcr" }, 555 { 0x100, "dma0_cr0" }, 556 { 0x101, "dma0_ct0" }, 557 { 0x102, "dma0_da0" }, 558 { 0x103, "dma0_sa0" }, 559 { 0x104, "dma0_sg0" }, 560 { 0x108, "dma0_cr1" }, 561 { 0x109, "dma0_ct1" }, 562 { 0x10a, "dma0_da1" }, 563 { 0x10b, "dma0_sa1" }, 564 { 0x10c, "dma0_sg1" }, 565 { 0x110, "dma0_cr2" }, 566 { 0x111, "dma0_ct2" }, 567 { 0x112, "dma0_da2" }, 568 { 0x113, "dma0_sa2" }, 569 { 0x114, "dma0_sg2" }, 570 { 0x118, "dma0_cr3" }, 571 { 0x119, "dma0_ct3" }, 572 { 0x11a, "dma0_da3" }, 573 { 0x11b, "dma0_sa3" }, 574 { 0x11c, "dma0_sg3" }, 575 { 0x120, "dma0_sr" }, 576 { 0x123, "dma0_sgc" }, 577 { 0x125, "dma0_slp" }, 578 { 0x126, "dma0_pol" }, 579 { 0x180, "mal0_cfg" }, 580 { 0x181, "mal0_esr" }, 581 { 0x182, "mal0_ier" }, 582 { 0x184, "mal0_txcasr" }, 583 { 0x185, "mal0_txcarr" }, 584 { 0x186, "mal0_txeobisr" }, 585 { 0x187, "mal0_txdeir" }, 586 { 0x190, "mal0_rxcasr" }, 587 { 0x191, "mal0_rxcarr" }, 588 { 0x192, "mal0_rxeobisr" }, 589 { 0x193, "mal0_rxdeir" }, 590 { 0x1a0, "mal0_txctp0r" }, 591 { 0x1a1, "mal0_txctp1r" }, 592 { 0x1a2, "mal0_txctp2r" }, 593 { 0x1a3, "mal0_txctp3r" }, 594 { 0x1c0, "mal0_rxctp0r" }, 595 { 0x1e0, "mal0_rcbs0" }, 596 { 0, NULL } 597 }; 598 599 static const char *condstr[8] = { 600 "ge", "le", "ne", "ns", "lt", "gt", "eq", "so" 601 }; 602 603 604 void 605 op_ill(instr_t instr, vm_offset_t loc) 606 { 607 db_printf("illegal instruction %x\n", instr); 608 } 609 610 u_int32_t 611 extract_field(u_int32_t value, u_int32_t base, u_int32_t width) 612 { 613 u_int32_t mask = (1 << width) - 1; 614 return ((value >> base) & mask); 615 } 616 617 const struct opcode * search_op(const struct opcode *); 618 619 void 620 disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, 621 char *disasm_str, size_t slen) 622 { 623 char * pstr; 624 enum function_mask func; 625 int len; 626 627 #define ADD_LEN(s) do { \ 628 len = (s); \ 629 slen -= len; \ 630 pstr += len; \ 631 } while(0) 632 #define APP_PSTR(fmt, arg) ADD_LEN(snprintf(pstr, slen, (fmt), (arg))) 633 #define APP_PSTRS(fmt) ADD_LEN(snprintf(pstr, slen, "%s", (fmt))) 634 635 pstr = disasm_str; 636 637 func = popcode->func; 638 if (func & Op_BC) { 639 u_int BO, BI; 640 BO = extract_field(instr, 31 - 10, 5); 641 BI = extract_field(instr, 31 - 15, 5); 642 func &= ~Op_BC; 643 if (BO & 4) { 644 /* standard, no decrement */ 645 if (BO & 16) { 646 if (popcode->code == 0x40000000) { 647 APP_PSTRS("c"); 648 func |= Op_BO | Op_BI; 649 } 650 } 651 else { 652 APP_PSTRS(condstr[((BO & 8) >> 1) + (BI & 3)]); 653 if (BI >= 4) 654 func |= Op_crfS; 655 } 656 } 657 else { 658 /* decrement and branch */ 659 if (BO & 2) 660 APP_PSTRS("dz"); 661 else 662 APP_PSTRS("dnz"); 663 if ((BO & 24) == 0) 664 APP_PSTRS("f"); 665 else if ((BO & 24) == 8) 666 APP_PSTRS("t"); 667 else 668 func |= Op_BI; 669 } 670 if (popcode->code == 0x4c000020) 671 APP_PSTRS("lr"); 672 else if (popcode->code == 0x4c000420) 673 APP_PSTRS("ctr"); 674 if ((BO & 20) != 20 && (func & Op_BO) == 0) 675 func |= Op_BP; /* branch prediction hint */ 676 } 677 if (func & Op_OE) { 678 u_int OE; 679 OE = extract_field(instr, 31 - 21, 1); 680 if (OE) { 681 APP_PSTRS("o"); 682 } 683 func &= ~Op_OE; 684 } 685 switch (func & Op_LKM) { 686 case Op_Rc: 687 if (instr & 0x1) 688 APP_PSTRS("."); 689 break; 690 case Op_AA: 691 if (instr & 0x1) 692 APP_PSTRS("l"); 693 if (instr & 0x2) { 694 APP_PSTRS("a"); 695 loc = 0; /* Absolute address */ 696 } 697 break; 698 case Op_LK: 699 if (instr & 0x1) 700 APP_PSTRS("l"); 701 break; 702 default: 703 func &= ~Op_LKM; 704 } 705 if (func & Op_BP) { 706 int y; 707 y = (instr & 0x200000) != 0; 708 if (popcode->code == 0x40000000) { 709 int BD; 710 BD = extract_field(instr, 31 - 29, 14); 711 BD = BD << 18; 712 BD = BD >> 16; 713 BD += loc; 714 if ((vm_offset_t)BD < loc) 715 y ^= 1; 716 } 717 APP_PSTR("%c", y ? '+' : '-'); 718 func &= ~Op_BP; 719 } 720 APP_PSTRS("\t"); 721 722 /* XXX: special cases here, out of flags in a 32bit word. */ 723 if (strcmp(popcode->name, "wrteei") == 0) { 724 int E; 725 E = extract_field(instr, 31 - 16, 5); 726 APP_PSTR("%d", E); 727 return; 728 } 729 else if (strcmp(popcode->name, "mtfsfi") == 0) { 730 u_int UI; 731 UI = extract_field(instr, 31 - 8, 3); 732 APP_PSTR("crf%u, ", UI); 733 UI = extract_field(instr, 31 - 19, 4); 734 APP_PSTR("0x%x", UI); 735 } 736 /* XXX: end of special cases here. */ 737 738 if ((func & Op_FM) == Op_FM) { 739 u_int FM; 740 FM = extract_field(instr, 31 - 14, 8); 741 APP_PSTR("0x%x, ", FM); 742 func &= ~Op_FM; 743 } 744 if (func & Op_D) { /* Op_ST is the same */ 745 u_int D; 746 D = extract_field(instr, 31 - 10, 5); 747 APP_PSTR("r%d, ", D); 748 func &= ~Op_D; 749 } 750 if (func & Op_crbD) { 751 u_int crbD; 752 crbD = extract_field(instr, 31 - 10, 5); 753 APP_PSTR("crb%d, ", crbD); 754 func &= ~Op_crbD; 755 } 756 if (func & Op_crfD) { 757 u_int crfD; 758 crfD = extract_field(instr, 31 - 8, 3); 759 APP_PSTR("crf%d, ", crfD); 760 func &= ~Op_crfD; 761 } 762 if (func & Op_TO) { 763 u_int TO; 764 TO = extract_field(instr, 31 - 10, 1); 765 APP_PSTR("%d, ", TO); 766 func &= ~Op_TO; 767 } 768 if (func & Op_crfS) { 769 u_int crfS; 770 crfS = extract_field(instr, 31 - 13, 3); 771 APP_PSTR("crf%d, ", crfS); 772 func &= ~Op_crfS; 773 } 774 if (func & Op_CRM) { 775 u_int CRM; 776 CRM = extract_field(instr, 31 - 19, 8); 777 APP_PSTR("0x%x, ", CRM); 778 func &= ~Op_CRM; 779 } 780 if (func & Op_BO) { 781 u_int BO; 782 BO = extract_field(instr, 31 - 10, 5); 783 APP_PSTR("%d, ", BO); 784 func &= ~Op_BO; 785 } 786 if (func & Op_BI) { 787 u_int BI; 788 BI = extract_field(instr, 31 - 15, 5); 789 APP_PSTR("%d, ", BI); 790 func &= ~Op_BI; 791 } 792 if (func & Op_dA) { /* register A indirect with displacement */ 793 u_int A; 794 A = extract_field(instr, 31 - 31, 16); 795 if (A & 0x8000) { 796 APP_PSTRS("-"); 797 A = 0x10000-A; 798 } 799 APP_PSTR("0x%x", A); 800 A = extract_field(instr, 31 - 15, 5); 801 APP_PSTR("(r%d)", A); 802 func &= ~Op_dA; 803 } 804 if (func & Op_spr) { 805 u_int spr; 806 u_int sprl; 807 u_int sprh; 808 const struct specialreg *regs; 809 int i; 810 sprl = extract_field(instr, 31 - 15, 5); 811 sprh = extract_field(instr, 31 - 20, 5); 812 spr = sprh << 5 | sprl; 813 814 /* ugly hack - out of bitfields in the function mask */ 815 if (popcode->name[2] == 'd') /* m.Dcr */ 816 regs = dcrregs; 817 else 818 regs = sprregs; 819 for (i = 0; regs[i].name != NULL; i++) 820 if (spr == regs[i].reg) 821 break; 822 if (regs[i].name == NULL) 823 APP_PSTR("[unknown special reg (%d)]", spr); 824 else 825 APP_PSTR("%s", regs[i].name); 826 827 if (popcode->name[1] == 't') /* spr is destination */ 828 APP_PSTRS(", "); 829 func &= ~Op_spr; 830 } 831 if (func & Op_SR) { 832 u_int SR; 833 SR = extract_field(instr, 31 - 15, 3); 834 APP_PSTR("sr%d", SR); 835 if (popcode->name[1] == 't') /* SR is destination */ 836 APP_PSTRS(", "); 837 func &= ~Op_SR; 838 } 839 if (func & Op_A) { 840 u_int A; 841 A = extract_field(instr, 31 - 15, 5); 842 APP_PSTR("r%d, ", A); 843 func &= ~Op_A; 844 } 845 if (func & Op_S) { 846 u_int D; 847 D = extract_field(instr, 31 - 10, 5); 848 APP_PSTR("r%d, ", D); 849 func &= ~Op_S; 850 } 851 if (func & Op_C) { 852 u_int C; 853 C = extract_field(instr, 31 - 25, 5); 854 APP_PSTR("r%d, ", C); 855 func &= ~Op_C; 856 } 857 if (func & Op_B) { 858 u_int B; 859 B = extract_field(instr, 31 - 20, 5); 860 APP_PSTR("r%d", B); 861 func &= ~Op_B; 862 } 863 if (func & Op_crbA) { 864 u_int crbA; 865 crbA = extract_field(instr, 31 - 15, 5); 866 APP_PSTR("%d, ", crbA); 867 func &= ~Op_crbA; 868 } 869 if (func & Op_crbB) { 870 u_int crbB; 871 crbB = extract_field(instr, 31 - 20, 5); 872 APP_PSTR("%d, ", crbB); 873 func &= ~Op_crbB; 874 } 875 if (func & Op_LI) { 876 int LI; 877 LI = extract_field(instr, 31 - 29, 24); 878 LI = LI << 8; 879 LI = LI >> 6; 880 LI += loc; 881 APP_PSTR("0x%x", LI); 882 func &= ~Op_LI; 883 } 884 switch (func & Op_SIMM) { 885 u_int IMM; 886 case Op_SIMM: /* same as Op_d */ 887 IMM = extract_field(instr, 31 - 31, 16); 888 if (IMM & 0x8000) { 889 APP_PSTRS("-"); 890 IMM = 0x10000-IMM; 891 } 892 func &= ~Op_SIMM; 893 goto common; 894 case Op_UIMM: 895 IMM = extract_field(instr, 31 - 31, 16); 896 func &= ~Op_UIMM; 897 goto common; 898 common: 899 APP_PSTR("0x%x", IMM); 900 break; 901 default: 902 ; 903 } 904 if (func & Op_BD) { 905 int BD; 906 BD = extract_field(instr, 31 - 29, 14); 907 BD = BD << 18; 908 BD = BD >> 16; 909 BD += loc; 910 /* Need to sign extend and shift up 2, then add addr */ 911 APP_PSTR("0x%x", BD); 912 func &= ~Op_BD; 913 } 914 if (func & Op_ds) { 915 u_int ds; 916 ds = extract_field(instr, 31 - 29, 14) << 2; 917 APP_PSTR("0x%x", ds); 918 func &= ~Op_ds; 919 } 920 if (func & Op_me) { 921 u_int me, mel, meh; 922 mel = extract_field(instr, 31 - 25, 4); 923 meh = extract_field(instr, 31 - 26, 1); 924 me = meh << 4 | mel; 925 APP_PSTR(", 0x%x", me); 926 func &= ~Op_me; 927 } 928 if ((func & Op_SH) && (func & Op_sh_mb_sh)) { 929 u_int SH; 930 SH = extract_field(instr, 31 - 20, 5); 931 APP_PSTR("%d", SH); 932 } 933 if ((func & Op_MB) && (func & Op_sh_mb_sh)) { 934 u_int MB; 935 u_int ME; 936 MB = extract_field(instr, 31 - 25, 5); 937 APP_PSTR(", %d", MB); 938 ME = extract_field(instr, 31 - 30, 5); 939 APP_PSTR(", %d", ME); 940 } 941 if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) { 942 u_int sh, shl, shh; 943 shl = extract_field(instr, 31 - 19, 4); 944 shh = extract_field(instr, 31 - 20, 1); 945 sh = shh << 4 | shl; 946 APP_PSTR(", %d", sh); 947 } 948 if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) { 949 u_int mb, mbl, mbh; 950 mbl = extract_field(instr, 31 - 25, 4); 951 mbh = extract_field(instr, 31 - 26, 1); 952 mb = mbh << 4 | mbl; 953 APP_PSTR(", %d", mb); 954 } 955 if ((func & Op_me) && ! (func & Op_sh_mb_sh)) { 956 u_int me, mel, meh; 957 mel = extract_field(instr, 31 - 25, 4); 958 meh = extract_field(instr, 31 - 26, 1); 959 me = meh << 4 | mel; 960 APP_PSTR(", %d", me); 961 } 962 if (func & Op_tbr) { 963 u_int tbr; 964 u_int tbrl; 965 u_int tbrh; 966 const char *reg; 967 tbrl = extract_field(instr, 31 - 15, 5); 968 tbrh = extract_field(instr, 31 - 20, 5); 969 tbr = tbrh << 5 | tbrl; 970 971 switch (tbr) { 972 case 268: 973 reg = "tbl"; 974 break; 975 case 269: 976 reg = "tbu"; 977 break; 978 default: 979 reg = NULL; 980 } 981 if (reg == NULL) 982 APP_PSTR(", [unknown tbr %d ]", tbr); 983 else 984 APP_PSTR(", %s", reg); 985 func &= ~Op_tbr; 986 } 987 if (func & Op_NB) { 988 u_int NB; 989 NB = extract_field(instr, 31 - 20, 5); 990 if (NB == 0) 991 NB = 32; 992 APP_PSTR(", %d", NB); 993 func &= ~Op_SR; 994 } 995 #undef ADD_LEN 996 #undef APP_PSTR 997 #undef APP_PSTRS 998 } 999 1000 void 1001 op_base(instr_t instr, vm_offset_t loc) 1002 { 1003 dis_ppc(opcodes, instr, loc); 1004 } 1005 1006 void 1007 op_cl_x13(instr_t instr, vm_offset_t loc) 1008 { 1009 dis_ppc(opcodes_13, instr, loc); 1010 } 1011 1012 void 1013 op_cl_x1e(instr_t instr, vm_offset_t loc) 1014 { 1015 dis_ppc(opcodes_1e, instr, loc); 1016 } 1017 1018 void 1019 op_cl_x1f(instr_t instr, vm_offset_t loc) 1020 { 1021 dis_ppc(opcodes_1f, instr, loc); 1022 } 1023 1024 void 1025 op_cl_x3a(instr_t instr, vm_offset_t loc) 1026 { 1027 dis_ppc(opcodes_3a, instr, loc); 1028 } 1029 1030 void 1031 op_cl_x3b(instr_t instr, vm_offset_t loc) 1032 { 1033 dis_ppc(opcodes_3b, instr, loc); 1034 } 1035 1036 void 1037 op_cl_x3e(instr_t instr, vm_offset_t loc) 1038 { 1039 dis_ppc(opcodes_3e, instr, loc); 1040 } 1041 1042 void 1043 op_cl_x3f(instr_t instr, vm_offset_t loc) 1044 { 1045 dis_ppc(opcodes_3f, instr, loc); 1046 } 1047 1048 void 1049 dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc) 1050 { 1051 const struct opcode *op; 1052 int found = 0; 1053 int i; 1054 char disasm_str[80]; 1055 1056 for (i = 0, op = &opcodeset[0]; 1057 found == 0 && op->mask != 0; 1058 i++, op = &opcodeset[i]) { 1059 if ((instr & op->mask) == op->code) { 1060 found = 1; 1061 disasm_fields(op, instr, loc, disasm_str, 1062 sizeof disasm_str); 1063 db_printf("%s%s\n", op->name, disasm_str); 1064 return; 1065 } 1066 } 1067 op_ill(instr, loc); 1068 } 1069 1070 db_addr_t 1071 db_disasm(db_addr_t loc, bool extended) 1072 { 1073 int class; 1074 instr_t opcode; 1075 opcode = *(instr_t *)(loc); 1076 class = opcode >> 26; 1077 (opcodes_base[class])(opcode, loc); 1078 1079 return (loc + 4); 1080 } 1081 1082 vm_offset_t opc_disasm(vm_offset_t loc, int); 1083 1084 vm_offset_t 1085 opc_disasm(vm_offset_t loc, int xin) 1086 { 1087 int class; 1088 instr_t opcode; 1089 opcode = xin; 1090 class = opcode >> 26; 1091 (opcodes_base[class])(opcode, loc); 1092 1093 return (loc + 4); 1094 }
Cache object: e9e3c51d8f45e823b593e795e5b12dbd
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]