The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/powerpc/powerpc/mmu_oea.c

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    1 /*-
    2  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    3  * All rights reserved.
    4  *
    5  * This code is derived from software contributed to The NetBSD Foundation
    6  * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *        This product includes software developed by the NetBSD
   19  *        Foundation, Inc. and its contributors.
   20  * 4. Neither the name of The NetBSD Foundation nor the names of its
   21  *    contributors may be used to endorse or promote products derived
   22  *    from this software without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   26  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   27  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   34  * POSSIBILITY OF SUCH DAMAGE.
   35  */
   36 /*-
   37  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
   38  * Copyright (C) 1995, 1996 TooLs GmbH.
   39  * All rights reserved.
   40  *
   41  * Redistribution and use in source and binary forms, with or without
   42  * modification, are permitted provided that the following conditions
   43  * are met:
   44  * 1. Redistributions of source code must retain the above copyright
   45  *    notice, this list of conditions and the following disclaimer.
   46  * 2. Redistributions in binary form must reproduce the above copyright
   47  *    notice, this list of conditions and the following disclaimer in the
   48  *    documentation and/or other materials provided with the distribution.
   49  * 3. All advertising materials mentioning features or use of this software
   50  *    must display the following acknowledgement:
   51  *      This product includes software developed by TooLs GmbH.
   52  * 4. The name of TooLs GmbH may not be used to endorse or promote products
   53  *    derived from this software without specific prior written permission.
   54  *
   55  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
   56  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   57  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   58  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   59  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
   60  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
   61  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   62  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
   63  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
   64  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   65  *
   66  * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
   67  */
   68 /*-
   69  * Copyright (C) 2001 Benno Rice.
   70  * All rights reserved.
   71  *
   72  * Redistribution and use in source and binary forms, with or without
   73  * modification, are permitted provided that the following conditions
   74  * are met:
   75  * 1. Redistributions of source code must retain the above copyright
   76  *    notice, this list of conditions and the following disclaimer.
   77  * 2. Redistributions in binary form must reproduce the above copyright
   78  *    notice, this list of conditions and the following disclaimer in the
   79  *    documentation and/or other materials provided with the distribution.
   80  *
   81  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
   82  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   83  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   84  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   85  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
   86  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
   87  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   88  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
   89  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
   90  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   91  */
   92 
   93 #include <sys/cdefs.h>
   94 __FBSDID("$FreeBSD$");
   95 
   96 /*
   97  * Manages physical address maps.
   98  *
   99  * In addition to hardware address maps, this module is called upon to
  100  * provide software-use-only maps which may or may not be stored in the
  101  * same form as hardware maps.  These pseudo-maps are used to store
  102  * intermediate results from copy operations to and from address spaces.
  103  *
  104  * Since the information managed by this module is also stored by the
  105  * logical address mapping module, this module may throw away valid virtual
  106  * to physical mappings at almost any time.  However, invalidations of
  107  * mappings must be done as requested.
  108  *
  109  * In order to cope with hardware architectures which make virtual to
  110  * physical map invalidates expensive, this module may delay invalidate
  111  * reduced protection operations until such time as they are actually
  112  * necessary.  This module is given full information as to which processors
  113  * are currently using which maps, and to when physical maps must be made
  114  * correct.
  115  */
  116 
  117 #include "opt_kstack_pages.h"
  118 
  119 #include <sys/param.h>
  120 #include <sys/kernel.h>
  121 #include <sys/ktr.h>
  122 #include <sys/lock.h>
  123 #include <sys/msgbuf.h>
  124 #include <sys/mutex.h>
  125 #include <sys/proc.h>
  126 #include <sys/sysctl.h>
  127 #include <sys/systm.h>
  128 #include <sys/vmmeter.h>
  129 
  130 #include <dev/ofw/openfirm.h>
  131 
  132 #include <vm/vm.h>
  133 #include <vm/vm_param.h>
  134 #include <vm/vm_kern.h>
  135 #include <vm/vm_page.h>
  136 #include <vm/vm_map.h>
  137 #include <vm/vm_object.h>
  138 #include <vm/vm_extern.h>
  139 #include <vm/vm_pageout.h>
  140 #include <vm/vm_pager.h>
  141 #include <vm/uma.h>
  142 
  143 #include <machine/cpu.h>
  144 #include <machine/powerpc.h>
  145 #include <machine/bat.h>
  146 #include <machine/frame.h>
  147 #include <machine/md_var.h>
  148 #include <machine/psl.h>
  149 #include <machine/pte.h>
  150 #include <machine/sr.h>
  151 #include <machine/mmuvar.h>
  152 
  153 #include "mmu_if.h"
  154 
  155 #define MOEA_DEBUG
  156 
  157 #define TODO    panic("%s: not implemented", __func__);
  158 
  159 #define TLBIE(va)       __asm __volatile("tlbie %0" :: "r"(va))
  160 #define TLBSYNC()       __asm __volatile("tlbsync");
  161 #define SYNC()          __asm __volatile("sync");
  162 #define EIEIO()         __asm __volatile("eieio");
  163 
  164 #define VSID_MAKE(sr, hash)     ((sr) | (((hash) & 0xfffff) << 4))
  165 #define VSID_TO_SR(vsid)        ((vsid) & 0xf)
  166 #define VSID_TO_HASH(vsid)      (((vsid) >> 4) & 0xfffff)
  167 
  168 #define PVO_PTEGIDX_MASK        0x007           /* which PTEG slot */
  169 #define PVO_PTEGIDX_VALID       0x008           /* slot is valid */
  170 #define PVO_WIRED               0x010           /* PVO entry is wired */
  171 #define PVO_MANAGED             0x020           /* PVO entry is managed */
  172 #define PVO_EXECUTABLE          0x040           /* PVO entry is executable */
  173 #define PVO_BOOTSTRAP           0x080           /* PVO entry allocated during
  174                                                    bootstrap */
  175 #define PVO_FAKE                0x100           /* fictitious phys page */
  176 #define PVO_VADDR(pvo)          ((pvo)->pvo_vaddr & ~ADDR_POFF)
  177 #define PVO_ISEXECUTABLE(pvo)   ((pvo)->pvo_vaddr & PVO_EXECUTABLE)
  178 #define PVO_ISFAKE(pvo)         ((pvo)->pvo_vaddr & PVO_FAKE)
  179 #define PVO_PTEGIDX_GET(pvo)    ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK)
  180 #define PVO_PTEGIDX_ISSET(pvo)  ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID)
  181 #define PVO_PTEGIDX_CLR(pvo)    \
  182         ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK)))
  183 #define PVO_PTEGIDX_SET(pvo, i) \
  184         ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID))
  185 
  186 #define MOEA_PVO_CHECK(pvo)
  187 
  188 struct ofw_map {
  189         vm_offset_t     om_va;
  190         vm_size_t       om_len;
  191         vm_offset_t     om_pa;
  192         u_int           om_mode;
  193 };
  194 
  195 /*
  196  * Map of physical memory regions.
  197  */
  198 static struct   mem_region *regions;
  199 static struct   mem_region *pregions;
  200 u_int           phys_avail_count;
  201 int             regions_sz, pregions_sz;
  202 static struct   ofw_map *translations;
  203 
  204 extern struct pmap ofw_pmap;
  205 
  206 
  207 
  208 /*
  209  * Lock for the pteg and pvo tables.
  210  */
  211 struct mtx      moea_table_mutex;
  212 
  213 /*
  214  * PTEG data.
  215  */
  216 static struct   pteg *moea_pteg_table;
  217 u_int           moea_pteg_count;
  218 u_int           moea_pteg_mask;
  219 
  220 /*
  221  * PVO data.
  222  */
  223 struct  pvo_head *moea_pvo_table;               /* pvo entries by pteg index */
  224 struct  pvo_head moea_pvo_kunmanaged =
  225     LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
  226 struct  pvo_head moea_pvo_unmanaged =
  227     LIST_HEAD_INITIALIZER(moea_pvo_unmanaged);  /* list of unmanaged pages */
  228 
  229 uma_zone_t      moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
  230 uma_zone_t      moea_mpvo_zone; /* zone for pvo entries for managed pages */
  231 
  232 #define BPVO_POOL_SIZE  32768
  233 static struct   pvo_entry *moea_bpvo_pool;
  234 static int      moea_bpvo_pool_index = 0;
  235 
  236 #define VSID_NBPW       (sizeof(u_int32_t) * 8)
  237 static u_int    moea_vsid_bitmap[NPMAPS / VSID_NBPW];
  238 
  239 static boolean_t moea_initialized = FALSE;
  240 
  241 /*
  242  * Statistics.
  243  */
  244 u_int   moea_pte_valid = 0;
  245 u_int   moea_pte_overflow = 0;
  246 u_int   moea_pte_replacements = 0;
  247 u_int   moea_pvo_entries = 0;
  248 u_int   moea_pvo_enter_calls = 0;
  249 u_int   moea_pvo_remove_calls = 0;
  250 u_int   moea_pte_spills = 0;
  251 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
  252     0, "");
  253 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
  254     &moea_pte_overflow, 0, "");
  255 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
  256     &moea_pte_replacements, 0, "");
  257 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
  258     0, "");
  259 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
  260     &moea_pvo_enter_calls, 0, "");
  261 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
  262     &moea_pvo_remove_calls, 0, "");
  263 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
  264     &moea_pte_spills, 0, "");
  265 
  266 struct  pvo_entry *moea_pvo_zeropage;
  267 struct  mtx     moea_pvo_zeropage_mtx;
  268 
  269 vm_offset_t     moea_rkva_start = VM_MIN_KERNEL_ADDRESS;
  270 u_int           moea_rkva_count = 4;
  271 
  272 /*
  273  * Allocate physical memory for use in moea_bootstrap.
  274  */
  275 static vm_offset_t      moea_bootstrap_alloc(vm_size_t, u_int);
  276 
  277 /*
  278  * PTE calls.
  279  */
  280 static int              moea_pte_insert(u_int, struct pte *);
  281 
  282 /*
  283  * PVO calls.
  284  */
  285 static int      moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
  286                     vm_offset_t, vm_offset_t, u_int, int);
  287 static void     moea_pvo_remove(struct pvo_entry *, int);
  288 static struct   pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
  289 static struct   pte *moea_pvo_to_pte(const struct pvo_entry *, int);
  290 
  291 /*
  292  * Utility routines.
  293  */
  294 static void             moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
  295                             vm_prot_t, boolean_t);
  296 static struct           pvo_entry *moea_rkva_alloc(mmu_t);
  297 static void             moea_pa_map(struct pvo_entry *, vm_offset_t,
  298                             struct pte *, int *);
  299 static void             moea_pa_unmap(struct pvo_entry *, struct pte *, int *);
  300 static void             moea_syncicache(vm_offset_t, vm_size_t);
  301 static boolean_t        moea_query_bit(vm_page_t, int);
  302 static u_int            moea_clear_bit(vm_page_t, int, int *);
  303 static void             moea_kremove(mmu_t, vm_offset_t);
  304 static void             tlbia(void);
  305 int             moea_pte_spill(vm_offset_t);
  306 
  307 /*
  308  * Kernel MMU interface
  309  */
  310 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
  311 void moea_clear_modify(mmu_t, vm_page_t);
  312 void moea_clear_reference(mmu_t, vm_page_t);
  313 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
  314 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
  315 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
  316     vm_prot_t);
  317 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
  318 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
  319 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
  320 void moea_init(mmu_t);
  321 boolean_t moea_is_modified(mmu_t, vm_page_t);
  322 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
  323 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
  324 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
  325 void moea_pinit(mmu_t, pmap_t);
  326 void moea_pinit0(mmu_t, pmap_t);
  327 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
  328 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
  329 void moea_qremove(mmu_t, vm_offset_t, int);
  330 void moea_release(mmu_t, pmap_t);
  331 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
  332 void moea_remove_all(mmu_t, vm_page_t);
  333 void moea_remove_write(mmu_t, vm_page_t);
  334 void moea_zero_page(mmu_t, vm_page_t);
  335 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
  336 void moea_zero_page_idle(mmu_t, vm_page_t);
  337 void moea_activate(mmu_t, struct thread *);
  338 void moea_deactivate(mmu_t, struct thread *);
  339 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
  340 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t);
  341 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
  342 vm_offset_t moea_kextract(mmu_t, vm_offset_t);
  343 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t);
  344 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
  345 boolean_t moea_page_executable(mmu_t, vm_page_t);
  346 
  347 static mmu_method_t moea_methods[] = {
  348         MMUMETHOD(mmu_change_wiring,    moea_change_wiring),
  349         MMUMETHOD(mmu_clear_modify,     moea_clear_modify),
  350         MMUMETHOD(mmu_clear_reference,  moea_clear_reference),
  351         MMUMETHOD(mmu_copy_page,        moea_copy_page),
  352         MMUMETHOD(mmu_enter,            moea_enter),
  353         MMUMETHOD(mmu_enter_object,     moea_enter_object),
  354         MMUMETHOD(mmu_enter_quick,      moea_enter_quick),
  355         MMUMETHOD(mmu_extract,          moea_extract),
  356         MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
  357         MMUMETHOD(mmu_init,             moea_init),
  358         MMUMETHOD(mmu_is_modified,      moea_is_modified),
  359         MMUMETHOD(mmu_ts_referenced,    moea_ts_referenced),
  360         MMUMETHOD(mmu_map,              moea_map),
  361         MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
  362         MMUMETHOD(mmu_pinit,            moea_pinit),
  363         MMUMETHOD(mmu_pinit0,           moea_pinit0),
  364         MMUMETHOD(mmu_protect,          moea_protect),
  365         MMUMETHOD(mmu_qenter,           moea_qenter),
  366         MMUMETHOD(mmu_qremove,          moea_qremove),
  367         MMUMETHOD(mmu_release,          moea_release),
  368         MMUMETHOD(mmu_remove,           moea_remove),
  369         MMUMETHOD(mmu_remove_all,       moea_remove_all),
  370         MMUMETHOD(mmu_remove_write,     moea_remove_write),
  371         MMUMETHOD(mmu_zero_page,        moea_zero_page),
  372         MMUMETHOD(mmu_zero_page_area,   moea_zero_page_area),
  373         MMUMETHOD(mmu_zero_page_idle,   moea_zero_page_idle),
  374         MMUMETHOD(mmu_activate,         moea_activate),
  375         MMUMETHOD(mmu_deactivate,       moea_deactivate),
  376 
  377         /* Internal interfaces */
  378         MMUMETHOD(mmu_bootstrap,        moea_bootstrap),
  379         MMUMETHOD(mmu_mapdev,           moea_mapdev),
  380         MMUMETHOD(mmu_unmapdev,         moea_unmapdev),
  381         MMUMETHOD(mmu_kextract,         moea_kextract),
  382         MMUMETHOD(mmu_kenter,           moea_kenter),
  383         MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
  384         MMUMETHOD(mmu_page_executable,  moea_page_executable),
  385 
  386         { 0, 0 }
  387 };
  388 
  389 static mmu_def_t oea_mmu = {
  390         MMU_TYPE_OEA,
  391         moea_methods,
  392         0
  393 };
  394 MMU_DEF(oea_mmu);
  395 
  396 
  397 static __inline int
  398 va_to_sr(u_int *sr, vm_offset_t va)
  399 {
  400         return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
  401 }
  402 
  403 static __inline u_int
  404 va_to_pteg(u_int sr, vm_offset_t addr)
  405 {
  406         u_int hash;
  407 
  408         hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
  409             ADDR_PIDX_SHFT);
  410         return (hash & moea_pteg_mask);
  411 }
  412 
  413 static __inline struct pvo_head *
  414 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p)
  415 {
  416         struct  vm_page *pg;
  417 
  418         pg = PHYS_TO_VM_PAGE(pa);
  419 
  420         if (pg_p != NULL)
  421                 *pg_p = pg;
  422 
  423         if (pg == NULL)
  424                 return (&moea_pvo_unmanaged);
  425 
  426         return (&pg->md.mdpg_pvoh);
  427 }
  428 
  429 static __inline struct pvo_head *
  430 vm_page_to_pvoh(vm_page_t m)
  431 {
  432 
  433         return (&m->md.mdpg_pvoh);
  434 }
  435 
  436 static __inline void
  437 moea_attr_clear(vm_page_t m, int ptebit)
  438 {
  439 
  440         mtx_assert(&vm_page_queue_mtx, MA_OWNED);
  441         m->md.mdpg_attrs &= ~ptebit;
  442 }
  443 
  444 static __inline int
  445 moea_attr_fetch(vm_page_t m)
  446 {
  447 
  448         return (m->md.mdpg_attrs);
  449 }
  450 
  451 static __inline void
  452 moea_attr_save(vm_page_t m, int ptebit)
  453 {
  454 
  455         mtx_assert(&vm_page_queue_mtx, MA_OWNED);
  456         m->md.mdpg_attrs |= ptebit;
  457 }
  458 
  459 static __inline int
  460 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
  461 {
  462         if (pt->pte_hi == pvo_pt->pte_hi)
  463                 return (1);
  464 
  465         return (0);
  466 }
  467 
  468 static __inline int
  469 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
  470 {
  471         return (pt->pte_hi & ~PTE_VALID) ==
  472             (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
  473             ((va >> ADDR_API_SHFT) & PTE_API) | which);
  474 }
  475 
  476 static __inline void
  477 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
  478 {
  479 
  480         mtx_assert(&moea_table_mutex, MA_OWNED);
  481 
  482         /*
  483          * Construct a PTE.  Default to IMB initially.  Valid bit only gets
  484          * set when the real pte is set in memory.
  485          *
  486          * Note: Don't set the valid bit for correct operation of tlb update.
  487          */
  488         pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
  489             (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
  490         pt->pte_lo = pte_lo;
  491 }
  492 
  493 static __inline void
  494 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
  495 {
  496 
  497         mtx_assert(&moea_table_mutex, MA_OWNED);
  498         pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
  499 }
  500 
  501 static __inline void
  502 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
  503 {
  504 
  505         mtx_assert(&moea_table_mutex, MA_OWNED);
  506 
  507         /*
  508          * As shown in Section 7.6.3.2.3
  509          */
  510         pt->pte_lo &= ~ptebit;
  511         TLBIE(va);
  512         EIEIO();
  513         TLBSYNC();
  514         SYNC();
  515 }
  516 
  517 static __inline void
  518 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
  519 {
  520 
  521         mtx_assert(&moea_table_mutex, MA_OWNED);
  522         pvo_pt->pte_hi |= PTE_VALID;
  523 
  524         /*
  525          * Update the PTE as defined in section 7.6.3.1.
  526          * Note that the REF/CHG bits are from pvo_pt and thus should havce
  527          * been saved so this routine can restore them (if desired).
  528          */
  529         pt->pte_lo = pvo_pt->pte_lo;
  530         EIEIO();
  531         pt->pte_hi = pvo_pt->pte_hi;
  532         SYNC();
  533         moea_pte_valid++;
  534 }
  535 
  536 static __inline void
  537 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
  538 {
  539 
  540         mtx_assert(&moea_table_mutex, MA_OWNED);
  541         pvo_pt->pte_hi &= ~PTE_VALID;
  542 
  543         /*
  544          * Force the reg & chg bits back into the PTEs.
  545          */
  546         SYNC();
  547 
  548         /*
  549          * Invalidate the pte.
  550          */
  551         pt->pte_hi &= ~PTE_VALID;
  552 
  553         SYNC();
  554         TLBIE(va);
  555         EIEIO();
  556         TLBSYNC();
  557         SYNC();
  558 
  559         /*
  560          * Save the reg & chg bits.
  561          */
  562         moea_pte_synch(pt, pvo_pt);
  563         moea_pte_valid--;
  564 }
  565 
  566 static __inline void
  567 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
  568 {
  569 
  570         /*
  571          * Invalidate the PTE
  572          */
  573         moea_pte_unset(pt, pvo_pt, va);
  574         moea_pte_set(pt, pvo_pt);
  575 }
  576 
  577 /*
  578  * Quick sort callout for comparing memory regions.
  579  */
  580 static int      mr_cmp(const void *a, const void *b);
  581 static int      om_cmp(const void *a, const void *b);
  582 
  583 static int
  584 mr_cmp(const void *a, const void *b)
  585 {
  586         const struct    mem_region *regiona;
  587         const struct    mem_region *regionb;
  588 
  589         regiona = a;
  590         regionb = b;
  591         if (regiona->mr_start < regionb->mr_start)
  592                 return (-1);
  593         else if (regiona->mr_start > regionb->mr_start)
  594                 return (1);
  595         else
  596                 return (0);
  597 }
  598 
  599 static int
  600 om_cmp(const void *a, const void *b)
  601 {
  602         const struct    ofw_map *mapa;
  603         const struct    ofw_map *mapb;
  604 
  605         mapa = a;
  606         mapb = b;
  607         if (mapa->om_pa < mapb->om_pa)
  608                 return (-1);
  609         else if (mapa->om_pa > mapb->om_pa)
  610                 return (1);
  611         else
  612                 return (0);
  613 }
  614 
  615 void
  616 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
  617 {
  618         ihandle_t       mmui;
  619         phandle_t       chosen, mmu;
  620         int             sz;
  621         int             i, j;
  622         int             ofw_mappings;
  623         vm_size_t       size, physsz, hwphyssz;
  624         vm_offset_t     pa, va, off;
  625         u_int           batl, batu;
  626 
  627         /*
  628          * Set up BAT0 to map the lowest 256 MB area
  629          */
  630         battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
  631         battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
  632 
  633         /*
  634          * Map PCI memory space.
  635          */
  636         battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
  637         battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
  638 
  639         battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
  640         battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
  641 
  642         battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
  643         battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
  644 
  645         battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
  646         battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
  647 
  648         /*
  649          * Map obio devices.
  650          */
  651         battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
  652         battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
  653 
  654         /*
  655          * Use an IBAT and a DBAT to map the bottom segment of memory
  656          * where we are.
  657          */
  658         batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
  659         batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
  660         __asm (".balign 32; \n"
  661                "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
  662                "mtdbatu 0,%0; mtdbatl 0,%1; isync"
  663             :: "r"(batu), "r"(batl));
  664 
  665 #if 0
  666         /* map frame buffer */
  667         batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
  668         batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
  669         __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync"
  670             :: "r"(batu), "r"(batl));
  671 #endif
  672 
  673 #if 1
  674         /* map pci space */
  675         batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
  676         batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
  677         __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync"
  678             :: "r"(batu), "r"(batl));
  679 #endif
  680 
  681         /*
  682          * Set the start and end of kva.
  683          */
  684         virtual_avail = VM_MIN_KERNEL_ADDRESS;
  685         virtual_end = VM_MAX_KERNEL_ADDRESS;
  686 
  687         mem_regions(&pregions, &pregions_sz, &regions, &regions_sz);
  688         CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
  689 
  690         qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp);
  691         for (i = 0; i < pregions_sz; i++) {
  692                 vm_offset_t pa;
  693                 vm_offset_t end;
  694 
  695                 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
  696                         pregions[i].mr_start,
  697                         pregions[i].mr_start + pregions[i].mr_size,
  698                         pregions[i].mr_size);
  699                 /*
  700                  * Install entries into the BAT table to allow all
  701                  * of physmem to be convered by on-demand BAT entries.
  702                  * The loop will sometimes set the same battable element
  703                  * twice, but that's fine since they won't be used for
  704                  * a while yet.
  705                  */
  706                 pa = pregions[i].mr_start & 0xf0000000;
  707                 end = pregions[i].mr_start + pregions[i].mr_size;
  708                 do {
  709                         u_int n = pa >> ADDR_SR_SHFT;
  710 
  711                         battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
  712                         battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
  713                         pa += SEGMENT_LENGTH;
  714                 } while (pa < end);
  715         }
  716 
  717         if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
  718                 panic("moea_bootstrap: phys_avail too small");
  719         qsort(regions, regions_sz, sizeof(*regions), mr_cmp);
  720         phys_avail_count = 0;
  721         physsz = 0;
  722         hwphyssz = 0;
  723         TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
  724         for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
  725                 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
  726                     regions[i].mr_start + regions[i].mr_size,
  727                     regions[i].mr_size);
  728                 if (hwphyssz != 0 &&
  729                     (physsz + regions[i].mr_size) >= hwphyssz) {
  730                         if (physsz < hwphyssz) {
  731                                 phys_avail[j] = regions[i].mr_start;
  732                                 phys_avail[j + 1] = regions[i].mr_start +
  733                                     hwphyssz - physsz;
  734                                 physsz = hwphyssz;
  735                                 phys_avail_count++;
  736                         }
  737                         break;
  738                 }
  739                 phys_avail[j] = regions[i].mr_start;
  740                 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
  741                 phys_avail_count++;
  742                 physsz += regions[i].mr_size;
  743         }
  744         physmem = btoc(physsz);
  745 
  746         /*
  747          * Allocate PTEG table.
  748          */
  749 #ifdef PTEGCOUNT
  750         moea_pteg_count = PTEGCOUNT;
  751 #else
  752         moea_pteg_count = 0x1000;
  753 
  754         while (moea_pteg_count < physmem)
  755                 moea_pteg_count <<= 1;
  756 
  757         moea_pteg_count >>= 1;
  758 #endif /* PTEGCOUNT */
  759 
  760         size = moea_pteg_count * sizeof(struct pteg);
  761         CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
  762             size);
  763         moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
  764         CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
  765         bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
  766         moea_pteg_mask = moea_pteg_count - 1;
  767 
  768         /*
  769          * Allocate pv/overflow lists.
  770          */
  771         size = sizeof(struct pvo_head) * moea_pteg_count;
  772         moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
  773             PAGE_SIZE);
  774         CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
  775         for (i = 0; i < moea_pteg_count; i++)
  776                 LIST_INIT(&moea_pvo_table[i]);
  777 
  778         /*
  779          * Initialize the lock that synchronizes access to the pteg and pvo
  780          * tables.
  781          */
  782         mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
  783             MTX_RECURSE);
  784 
  785         /*
  786          * Allocate the message buffer.
  787          */
  788         msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, 0);
  789 
  790         /*
  791          * Initialise the unmanaged pvo pool.
  792          */
  793         moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
  794                 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
  795         moea_bpvo_pool_index = 0;
  796 
  797         /*
  798          * Make sure kernel vsid is allocated as well as VSID 0.
  799          */
  800         moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
  801                 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
  802         moea_vsid_bitmap[0] |= 1;
  803 
  804         /*
  805          * Set up the Open Firmware pmap and add it's mappings.
  806          */
  807         moea_pinit(mmup, &ofw_pmap);
  808         ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
  809         ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
  810         if ((chosen = OF_finddevice("/chosen")) == -1)
  811                 panic("moea_bootstrap: can't find /chosen");
  812         OF_getprop(chosen, "mmu", &mmui, 4);
  813         if ((mmu = OF_instance_to_package(mmui)) == -1)
  814                 panic("moea_bootstrap: can't get mmu package");
  815         if ((sz = OF_getproplen(mmu, "translations")) == -1)
  816                 panic("moea_bootstrap: can't get ofw translation count");
  817         translations = NULL;
  818         for (i = 0; phys_avail[i] != 0; i += 2) {
  819                 if (phys_avail[i + 1] >= sz) {
  820                         translations = (struct ofw_map *)phys_avail[i];
  821                         break;
  822                 }
  823         }
  824         if (translations == NULL)
  825                 panic("moea_bootstrap: no space to copy translations");
  826         bzero(translations, sz);
  827         if (OF_getprop(mmu, "translations", translations, sz) == -1)
  828                 panic("moea_bootstrap: can't get ofw translations");
  829         CTR0(KTR_PMAP, "moea_bootstrap: translations");
  830         sz /= sizeof(*translations);
  831         qsort(translations, sz, sizeof (*translations), om_cmp);
  832         for (i = 0, ofw_mappings = 0; i < sz; i++) {
  833                 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
  834                     translations[i].om_pa, translations[i].om_va,
  835                     translations[i].om_len);
  836 
  837                 /*
  838                  * If the mapping is 1:1, let the RAM and device on-demand
  839                  * BAT tables take care of the translation.
  840                  */
  841                 if (translations[i].om_va == translations[i].om_pa)
  842                         continue;
  843 
  844                 /* Enter the pages */
  845                 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
  846                         struct  vm_page m;
  847 
  848                         m.phys_addr = translations[i].om_pa + off;
  849                         PMAP_LOCK(&ofw_pmap);
  850                         moea_enter_locked(&ofw_pmap,
  851                                    translations[i].om_va + off, &m,
  852                                    VM_PROT_ALL, 1);
  853                         PMAP_UNLOCK(&ofw_pmap);
  854                         ofw_mappings++;
  855                 }
  856         }
  857 #ifdef SMP
  858         TLBSYNC();
  859 #endif
  860 
  861         /*
  862          * Initialize the kernel pmap (which is statically allocated).
  863          */
  864         PMAP_LOCK_INIT(kernel_pmap);
  865         for (i = 0; i < 16; i++) {
  866                 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT;
  867         }
  868         kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
  869         kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
  870         kernel_pmap->pm_active = ~0;
  871 
  872         /*
  873          * Allocate a kernel stack with a guard page for thread0 and map it
  874          * into the kernel page map.
  875          */
  876         pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0);
  877         kstack0_phys = pa;
  878         kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE);
  879         CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", kstack0_phys,
  880             kstack0);
  881         virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE;
  882         for (i = 0; i < KSTACK_PAGES; i++) {
  883                 pa = kstack0_phys + i * PAGE_SIZE;
  884                 va = kstack0 + i * PAGE_SIZE;
  885                 moea_kenter(mmup, va, pa);
  886                 TLBIE(va);
  887         }
  888 
  889         /*
  890          * Calculate the last available physical address.
  891          */
  892         for (i = 0; phys_avail[i + 2] != 0; i += 2)
  893                 ;
  894         Maxmem = powerpc_btop(phys_avail[i + 1]);
  895 
  896         /*
  897          * Allocate virtual address space for the message buffer.
  898          */
  899         msgbufp = (struct msgbuf *)virtual_avail;
  900         virtual_avail += round_page(MSGBUF_SIZE);
  901 
  902         /*
  903          * Initialize hardware.
  904          */
  905         for (i = 0; i < 16; i++) {
  906                 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT);
  907         }
  908         __asm __volatile ("mtsr %0,%1"
  909             :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT));
  910         __asm __volatile ("mtsr %0,%1"
  911             :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT));
  912         __asm __volatile ("sync; mtsdr1 %0; isync"
  913             :: "r"((u_int)moea_pteg_table | (moea_pteg_mask >> 10)));
  914         tlbia();
  915 
  916         pmap_bootstrapped++;
  917 }
  918 
  919 /*
  920  * Activate a user pmap.  The pmap must be activated before it's address
  921  * space can be accessed in any way.
  922  */
  923 void
  924 moea_activate(mmu_t mmu, struct thread *td)
  925 {
  926         pmap_t  pm, pmr;
  927 
  928         /*
  929          * Load all the data we need up front to encourage the compiler to
  930          * not issue any loads while we have interrupts disabled below.
  931          */
  932         pm = &td->td_proc->p_vmspace->vm_pmap;
  933 
  934         if ((pmr = (pmap_t)moea_kextract(mmu, (vm_offset_t)pm)) == NULL)
  935                 pmr = pm;
  936 
  937         pm->pm_active |= PCPU_GET(cpumask);
  938         PCPU_SET(curpmap, pmr);
  939 }
  940 
  941 void
  942 moea_deactivate(mmu_t mmu, struct thread *td)
  943 {
  944         pmap_t  pm;
  945 
  946         pm = &td->td_proc->p_vmspace->vm_pmap;
  947         pm->pm_active &= ~(PCPU_GET(cpumask));
  948         PCPU_SET(curpmap, NULL);
  949 }
  950 
  951 void
  952 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
  953 {
  954         struct  pvo_entry *pvo;
  955 
  956         PMAP_LOCK(pm);
  957         pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
  958 
  959         if (pvo != NULL) {
  960                 if (wired) {
  961                         if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
  962                                 pm->pm_stats.wired_count++;
  963                         pvo->pvo_vaddr |= PVO_WIRED;
  964                 } else {
  965                         if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
  966                                 pm->pm_stats.wired_count--;
  967                         pvo->pvo_vaddr &= ~PVO_WIRED;
  968                 }
  969         }
  970         PMAP_UNLOCK(pm);
  971 }
  972 
  973 void
  974 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
  975 {
  976         vm_offset_t     dst;
  977         vm_offset_t     src;
  978 
  979         dst = VM_PAGE_TO_PHYS(mdst);
  980         src = VM_PAGE_TO_PHYS(msrc);
  981 
  982         kcopy((void *)src, (void *)dst, PAGE_SIZE);
  983 }
  984 
  985 /*
  986  * Zero a page of physical memory by temporarily mapping it into the tlb.
  987  */
  988 void
  989 moea_zero_page(mmu_t mmu, vm_page_t m)
  990 {
  991         vm_offset_t pa = VM_PAGE_TO_PHYS(m);
  992         caddr_t va;
  993 
  994         if (pa < SEGMENT_LENGTH) {
  995                 va = (caddr_t) pa;
  996         } else if (moea_initialized) {
  997                 if (moea_pvo_zeropage == NULL) {
  998                         moea_pvo_zeropage = moea_rkva_alloc(mmu);
  999                         mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page",
 1000                             NULL, MTX_DEF);
 1001                 }
 1002                 mtx_lock(&moea_pvo_zeropage_mtx);
 1003                 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL);
 1004                 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage);
 1005         } else {
 1006                 panic("moea_zero_page: can't zero pa %#x", pa);
 1007         }
 1008 
 1009         bzero(va, PAGE_SIZE);
 1010 
 1011         if (pa >= SEGMENT_LENGTH) {
 1012                 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL);
 1013                 mtx_unlock(&moea_pvo_zeropage_mtx);
 1014         }
 1015 }
 1016 
 1017 void
 1018 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
 1019 {
 1020         vm_offset_t pa = VM_PAGE_TO_PHYS(m);
 1021         caddr_t va;
 1022 
 1023         if (pa < SEGMENT_LENGTH) {
 1024                 va = (caddr_t) pa;
 1025         } else if (moea_initialized) {
 1026                 if (moea_pvo_zeropage == NULL) {
 1027                         moea_pvo_zeropage = moea_rkva_alloc(mmu);
 1028                         mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page",
 1029                             NULL, MTX_DEF);
 1030                 }
 1031                 mtx_lock(&moea_pvo_zeropage_mtx);
 1032                 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL);
 1033                 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage);
 1034         } else {
 1035                 panic("moea_zero_page: can't zero pa %#x", pa);
 1036         }
 1037 
 1038         bzero(va + off, size);
 1039 
 1040         if (pa >= SEGMENT_LENGTH) {
 1041                 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL);
 1042                 mtx_unlock(&moea_pvo_zeropage_mtx);
 1043         }
 1044 }
 1045 
 1046 void
 1047 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
 1048 {
 1049 
 1050         moea_zero_page(mmu, m);
 1051 }
 1052 
 1053 /*
 1054  * Map the given physical page at the specified virtual address in the
 1055  * target pmap with the protection requested.  If specified the page
 1056  * will be wired down.
 1057  */
 1058 void
 1059 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
 1060            boolean_t wired)
 1061 {
 1062 
 1063         vm_page_lock_queues();
 1064         PMAP_LOCK(pmap);
 1065         moea_enter_locked(pmap, va, m, prot, wired);
 1066         vm_page_unlock_queues();
 1067         PMAP_UNLOCK(pmap);
 1068 }
 1069 
 1070 /*
 1071  * Map the given physical page at the specified virtual address in the
 1072  * target pmap with the protection requested.  If specified the page
 1073  * will be wired down.
 1074  *
 1075  * The page queues and pmap must be locked.
 1076  */
 1077 static void
 1078 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
 1079     boolean_t wired)
 1080 {
 1081         struct          pvo_head *pvo_head;
 1082         uma_zone_t      zone;
 1083         vm_page_t       pg;
 1084         u_int           pte_lo, pvo_flags, was_exec, i;
 1085         int             error;
 1086 
 1087         if (!moea_initialized) {
 1088                 pvo_head = &moea_pvo_kunmanaged;
 1089                 zone = moea_upvo_zone;
 1090                 pvo_flags = 0;
 1091                 pg = NULL;
 1092                 was_exec = PTE_EXEC;
 1093         } else {
 1094                 pvo_head = vm_page_to_pvoh(m);
 1095                 pg = m;
 1096                 zone = moea_mpvo_zone;
 1097                 pvo_flags = PVO_MANAGED;
 1098                 was_exec = 0;
 1099         }
 1100         if (pmap_bootstrapped)
 1101                 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
 1102         PMAP_LOCK_ASSERT(pmap, MA_OWNED);
 1103 
 1104         /* XXX change the pvo head for fake pages */
 1105         if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS)
 1106                 pvo_head = &moea_pvo_kunmanaged;
 1107 
 1108         /*
 1109          * If this is a managed page, and it's the first reference to the page,
 1110          * clear the execness of the page.  Otherwise fetch the execness.
 1111          */
 1112         if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) {
 1113                 if (LIST_EMPTY(pvo_head)) {
 1114                         moea_attr_clear(pg, PTE_EXEC);
 1115                 } else {
 1116                         was_exec = moea_attr_fetch(pg) & PTE_EXEC;
 1117                 }
 1118         }
 1119 
 1120         /*
 1121          * Assume the page is cache inhibited and access is guarded unless
 1122          * it's in our available memory array.
 1123          */
 1124         pte_lo = PTE_I | PTE_G;
 1125         for (i = 0; i < pregions_sz; i++) {
 1126                 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) &&
 1127                     (VM_PAGE_TO_PHYS(m) < 
 1128                         (pregions[i].mr_start + pregions[i].mr_size))) {
 1129                         pte_lo &= ~(PTE_I | PTE_G);
 1130                         break;
 1131                 }
 1132         }
 1133 
 1134         if (prot & VM_PROT_WRITE) {
 1135                 pte_lo |= PTE_BW;
 1136                 if (pmap_bootstrapped)
 1137                         vm_page_flag_set(m, PG_WRITEABLE);
 1138         } else
 1139                 pte_lo |= PTE_BR;
 1140 
 1141         if (prot & VM_PROT_EXECUTE)
 1142                 pvo_flags |= PVO_EXECUTABLE;
 1143 
 1144         if (wired)
 1145                 pvo_flags |= PVO_WIRED;
 1146 
 1147         if ((m->flags & PG_FICTITIOUS) != 0)
 1148                 pvo_flags |= PVO_FAKE;
 1149 
 1150         error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
 1151             pte_lo, pvo_flags);
 1152 
 1153         /*
 1154          * Flush the real page from the instruction cache if this page is
 1155          * mapped executable and cacheable and was not previously mapped (or
 1156          * was not mapped executable).
 1157          */
 1158         if (error == 0 && (pvo_flags & PVO_EXECUTABLE) &&
 1159             (pte_lo & PTE_I) == 0 && was_exec == 0) {
 1160                 /*
 1161                  * Flush the real memory from the cache.
 1162                  */
 1163                 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
 1164                 if (pg != NULL)
 1165                         moea_attr_save(pg, PTE_EXEC);
 1166         }
 1167 
 1168         /* XXX syncicache always until problems are sorted */
 1169         moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
 1170 }
 1171 
 1172 /*
 1173  * Maps a sequence of resident pages belonging to the same object.
 1174  * The sequence begins with the given page m_start.  This page is
 1175  * mapped at the given virtual address start.  Each subsequent page is
 1176  * mapped at a virtual address that is offset from start by the same
 1177  * amount as the page is offset from m_start within the object.  The
 1178  * last page in the sequence is the page with the largest offset from
 1179  * m_start that can be mapped at a virtual address less than the given
 1180  * virtual address end.  Not every virtual page between start and end
 1181  * is mapped; only those for which a resident page exists with the
 1182  * corresponding offset from m_start are mapped.
 1183  */
 1184 void
 1185 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
 1186     vm_page_t m_start, vm_prot_t prot)
 1187 {
 1188         vm_page_t m;
 1189         vm_pindex_t diff, psize;
 1190 
 1191         psize = atop(end - start);
 1192         m = m_start;
 1193         PMAP_LOCK(pm);
 1194         while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
 1195                 moea_enter_locked(pm, start + ptoa(diff), m, prot &
 1196                     (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
 1197                 m = TAILQ_NEXT(m, listq);
 1198         }
 1199         PMAP_UNLOCK(pm);
 1200 }
 1201 
 1202 void
 1203 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
 1204     vm_prot_t prot)
 1205 {
 1206 
 1207         PMAP_LOCK(pm);
 1208         moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
 1209             FALSE);
 1210         PMAP_UNLOCK(pm);
 1211 
 1212 }
 1213 
 1214 vm_paddr_t
 1215 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
 1216 {
 1217         struct  pvo_entry *pvo;
 1218         vm_paddr_t pa;
 1219 
 1220         PMAP_LOCK(pm);
 1221         pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
 1222         if (pvo == NULL)
 1223                 pa = 0;
 1224         else
 1225                 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
 1226         PMAP_UNLOCK(pm);
 1227         return (pa);
 1228 }
 1229 
 1230 /*
 1231  * Atomically extract and hold the physical page with the given
 1232  * pmap and virtual address pair if that mapping permits the given
 1233  * protection.
 1234  */
 1235 vm_page_t
 1236 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
 1237 {
 1238         struct  pvo_entry *pvo;
 1239         vm_page_t m;
 1240         
 1241         m = NULL;
 1242         vm_page_lock_queues();
 1243         PMAP_LOCK(pmap);
 1244         pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
 1245         if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) &&
 1246             ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW ||
 1247              (prot & VM_PROT_WRITE) == 0)) {
 1248                 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN);
 1249                 vm_page_hold(m);
 1250         }
 1251         vm_page_unlock_queues();
 1252         PMAP_UNLOCK(pmap);
 1253         return (m);
 1254 }
 1255 
 1256 void
 1257 moea_init(mmu_t mmu)
 1258 {
 1259 
 1260         CTR0(KTR_PMAP, "moea_init");
 1261 
 1262         moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
 1263             NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
 1264             UMA_ZONE_VM | UMA_ZONE_NOFREE);
 1265         moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
 1266             NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
 1267             UMA_ZONE_VM | UMA_ZONE_NOFREE);
 1268         moea_initialized = TRUE;
 1269 }
 1270 
 1271 boolean_t
 1272 moea_is_modified(mmu_t mmu, vm_page_t m)
 1273 {
 1274 
 1275         if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0)
 1276                 return (FALSE);
 1277 
 1278         return (moea_query_bit(m, PTE_CHG));
 1279 }
 1280 
 1281 void
 1282 moea_clear_reference(mmu_t mmu, vm_page_t m)
 1283 {
 1284 
 1285         if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
 1286                 return;
 1287         moea_clear_bit(m, PTE_REF, NULL);
 1288 }
 1289 
 1290 void
 1291 moea_clear_modify(mmu_t mmu, vm_page_t m)
 1292 {
 1293 
 1294         if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
 1295                 return;
 1296         moea_clear_bit(m, PTE_CHG, NULL);
 1297 }
 1298 
 1299 /*
 1300  * Clear the write and modified bits in each of the given page's mappings.
 1301  */
 1302 void
 1303 moea_remove_write(mmu_t mmu, vm_page_t m)
 1304 {
 1305         struct  pvo_entry *pvo;
 1306         struct  pte *pt;
 1307         pmap_t  pmap;
 1308         u_int   lo;
 1309 
 1310         mtx_assert(&vm_page_queue_mtx, MA_OWNED);
 1311         if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
 1312             (m->flags & PG_WRITEABLE) == 0)
 1313                 return;
 1314         lo = moea_attr_fetch(m);
 1315         SYNC();
 1316         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 1317                 pmap = pvo->pvo_pmap;
 1318                 PMAP_LOCK(pmap);
 1319                 if ((pvo->pvo_pte.pte_lo & PTE_PP) != PTE_BR) {
 1320                         pt = moea_pvo_to_pte(pvo, -1);
 1321                         pvo->pvo_pte.pte_lo &= ~PTE_PP;
 1322                         pvo->pvo_pte.pte_lo |= PTE_BR;
 1323                         if (pt != NULL) {
 1324                                 moea_pte_synch(pt, &pvo->pvo_pte);
 1325                                 lo |= pvo->pvo_pte.pte_lo;
 1326                                 pvo->pvo_pte.pte_lo &= ~PTE_CHG;
 1327                                 moea_pte_change(pt, &pvo->pvo_pte,
 1328                                     pvo->pvo_vaddr);
 1329                                 mtx_unlock(&moea_table_mutex);
 1330                         }
 1331                 }
 1332                 PMAP_UNLOCK(pmap);
 1333         }
 1334         if ((lo & PTE_CHG) != 0) {
 1335                 moea_attr_clear(m, PTE_CHG);
 1336                 vm_page_dirty(m);
 1337         }
 1338         vm_page_flag_clear(m, PG_WRITEABLE);
 1339 }
 1340 
 1341 /*
 1342  *      moea_ts_referenced:
 1343  *
 1344  *      Return a count of reference bits for a page, clearing those bits.
 1345  *      It is not necessary for every reference bit to be cleared, but it
 1346  *      is necessary that 0 only be returned when there are truly no
 1347  *      reference bits set.
 1348  *
 1349  *      XXX: The exact number of bits to check and clear is a matter that
 1350  *      should be tested and standardized at some point in the future for
 1351  *      optimal aging of shared pages.
 1352  */
 1353 boolean_t
 1354 moea_ts_referenced(mmu_t mmu, vm_page_t m)
 1355 {
 1356         int count;
 1357 
 1358         if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
 1359                 return (0);
 1360 
 1361         count = moea_clear_bit(m, PTE_REF, NULL);
 1362 
 1363         return (count);
 1364 }
 1365 
 1366 /*
 1367  * Map a wired page into kernel virtual address space.
 1368  */
 1369 void
 1370 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
 1371 {
 1372         u_int           pte_lo;
 1373         int             error;  
 1374         int             i;
 1375 
 1376 #if 0
 1377         if (va < VM_MIN_KERNEL_ADDRESS)
 1378                 panic("moea_kenter: attempt to enter non-kernel address %#x",
 1379                     va);
 1380 #endif
 1381 
 1382         pte_lo = PTE_I | PTE_G;
 1383         for (i = 0; i < pregions_sz; i++) {
 1384                 if ((pa >= pregions[i].mr_start) &&
 1385                     (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
 1386                         pte_lo &= ~(PTE_I | PTE_G);
 1387                         break;
 1388                 }
 1389         }       
 1390 
 1391         PMAP_LOCK(kernel_pmap);
 1392         error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
 1393             &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
 1394 
 1395         if (error != 0 && error != ENOENT)
 1396                 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
 1397                     pa, error);
 1398 
 1399         /*
 1400          * Flush the real memory from the instruction cache.
 1401          */
 1402         if ((pte_lo & (PTE_I | PTE_G)) == 0) {
 1403                 moea_syncicache(pa, PAGE_SIZE);
 1404         }
 1405         PMAP_UNLOCK(kernel_pmap);
 1406 }
 1407 
 1408 /*
 1409  * Extract the physical page address associated with the given kernel virtual
 1410  * address.
 1411  */
 1412 vm_offset_t
 1413 moea_kextract(mmu_t mmu, vm_offset_t va)
 1414 {
 1415         struct          pvo_entry *pvo;
 1416         vm_paddr_t pa;
 1417 
 1418 #ifdef UMA_MD_SMALL_ALLOC
 1419         /*
 1420          * Allow direct mappings
 1421          */
 1422         if (va < VM_MIN_KERNEL_ADDRESS) {
 1423                 return (va);
 1424         }
 1425 #endif
 1426 
 1427         PMAP_LOCK(kernel_pmap);
 1428         pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
 1429         KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
 1430         pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
 1431         PMAP_UNLOCK(kernel_pmap);
 1432         return (pa);
 1433 }
 1434 
 1435 /*
 1436  * Remove a wired page from kernel virtual address space.
 1437  */
 1438 void
 1439 moea_kremove(mmu_t mmu, vm_offset_t va)
 1440 {
 1441 
 1442         moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
 1443 }
 1444 
 1445 /*
 1446  * Map a range of physical addresses into kernel virtual address space.
 1447  *
 1448  * The value passed in *virt is a suggested virtual address for the mapping.
 1449  * Architectures which can support a direct-mapped physical to virtual region
 1450  * can return the appropriate address within that region, leaving '*virt'
 1451  * unchanged.  We cannot and therefore do not; *virt is updated with the
 1452  * first usable address after the mapped region.
 1453  */
 1454 vm_offset_t
 1455 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
 1456     vm_offset_t pa_end, int prot)
 1457 {
 1458         vm_offset_t     sva, va;
 1459 
 1460         sva = *virt;
 1461         va = sva;
 1462         for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
 1463                 moea_kenter(mmu, va, pa_start);
 1464         *virt = va;
 1465         return (sva);
 1466 }
 1467 
 1468 /*
 1469  * Returns true if the pmap's pv is one of the first
 1470  * 16 pvs linked to from this page.  This count may
 1471  * be changed upwards or downwards in the future; it
 1472  * is only necessary that true be returned for a small
 1473  * subset of pmaps for proper page aging.
 1474  */
 1475 boolean_t
 1476 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
 1477 {
 1478         int loops;
 1479         struct pvo_entry *pvo;
 1480 
 1481         if (!moea_initialized || (m->flags & PG_FICTITIOUS))
 1482                 return FALSE;
 1483 
 1484         loops = 0;
 1485         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 1486                 if (pvo->pvo_pmap == pmap)
 1487                         return (TRUE);
 1488                 if (++loops >= 16)
 1489                         break;
 1490         }
 1491 
 1492         return (FALSE);
 1493 }
 1494 
 1495 static u_int    moea_vsidcontext;
 1496 
 1497 void
 1498 moea_pinit(mmu_t mmu, pmap_t pmap)
 1499 {
 1500         int     i, mask;
 1501         u_int   entropy;
 1502 
 1503         KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
 1504         PMAP_LOCK_INIT(pmap);
 1505 
 1506         entropy = 0;
 1507         __asm __volatile("mftb %0" : "=r"(entropy));
 1508 
 1509         /*
 1510          * Allocate some segment registers for this pmap.
 1511          */
 1512         for (i = 0; i < NPMAPS; i += VSID_NBPW) {
 1513                 u_int   hash, n;
 1514 
 1515                 /*
 1516                  * Create a new value by mutiplying by a prime and adding in
 1517                  * entropy from the timebase register.  This is to make the
 1518                  * VSID more random so that the PT hash function collides
 1519                  * less often.  (Note that the prime casues gcc to do shifts
 1520                  * instead of a multiply.)
 1521                  */
 1522                 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
 1523                 hash = moea_vsidcontext & (NPMAPS - 1);
 1524                 if (hash == 0)          /* 0 is special, avoid it */
 1525                         continue;
 1526                 n = hash >> 5;
 1527                 mask = 1 << (hash & (VSID_NBPW - 1));
 1528                 hash = (moea_vsidcontext & 0xfffff);
 1529                 if (moea_vsid_bitmap[n] & mask) {       /* collision? */
 1530                         /* anything free in this bucket? */
 1531                         if (moea_vsid_bitmap[n] == 0xffffffff) {
 1532                                 entropy = (moea_vsidcontext >> 20);
 1533                                 continue;
 1534                         }
 1535                         i = ffs(~moea_vsid_bitmap[i]) - 1;
 1536                         mask = 1 << i;
 1537                         hash &= 0xfffff & ~(VSID_NBPW - 1);
 1538                         hash |= i;
 1539                 }
 1540                 moea_vsid_bitmap[n] |= mask;
 1541                 for (i = 0; i < 16; i++)
 1542                         pmap->pm_sr[i] = VSID_MAKE(i, hash);
 1543                 return;
 1544         }
 1545 
 1546         panic("moea_pinit: out of segments");
 1547 }
 1548 
 1549 /*
 1550  * Initialize the pmap associated with process 0.
 1551  */
 1552 void
 1553 moea_pinit0(mmu_t mmu, pmap_t pm)
 1554 {
 1555 
 1556         moea_pinit(mmu, pm);
 1557         bzero(&pm->pm_stats, sizeof(pm->pm_stats));
 1558 }
 1559 
 1560 /*
 1561  * Set the physical protection on the specified range of this map as requested.
 1562  */
 1563 void
 1564 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
 1565     vm_prot_t prot)
 1566 {
 1567         struct  pvo_entry *pvo;
 1568         struct  pte *pt;
 1569         int     pteidx;
 1570 
 1571         CTR4(KTR_PMAP, "moea_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva,
 1572             eva, prot);
 1573 
 1574 
 1575         KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
 1576             ("moea_protect: non current pmap"));
 1577 
 1578         if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
 1579                 moea_remove(mmu, pm, sva, eva);
 1580                 return;
 1581         }
 1582 
 1583         vm_page_lock_queues();
 1584         PMAP_LOCK(pm);
 1585         for (; sva < eva; sva += PAGE_SIZE) {
 1586                 pvo = moea_pvo_find_va(pm, sva, &pteidx);
 1587                 if (pvo == NULL)
 1588                         continue;
 1589 
 1590                 if ((prot & VM_PROT_EXECUTE) == 0)
 1591                         pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
 1592 
 1593                 /*
 1594                  * Grab the PTE pointer before we diddle with the cached PTE
 1595                  * copy.
 1596                  */
 1597                 pt = moea_pvo_to_pte(pvo, pteidx);
 1598                 /*
 1599                  * Change the protection of the page.
 1600                  */
 1601                 pvo->pvo_pte.pte_lo &= ~PTE_PP;
 1602                 pvo->pvo_pte.pte_lo |= PTE_BR;
 1603 
 1604                 /*
 1605                  * If the PVO is in the page table, update that pte as well.
 1606                  */
 1607                 if (pt != NULL) {
 1608                         moea_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 1609                         mtx_unlock(&moea_table_mutex);
 1610                 }
 1611         }
 1612         vm_page_unlock_queues();
 1613         PMAP_UNLOCK(pm);
 1614 }
 1615 
 1616 /*
 1617  * Map a list of wired pages into kernel virtual address space.  This is
 1618  * intended for temporary mappings which do not need page modification or
 1619  * references recorded.  Existing mappings in the region are overwritten.
 1620  */
 1621 void
 1622 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
 1623 {
 1624         vm_offset_t va;
 1625 
 1626         va = sva;
 1627         while (count-- > 0) {
 1628                 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
 1629                 va += PAGE_SIZE;
 1630                 m++;
 1631         }
 1632 }
 1633 
 1634 /*
 1635  * Remove page mappings from kernel virtual address space.  Intended for
 1636  * temporary mappings entered by moea_qenter.
 1637  */
 1638 void
 1639 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
 1640 {
 1641         vm_offset_t va;
 1642 
 1643         va = sva;
 1644         while (count-- > 0) {
 1645                 moea_kremove(mmu, va);
 1646                 va += PAGE_SIZE;
 1647         }
 1648 }
 1649 
 1650 void
 1651 moea_release(mmu_t mmu, pmap_t pmap)
 1652 {
 1653         int idx, mask;
 1654         
 1655         /*
 1656          * Free segment register's VSID
 1657          */
 1658         if (pmap->pm_sr[0] == 0)
 1659                 panic("moea_release");
 1660 
 1661         idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
 1662         mask = 1 << (idx % VSID_NBPW);
 1663         idx /= VSID_NBPW;
 1664         moea_vsid_bitmap[idx] &= ~mask;
 1665         PMAP_LOCK_DESTROY(pmap);
 1666 }
 1667 
 1668 /*
 1669  * Remove the given range of addresses from the specified map.
 1670  */
 1671 void
 1672 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
 1673 {
 1674         struct  pvo_entry *pvo;
 1675         int     pteidx;
 1676 
 1677         vm_page_lock_queues();
 1678         PMAP_LOCK(pm);
 1679         for (; sva < eva; sva += PAGE_SIZE) {
 1680                 pvo = moea_pvo_find_va(pm, sva, &pteidx);
 1681                 if (pvo != NULL) {
 1682                         moea_pvo_remove(pvo, pteidx);
 1683                 }
 1684         }
 1685         PMAP_UNLOCK(pm);
 1686         vm_page_unlock_queues();
 1687 }
 1688 
 1689 /*
 1690  * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
 1691  * will reflect changes in pte's back to the vm_page.
 1692  */
 1693 void
 1694 moea_remove_all(mmu_t mmu, vm_page_t m)
 1695 {
 1696         struct  pvo_head *pvo_head;
 1697         struct  pvo_entry *pvo, *next_pvo;
 1698         pmap_t  pmap;
 1699 
 1700         mtx_assert(&vm_page_queue_mtx, MA_OWNED);
 1701 
 1702         pvo_head = vm_page_to_pvoh(m);
 1703         for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
 1704                 next_pvo = LIST_NEXT(pvo, pvo_vlink);
 1705 
 1706                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 1707                 pmap = pvo->pvo_pmap;
 1708                 PMAP_LOCK(pmap);
 1709                 moea_pvo_remove(pvo, -1);
 1710                 PMAP_UNLOCK(pmap);
 1711         }
 1712         vm_page_flag_clear(m, PG_WRITEABLE);
 1713 }
 1714 
 1715 /*
 1716  * Allocate a physical page of memory directly from the phys_avail map.
 1717  * Can only be called from moea_bootstrap before avail start and end are
 1718  * calculated.
 1719  */
 1720 static vm_offset_t
 1721 moea_bootstrap_alloc(vm_size_t size, u_int align)
 1722 {
 1723         vm_offset_t     s, e;
 1724         int             i, j;
 1725 
 1726         size = round_page(size);
 1727         for (i = 0; phys_avail[i + 1] != 0; i += 2) {
 1728                 if (align != 0)
 1729                         s = (phys_avail[i] + align - 1) & ~(align - 1);
 1730                 else
 1731                         s = phys_avail[i];
 1732                 e = s + size;
 1733 
 1734                 if (s < phys_avail[i] || e > phys_avail[i + 1])
 1735                         continue;
 1736 
 1737                 if (s == phys_avail[i]) {
 1738                         phys_avail[i] += size;
 1739                 } else if (e == phys_avail[i + 1]) {
 1740                         phys_avail[i + 1] -= size;
 1741                 } else {
 1742                         for (j = phys_avail_count * 2; j > i; j -= 2) {
 1743                                 phys_avail[j] = phys_avail[j - 2];
 1744                                 phys_avail[j + 1] = phys_avail[j - 1];
 1745                         }
 1746 
 1747                         phys_avail[i + 3] = phys_avail[i + 1];
 1748                         phys_avail[i + 1] = s;
 1749                         phys_avail[i + 2] = e;
 1750                         phys_avail_count++;
 1751                 }
 1752 
 1753                 return (s);
 1754         }
 1755         panic("moea_bootstrap_alloc: could not allocate memory");
 1756 }
 1757 
 1758 /*
 1759  * Return an unmapped pvo for a kernel virtual address.
 1760  * Used by pmap functions that operate on physical pages.
 1761  */
 1762 static struct pvo_entry *
 1763 moea_rkva_alloc(mmu_t mmu)
 1764 {
 1765         struct          pvo_entry *pvo;
 1766         struct          pte *pt;
 1767         vm_offset_t     kva;
 1768         int             pteidx;
 1769 
 1770         if (moea_rkva_count == 0)
 1771                 panic("moea_rkva_alloc: no more reserved KVAs");
 1772 
 1773         kva = moea_rkva_start + (PAGE_SIZE * --moea_rkva_count);
 1774         moea_kenter(mmu, kva, 0);
 1775 
 1776         pvo = moea_pvo_find_va(kernel_pmap, kva, &pteidx);
 1777 
 1778         if (pvo == NULL)
 1779                 panic("moea_kva_alloc: moea_pvo_find_va failed");
 1780 
 1781         pt = moea_pvo_to_pte(pvo, pteidx);
 1782 
 1783         if (pt == NULL)
 1784                 panic("moea_kva_alloc: moea_pvo_to_pte failed");
 1785 
 1786         moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 1787         mtx_unlock(&moea_table_mutex);
 1788         PVO_PTEGIDX_CLR(pvo);
 1789 
 1790         moea_pte_overflow++;
 1791 
 1792         return (pvo);
 1793 }
 1794 
 1795 static void
 1796 moea_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt,
 1797     int *depth_p)
 1798 {
 1799         struct  pte *pt;
 1800 
 1801         /*
 1802          * If this pvo already has a valid pte, we need to save it so it can
 1803          * be restored later.  We then just reload the new PTE over the old
 1804          * slot.
 1805          */
 1806         if (saved_pt != NULL) {
 1807                 pt = moea_pvo_to_pte(pvo, -1);
 1808 
 1809                 if (pt != NULL) {
 1810                         moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 1811                         mtx_unlock(&moea_table_mutex);
 1812                         PVO_PTEGIDX_CLR(pvo);
 1813                         moea_pte_overflow++;
 1814                 }
 1815 
 1816                 *saved_pt = pvo->pvo_pte;
 1817 
 1818                 pvo->pvo_pte.pte_lo &= ~PTE_RPGN;
 1819         }
 1820 
 1821         pvo->pvo_pte.pte_lo |= pa;
 1822 
 1823         if (!moea_pte_spill(pvo->pvo_vaddr))
 1824                 panic("moea_pa_map: could not spill pvo %p", pvo);
 1825 
 1826         if (depth_p != NULL)
 1827                 (*depth_p)++;
 1828 }
 1829 
 1830 static void
 1831 moea_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p)
 1832 {
 1833         struct  pte *pt;
 1834 
 1835         pt = moea_pvo_to_pte(pvo, -1);
 1836 
 1837         if (pt != NULL) {
 1838                 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 1839                 mtx_unlock(&moea_table_mutex);
 1840                 PVO_PTEGIDX_CLR(pvo);
 1841                 moea_pte_overflow++;
 1842         }
 1843 
 1844         pvo->pvo_pte.pte_lo &= ~PTE_RPGN;
 1845 
 1846         /*
 1847          * If there is a saved PTE and it's valid, restore it and return.
 1848          */
 1849         if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) {
 1850                 if (depth_p != NULL && --(*depth_p) == 0)
 1851                         panic("moea_pa_unmap: restoring but depth == 0");
 1852 
 1853                 pvo->pvo_pte = *saved_pt;
 1854 
 1855                 if (!moea_pte_spill(pvo->pvo_vaddr))
 1856                         panic("moea_pa_unmap: could not spill pvo %p", pvo);
 1857         }
 1858 }
 1859 
 1860 static void
 1861 moea_syncicache(vm_offset_t pa, vm_size_t len)
 1862 {
 1863         __syncicache((void *)pa, len);
 1864 }
 1865 
 1866 static void
 1867 tlbia(void)
 1868 {
 1869         caddr_t i;
 1870 
 1871         SYNC();
 1872         for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) {
 1873                 TLBIE(i);
 1874                 EIEIO();
 1875         }
 1876         TLBSYNC();
 1877         SYNC();
 1878 }
 1879 
 1880 static int
 1881 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
 1882     vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
 1883 {
 1884         struct  pvo_entry *pvo;
 1885         u_int   sr;
 1886         int     first;
 1887         u_int   ptegidx;
 1888         int     i;
 1889         int     bootstrap;
 1890 
 1891         moea_pvo_enter_calls++;
 1892         first = 0;
 1893         bootstrap = 0;
 1894 
 1895         /*
 1896          * Compute the PTE Group index.
 1897          */
 1898         va &= ~ADDR_POFF;
 1899         sr = va_to_sr(pm->pm_sr, va);
 1900         ptegidx = va_to_pteg(sr, va);
 1901 
 1902         /*
 1903          * Remove any existing mapping for this page.  Reuse the pvo entry if
 1904          * there is a mapping.
 1905          */
 1906         mtx_lock(&moea_table_mutex);
 1907         LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
 1908                 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
 1909                         if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa &&
 1910                             (pvo->pvo_pte.pte_lo & PTE_PP) ==
 1911                             (pte_lo & PTE_PP)) {
 1912                                 mtx_unlock(&moea_table_mutex);
 1913                                 return (0);
 1914                         }
 1915                         moea_pvo_remove(pvo, -1);
 1916                         break;
 1917                 }
 1918         }
 1919 
 1920         /*
 1921          * If we aren't overwriting a mapping, try to allocate.
 1922          */
 1923         if (moea_initialized) {
 1924                 pvo = uma_zalloc(zone, M_NOWAIT);
 1925         } else {
 1926                 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
 1927                         panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
 1928                               moea_bpvo_pool_index, BPVO_POOL_SIZE, 
 1929                               BPVO_POOL_SIZE * sizeof(struct pvo_entry));
 1930                 }
 1931                 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
 1932                 moea_bpvo_pool_index++;
 1933                 bootstrap = 1;
 1934         }
 1935 
 1936         if (pvo == NULL) {
 1937                 mtx_unlock(&moea_table_mutex);
 1938                 return (ENOMEM);
 1939         }
 1940 
 1941         moea_pvo_entries++;
 1942         pvo->pvo_vaddr = va;
 1943         pvo->pvo_pmap = pm;
 1944         LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
 1945         pvo->pvo_vaddr &= ~ADDR_POFF;
 1946         if (flags & VM_PROT_EXECUTE)
 1947                 pvo->pvo_vaddr |= PVO_EXECUTABLE;
 1948         if (flags & PVO_WIRED)
 1949                 pvo->pvo_vaddr |= PVO_WIRED;
 1950         if (pvo_head != &moea_pvo_kunmanaged)
 1951                 pvo->pvo_vaddr |= PVO_MANAGED;
 1952         if (bootstrap)
 1953                 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
 1954         if (flags & PVO_FAKE)
 1955                 pvo->pvo_vaddr |= PVO_FAKE;
 1956 
 1957         moea_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo);
 1958 
 1959         /*
 1960          * Remember if the list was empty and therefore will be the first
 1961          * item.
 1962          */
 1963         if (LIST_FIRST(pvo_head) == NULL)
 1964                 first = 1;
 1965         LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
 1966 
 1967         if (pvo->pvo_pte.pte_lo & PVO_WIRED)
 1968                 pm->pm_stats.wired_count++;
 1969         pm->pm_stats.resident_count++;
 1970 
 1971         /*
 1972          * We hope this succeeds but it isn't required.
 1973          */
 1974         i = moea_pte_insert(ptegidx, &pvo->pvo_pte);
 1975         if (i >= 0) {
 1976                 PVO_PTEGIDX_SET(pvo, i);
 1977         } else {
 1978                 panic("moea_pvo_enter: overflow");
 1979                 moea_pte_overflow++;
 1980         }
 1981         mtx_unlock(&moea_table_mutex);
 1982 
 1983         return (first ? ENOENT : 0);
 1984 }
 1985 
 1986 static void
 1987 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
 1988 {
 1989         struct  pte *pt;
 1990 
 1991         /*
 1992          * If there is an active pte entry, we need to deactivate it (and
 1993          * save the ref & cfg bits).
 1994          */
 1995         pt = moea_pvo_to_pte(pvo, pteidx);
 1996         if (pt != NULL) {
 1997                 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 1998                 mtx_unlock(&moea_table_mutex);
 1999                 PVO_PTEGIDX_CLR(pvo);
 2000         } else {
 2001                 moea_pte_overflow--;
 2002         }
 2003 
 2004         /*
 2005          * Update our statistics.
 2006          */
 2007         pvo->pvo_pmap->pm_stats.resident_count--;
 2008         if (pvo->pvo_pte.pte_lo & PVO_WIRED)
 2009                 pvo->pvo_pmap->pm_stats.wired_count--;
 2010 
 2011         /*
 2012          * Save the REF/CHG bits into their cache if the page is managed.
 2013          */
 2014         if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) {
 2015                 struct  vm_page *pg;
 2016 
 2017                 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN);
 2018                 if (pg != NULL) {
 2019                         moea_attr_save(pg, pvo->pvo_pte.pte_lo &
 2020                             (PTE_REF | PTE_CHG));
 2021                 }
 2022         }
 2023 
 2024         /*
 2025          * Remove this PVO from the PV list.
 2026          */
 2027         LIST_REMOVE(pvo, pvo_vlink);
 2028 
 2029         /*
 2030          * Remove this from the overflow list and return it to the pool
 2031          * if we aren't going to reuse it.
 2032          */
 2033         LIST_REMOVE(pvo, pvo_olink);
 2034         if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
 2035                 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
 2036                     moea_upvo_zone, pvo);
 2037         moea_pvo_entries--;
 2038         moea_pvo_remove_calls++;
 2039 }
 2040 
 2041 static __inline int
 2042 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
 2043 {
 2044         int     pteidx;
 2045 
 2046         /*
 2047          * We can find the actual pte entry without searching by grabbing
 2048          * the PTEG index from 3 unused bits in pte_lo[11:9] and by
 2049          * noticing the HID bit.
 2050          */
 2051         pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
 2052         if (pvo->pvo_pte.pte_hi & PTE_HID)
 2053                 pteidx ^= moea_pteg_mask * 8;
 2054 
 2055         return (pteidx);
 2056 }
 2057 
 2058 static struct pvo_entry *
 2059 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
 2060 {
 2061         struct  pvo_entry *pvo;
 2062         int     ptegidx;
 2063         u_int   sr;
 2064 
 2065         va &= ~ADDR_POFF;
 2066         sr = va_to_sr(pm->pm_sr, va);
 2067         ptegidx = va_to_pteg(sr, va);
 2068 
 2069         mtx_lock(&moea_table_mutex);
 2070         LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
 2071                 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
 2072                         if (pteidx_p)
 2073                                 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
 2074                         break;
 2075                 }
 2076         }
 2077         mtx_unlock(&moea_table_mutex);
 2078 
 2079         return (pvo);
 2080 }
 2081 
 2082 static struct pte *
 2083 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
 2084 {
 2085         struct  pte *pt;
 2086 
 2087         /*
 2088          * If we haven't been supplied the ptegidx, calculate it.
 2089          */
 2090         if (pteidx == -1) {
 2091                 int     ptegidx;
 2092                 u_int   sr;
 2093 
 2094                 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
 2095                 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
 2096                 pteidx = moea_pvo_pte_index(pvo, ptegidx);
 2097         }
 2098 
 2099         pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
 2100         mtx_lock(&moea_table_mutex);
 2101 
 2102         if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
 2103                 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
 2104                     "valid pte index", pvo);
 2105         }
 2106 
 2107         if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
 2108                 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
 2109                     "pvo but no valid pte", pvo);
 2110         }
 2111 
 2112         if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
 2113                 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) {
 2114                         panic("moea_pvo_to_pte: pvo %p has valid pte in "
 2115                             "moea_pteg_table %p but invalid in pvo", pvo, pt);
 2116                 }
 2117 
 2118                 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF))
 2119                     != 0) {
 2120                         panic("moea_pvo_to_pte: pvo %p pte does not match "
 2121                             "pte %p in moea_pteg_table", pvo, pt);
 2122                 }
 2123 
 2124                 mtx_assert(&moea_table_mutex, MA_OWNED);
 2125                 return (pt);
 2126         }
 2127 
 2128         if (pvo->pvo_pte.pte_hi & PTE_VALID) {
 2129                 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
 2130                     "moea_pteg_table but valid in pvo", pvo, pt);
 2131         }
 2132 
 2133         mtx_unlock(&moea_table_mutex);
 2134         return (NULL);
 2135 }
 2136 
 2137 /*
 2138  * XXX: THIS STUFF SHOULD BE IN pte.c?
 2139  */
 2140 int
 2141 moea_pte_spill(vm_offset_t addr)
 2142 {
 2143         struct  pvo_entry *source_pvo, *victim_pvo;
 2144         struct  pvo_entry *pvo;
 2145         int     ptegidx, i, j;
 2146         u_int   sr;
 2147         struct  pteg *pteg;
 2148         struct  pte *pt;
 2149 
 2150         moea_pte_spills++;
 2151 
 2152         sr = mfsrin(addr);
 2153         ptegidx = va_to_pteg(sr, addr);
 2154 
 2155         /*
 2156          * Have to substitute some entry.  Use the primary hash for this.
 2157          * Use low bits of timebase as random generator.
 2158          */
 2159         pteg = &moea_pteg_table[ptegidx];
 2160         mtx_lock(&moea_table_mutex);
 2161         __asm __volatile("mftb %0" : "=r"(i));
 2162         i &= 7;
 2163         pt = &pteg->pt[i];
 2164 
 2165         source_pvo = NULL;
 2166         victim_pvo = NULL;
 2167         LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
 2168                 /*
 2169                  * We need to find a pvo entry for this address.
 2170                  */
 2171                 MOEA_PVO_CHECK(pvo);
 2172                 if (source_pvo == NULL &&
 2173                     moea_pte_match(&pvo->pvo_pte, sr, addr,
 2174                     pvo->pvo_pte.pte_hi & PTE_HID)) {
 2175                         /*
 2176                          * Now found an entry to be spilled into the pteg.
 2177                          * The PTE is now valid, so we know it's active.
 2178                          */
 2179                         j = moea_pte_insert(ptegidx, &pvo->pvo_pte);
 2180 
 2181                         if (j >= 0) {
 2182                                 PVO_PTEGIDX_SET(pvo, j);
 2183                                 moea_pte_overflow--;
 2184                                 MOEA_PVO_CHECK(pvo);
 2185                                 mtx_unlock(&moea_table_mutex);
 2186                                 return (1);
 2187                         }
 2188 
 2189                         source_pvo = pvo;
 2190 
 2191                         if (victim_pvo != NULL)
 2192                                 break;
 2193                 }
 2194 
 2195                 /*
 2196                  * We also need the pvo entry of the victim we are replacing
 2197                  * so save the R & C bits of the PTE.
 2198                  */
 2199                 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
 2200                     moea_pte_compare(pt, &pvo->pvo_pte)) {
 2201                         victim_pvo = pvo;
 2202                         if (source_pvo != NULL)
 2203                                 break;
 2204                 }
 2205         }
 2206 
 2207         if (source_pvo == NULL) {
 2208                 mtx_unlock(&moea_table_mutex);
 2209                 return (0);
 2210         }
 2211 
 2212         if (victim_pvo == NULL) {
 2213                 if ((pt->pte_hi & PTE_HID) == 0)
 2214                         panic("moea_pte_spill: victim p-pte (%p) has no pvo"
 2215                             "entry", pt);
 2216 
 2217                 /*
 2218                  * If this is a secondary PTE, we need to search it's primary
 2219                  * pvo bucket for the matching PVO.
 2220                  */
 2221                 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
 2222                     pvo_olink) {
 2223                         MOEA_PVO_CHECK(pvo);
 2224                         /*
 2225                          * We also need the pvo entry of the victim we are
 2226                          * replacing so save the R & C bits of the PTE.
 2227                          */
 2228                         if (moea_pte_compare(pt, &pvo->pvo_pte)) {
 2229                                 victim_pvo = pvo;
 2230                                 break;
 2231                         }
 2232                 }
 2233 
 2234                 if (victim_pvo == NULL)
 2235                         panic("moea_pte_spill: victim s-pte (%p) has no pvo"
 2236                             "entry", pt);
 2237         }
 2238 
 2239         /*
 2240          * We are invalidating the TLB entry for the EA we are replacing even
 2241          * though it's valid.  If we don't, we lose any ref/chg bit changes
 2242          * contained in the TLB entry.
 2243          */
 2244         source_pvo->pvo_pte.pte_hi &= ~PTE_HID;
 2245 
 2246         moea_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr);
 2247         moea_pte_set(pt, &source_pvo->pvo_pte);
 2248 
 2249         PVO_PTEGIDX_CLR(victim_pvo);
 2250         PVO_PTEGIDX_SET(source_pvo, i);
 2251         moea_pte_replacements++;
 2252 
 2253         MOEA_PVO_CHECK(victim_pvo);
 2254         MOEA_PVO_CHECK(source_pvo);
 2255 
 2256         mtx_unlock(&moea_table_mutex);
 2257         return (1);
 2258 }
 2259 
 2260 static int
 2261 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
 2262 {
 2263         struct  pte *pt;
 2264         int     i;
 2265 
 2266         mtx_assert(&moea_table_mutex, MA_OWNED);
 2267 
 2268         /*
 2269          * First try primary hash.
 2270          */
 2271         for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
 2272                 if ((pt->pte_hi & PTE_VALID) == 0) {
 2273                         pvo_pt->pte_hi &= ~PTE_HID;
 2274                         moea_pte_set(pt, pvo_pt);
 2275                         return (i);
 2276                 }
 2277         }
 2278 
 2279         /*
 2280          * Now try secondary hash.
 2281          */
 2282         ptegidx ^= moea_pteg_mask;
 2283 
 2284         for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
 2285                 if ((pt->pte_hi & PTE_VALID) == 0) {
 2286                         pvo_pt->pte_hi |= PTE_HID;
 2287                         moea_pte_set(pt, pvo_pt);
 2288                         return (i);
 2289                 }
 2290         }
 2291 
 2292         panic("moea_pte_insert: overflow");
 2293         return (-1);
 2294 }
 2295 
 2296 static boolean_t
 2297 moea_query_bit(vm_page_t m, int ptebit)
 2298 {
 2299         struct  pvo_entry *pvo;
 2300         struct  pte *pt;
 2301 
 2302 #if 0
 2303         if (moea_attr_fetch(m) & ptebit)
 2304                 return (TRUE);
 2305 #endif
 2306 
 2307         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 2308                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2309 
 2310                 /*
 2311                  * See if we saved the bit off.  If so, cache it and return
 2312                  * success.
 2313                  */
 2314                 if (pvo->pvo_pte.pte_lo & ptebit) {
 2315                         moea_attr_save(m, ptebit);
 2316                         MOEA_PVO_CHECK(pvo);    /* sanity check */
 2317                         return (TRUE);
 2318                 }
 2319         }
 2320 
 2321         /*
 2322          * No luck, now go through the hard part of looking at the PTEs
 2323          * themselves.  Sync so that any pending REF/CHG bits are flushed to
 2324          * the PTEs.
 2325          */
 2326         SYNC();
 2327         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 2328                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2329 
 2330                 /*
 2331                  * See if this pvo has a valid PTE.  if so, fetch the
 2332                  * REF/CHG bits from the valid PTE.  If the appropriate
 2333                  * ptebit is set, cache it and return success.
 2334                  */
 2335                 pt = moea_pvo_to_pte(pvo, -1);
 2336                 if (pt != NULL) {
 2337                         moea_pte_synch(pt, &pvo->pvo_pte);
 2338                         mtx_unlock(&moea_table_mutex);
 2339                         if (pvo->pvo_pte.pte_lo & ptebit) {
 2340                                 moea_attr_save(m, ptebit);
 2341                                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2342                                 return (TRUE);
 2343                         }
 2344                 }
 2345         }
 2346 
 2347         return (FALSE);
 2348 }
 2349 
 2350 static u_int
 2351 moea_clear_bit(vm_page_t m, int ptebit, int *origbit)
 2352 {
 2353         u_int   count;
 2354         struct  pvo_entry *pvo;
 2355         struct  pte *pt;
 2356         int     rv;
 2357 
 2358         /*
 2359          * Clear the cached value.
 2360          */
 2361         rv = moea_attr_fetch(m);
 2362         moea_attr_clear(m, ptebit);
 2363 
 2364         /*
 2365          * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
 2366          * we can reset the right ones).  note that since the pvo entries and
 2367          * list heads are accessed via BAT0 and are never placed in the page
 2368          * table, we don't have to worry about further accesses setting the
 2369          * REF/CHG bits.
 2370          */
 2371         SYNC();
 2372 
 2373         /*
 2374          * For each pvo entry, clear the pvo's ptebit.  If this pvo has a
 2375          * valid pte clear the ptebit from the valid pte.
 2376          */
 2377         count = 0;
 2378         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 2379                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2380                 pt = moea_pvo_to_pte(pvo, -1);
 2381                 if (pt != NULL) {
 2382                         moea_pte_synch(pt, &pvo->pvo_pte);
 2383                         if (pvo->pvo_pte.pte_lo & ptebit) {
 2384                                 count++;
 2385                                 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
 2386                         }
 2387                         mtx_unlock(&moea_table_mutex);
 2388                 }
 2389                 rv |= pvo->pvo_pte.pte_lo;
 2390                 pvo->pvo_pte.pte_lo &= ~ptebit;
 2391                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2392         }
 2393 
 2394         if (origbit != NULL) {
 2395                 *origbit = rv;
 2396         }
 2397 
 2398         return (count);
 2399 }
 2400 
 2401 /*
 2402  * Return true if the physical range is encompassed by the battable[idx]
 2403  */
 2404 static int
 2405 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
 2406 {
 2407         u_int prot;
 2408         u_int32_t start;
 2409         u_int32_t end;
 2410         u_int32_t bat_ble;
 2411 
 2412         /*
 2413          * Return immediately if not a valid mapping
 2414          */
 2415         if (!battable[idx].batu & BAT_Vs)
 2416                 return (EINVAL);
 2417 
 2418         /*
 2419          * The BAT entry must be cache-inhibited, guarded, and r/w
 2420          * so it can function as an i/o page
 2421          */
 2422         prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
 2423         if (prot != (BAT_I|BAT_G|BAT_PP_RW))
 2424                 return (EPERM); 
 2425 
 2426         /*
 2427          * The address should be within the BAT range. Assume that the
 2428          * start address in the BAT has the correct alignment (thus
 2429          * not requiring masking)
 2430          */
 2431         start = battable[idx].batl & BAT_PBS;
 2432         bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
 2433         end = start | (bat_ble << 15) | 0x7fff;
 2434 
 2435         if ((pa < start) || ((pa + size) > end))
 2436                 return (ERANGE);
 2437 
 2438         return (0);
 2439 }
 2440 
 2441 boolean_t
 2442 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
 2443 {
 2444         int i;
 2445 
 2446         /*
 2447          * This currently does not work for entries that 
 2448          * overlap 256M BAT segments.
 2449          */
 2450 
 2451         for(i = 0; i < 16; i++)
 2452                 if (moea_bat_mapped(i, pa, size) == 0)
 2453                         return (0);
 2454 
 2455         return (EFAULT);
 2456 }
 2457 
 2458 boolean_t
 2459 moea_page_executable(mmu_t mmu, vm_page_t pg)
 2460 {
 2461         return ((moea_attr_fetch(pg) & PTE_EXEC) == PTE_EXEC);
 2462 }
 2463 
 2464 /*
 2465  * Map a set of physical memory pages into the kernel virtual
 2466  * address space. Return a pointer to where it is mapped. This
 2467  * routine is intended to be used for mapping device memory,
 2468  * NOT real memory.
 2469  */
 2470 void *
 2471 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
 2472 {
 2473         vm_offset_t va, tmpva, ppa, offset;
 2474         int i;
 2475 
 2476         ppa = trunc_page(pa);
 2477         offset = pa & PAGE_MASK;
 2478         size = roundup(offset + size, PAGE_SIZE);
 2479         
 2480         GIANT_REQUIRED;
 2481 
 2482         /*
 2483          * If the physical address lies within a valid BAT table entry,
 2484          * return the 1:1 mapping. This currently doesn't work
 2485          * for regions that overlap 256M BAT segments.
 2486          */
 2487         for (i = 0; i < 16; i++) {
 2488                 if (moea_bat_mapped(i, pa, size) == 0)
 2489                         return ((void *) pa);
 2490         }
 2491 
 2492         va = kmem_alloc_nofault(kernel_map, size);
 2493         if (!va)
 2494                 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
 2495 
 2496         for (tmpva = va; size > 0;) {
 2497                 moea_kenter(mmu, tmpva, ppa);
 2498                 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */
 2499                 size -= PAGE_SIZE;
 2500                 tmpva += PAGE_SIZE;
 2501                 ppa += PAGE_SIZE;
 2502         }
 2503 
 2504         return ((void *)(va + offset));
 2505 }
 2506 
 2507 void
 2508 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
 2509 {
 2510         vm_offset_t base, offset;
 2511 
 2512         /*
 2513          * If this is outside kernel virtual space, then it's a
 2514          * battable entry and doesn't require unmapping
 2515          */
 2516         if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
 2517                 base = trunc_page(va);
 2518                 offset = va & PAGE_MASK;
 2519                 size = roundup(offset + size, PAGE_SIZE);
 2520                 kmem_free(kernel_map, base, size);
 2521         }
 2522 }

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