The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/powerpc/powerpc/mmu_oea.c

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    1 /*-
    2  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    3  * All rights reserved.
    4  *
    5  * This code is derived from software contributed to The NetBSD Foundation
    6  * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *        This product includes software developed by the NetBSD
   19  *        Foundation, Inc. and its contributors.
   20  * 4. Neither the name of The NetBSD Foundation nor the names of its
   21  *    contributors may be used to endorse or promote products derived
   22  *    from this software without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   26  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   27  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   34  * POSSIBILITY OF SUCH DAMAGE.
   35  */
   36 /*-
   37  * Copyright (C) 1995, 1996 Wolfgang Solfrank.
   38  * Copyright (C) 1995, 1996 TooLs GmbH.
   39  * All rights reserved.
   40  *
   41  * Redistribution and use in source and binary forms, with or without
   42  * modification, are permitted provided that the following conditions
   43  * are met:
   44  * 1. Redistributions of source code must retain the above copyright
   45  *    notice, this list of conditions and the following disclaimer.
   46  * 2. Redistributions in binary form must reproduce the above copyright
   47  *    notice, this list of conditions and the following disclaimer in the
   48  *    documentation and/or other materials provided with the distribution.
   49  * 3. All advertising materials mentioning features or use of this software
   50  *    must display the following acknowledgement:
   51  *      This product includes software developed by TooLs GmbH.
   52  * 4. The name of TooLs GmbH may not be used to endorse or promote products
   53  *    derived from this software without specific prior written permission.
   54  *
   55  * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
   56  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   57  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   58  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   59  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
   60  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
   61  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   62  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
   63  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
   64  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   65  *
   66  * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
   67  */
   68 /*-
   69  * Copyright (C) 2001 Benno Rice.
   70  * All rights reserved.
   71  *
   72  * Redistribution and use in source and binary forms, with or without
   73  * modification, are permitted provided that the following conditions
   74  * are met:
   75  * 1. Redistributions of source code must retain the above copyright
   76  *    notice, this list of conditions and the following disclaimer.
   77  * 2. Redistributions in binary form must reproduce the above copyright
   78  *    notice, this list of conditions and the following disclaimer in the
   79  *    documentation and/or other materials provided with the distribution.
   80  *
   81  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
   82  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   83  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   84  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   85  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
   86  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
   87  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   88  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
   89  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
   90  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   91  */
   92 
   93 #include <sys/cdefs.h>
   94 __FBSDID("$FreeBSD$");
   95 
   96 /*
   97  * Manages physical address maps.
   98  *
   99  * In addition to hardware address maps, this module is called upon to
  100  * provide software-use-only maps which may or may not be stored in the
  101  * same form as hardware maps.  These pseudo-maps are used to store
  102  * intermediate results from copy operations to and from address spaces.
  103  *
  104  * Since the information managed by this module is also stored by the
  105  * logical address mapping module, this module may throw away valid virtual
  106  * to physical mappings at almost any time.  However, invalidations of
  107  * mappings must be done as requested.
  108  *
  109  * In order to cope with hardware architectures which make virtual to
  110  * physical map invalidates expensive, this module may delay invalidate
  111  * reduced protection operations until such time as they are actually
  112  * necessary.  This module is given full information as to which processors
  113  * are currently using which maps, and to when physical maps must be made
  114  * correct.
  115  */
  116 
  117 #include "opt_kstack_pages.h"
  118 
  119 #include <sys/param.h>
  120 #include <sys/kernel.h>
  121 #include <sys/ktr.h>
  122 #include <sys/lock.h>
  123 #include <sys/msgbuf.h>
  124 #include <sys/mutex.h>
  125 #include <sys/proc.h>
  126 #include <sys/sysctl.h>
  127 #include <sys/systm.h>
  128 #include <sys/vmmeter.h>
  129 
  130 #include <dev/ofw/openfirm.h>
  131 
  132 #include <vm/vm.h>
  133 #include <vm/vm_param.h>
  134 #include <vm/vm_kern.h>
  135 #include <vm/vm_page.h>
  136 #include <vm/vm_map.h>
  137 #include <vm/vm_object.h>
  138 #include <vm/vm_extern.h>
  139 #include <vm/vm_pageout.h>
  140 #include <vm/vm_pager.h>
  141 #include <vm/uma.h>
  142 
  143 #include <machine/cpu.h>
  144 #include <machine/powerpc.h>
  145 #include <machine/bat.h>
  146 #include <machine/frame.h>
  147 #include <machine/md_var.h>
  148 #include <machine/psl.h>
  149 #include <machine/pte.h>
  150 #include <machine/sr.h>
  151 #include <machine/mmuvar.h>
  152 
  153 #include "mmu_if.h"
  154 
  155 #define MOEA_DEBUG
  156 
  157 #define TODO    panic("%s: not implemented", __func__);
  158 
  159 #define TLBIE(va)       __asm __volatile("tlbie %0" :: "r"(va))
  160 #define TLBSYNC()       __asm __volatile("tlbsync");
  161 #define SYNC()          __asm __volatile("sync");
  162 #define EIEIO()         __asm __volatile("eieio");
  163 
  164 #define VSID_MAKE(sr, hash)     ((sr) | (((hash) & 0xfffff) << 4))
  165 #define VSID_TO_SR(vsid)        ((vsid) & 0xf)
  166 #define VSID_TO_HASH(vsid)      (((vsid) >> 4) & 0xfffff)
  167 
  168 #define PVO_PTEGIDX_MASK        0x007           /* which PTEG slot */
  169 #define PVO_PTEGIDX_VALID       0x008           /* slot is valid */
  170 #define PVO_WIRED               0x010           /* PVO entry is wired */
  171 #define PVO_MANAGED             0x020           /* PVO entry is managed */
  172 #define PVO_EXECUTABLE          0x040           /* PVO entry is executable */
  173 #define PVO_BOOTSTRAP           0x080           /* PVO entry allocated during
  174                                                    bootstrap */
  175 #define PVO_FAKE                0x100           /* fictitious phys page */
  176 #define PVO_VADDR(pvo)          ((pvo)->pvo_vaddr & ~ADDR_POFF)
  177 #define PVO_ISEXECUTABLE(pvo)   ((pvo)->pvo_vaddr & PVO_EXECUTABLE)
  178 #define PVO_ISFAKE(pvo)         ((pvo)->pvo_vaddr & PVO_FAKE)
  179 #define PVO_PTEGIDX_GET(pvo)    ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK)
  180 #define PVO_PTEGIDX_ISSET(pvo)  ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID)
  181 #define PVO_PTEGIDX_CLR(pvo)    \
  182         ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK)))
  183 #define PVO_PTEGIDX_SET(pvo, i) \
  184         ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID))
  185 
  186 #define MOEA_PVO_CHECK(pvo)
  187 
  188 struct ofw_map {
  189         vm_offset_t     om_va;
  190         vm_size_t       om_len;
  191         vm_offset_t     om_pa;
  192         u_int           om_mode;
  193 };
  194 
  195 /*
  196  * Map of physical memory regions.
  197  */
  198 static struct   mem_region *regions;
  199 static struct   mem_region *pregions;
  200 u_int           phys_avail_count;
  201 int             regions_sz, pregions_sz;
  202 static struct   ofw_map *translations;
  203 
  204 extern struct pmap ofw_pmap;
  205 
  206 
  207 
  208 /*
  209  * Lock for the pteg and pvo tables.
  210  */
  211 struct mtx      moea_table_mutex;
  212 
  213 /*
  214  * PTEG data.
  215  */
  216 static struct   pteg *moea_pteg_table;
  217 u_int           moea_pteg_count;
  218 u_int           moea_pteg_mask;
  219 
  220 /*
  221  * PVO data.
  222  */
  223 struct  pvo_head *moea_pvo_table;               /* pvo entries by pteg index */
  224 struct  pvo_head moea_pvo_kunmanaged =
  225     LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
  226 struct  pvo_head moea_pvo_unmanaged =
  227     LIST_HEAD_INITIALIZER(moea_pvo_unmanaged);  /* list of unmanaged pages */
  228 
  229 uma_zone_t      moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
  230 uma_zone_t      moea_mpvo_zone; /* zone for pvo entries for managed pages */
  231 
  232 #define BPVO_POOL_SIZE  32768
  233 static struct   pvo_entry *moea_bpvo_pool;
  234 static int      moea_bpvo_pool_index = 0;
  235 
  236 #define VSID_NBPW       (sizeof(u_int32_t) * 8)
  237 static u_int    moea_vsid_bitmap[NPMAPS / VSID_NBPW];
  238 
  239 static boolean_t moea_initialized = FALSE;
  240 
  241 /*
  242  * Statistics.
  243  */
  244 u_int   moea_pte_valid = 0;
  245 u_int   moea_pte_overflow = 0;
  246 u_int   moea_pte_replacements = 0;
  247 u_int   moea_pvo_entries = 0;
  248 u_int   moea_pvo_enter_calls = 0;
  249 u_int   moea_pvo_remove_calls = 0;
  250 u_int   moea_pte_spills = 0;
  251 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
  252     0, "");
  253 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
  254     &moea_pte_overflow, 0, "");
  255 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
  256     &moea_pte_replacements, 0, "");
  257 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
  258     0, "");
  259 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
  260     &moea_pvo_enter_calls, 0, "");
  261 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
  262     &moea_pvo_remove_calls, 0, "");
  263 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
  264     &moea_pte_spills, 0, "");
  265 
  266 struct  pvo_entry *moea_pvo_zeropage;
  267 struct  mtx     moea_pvo_zeropage_mtx;
  268 
  269 vm_offset_t     moea_rkva_start = VM_MIN_KERNEL_ADDRESS;
  270 u_int           moea_rkva_count = 4;
  271 
  272 /*
  273  * Allocate physical memory for use in moea_bootstrap.
  274  */
  275 static vm_offset_t      moea_bootstrap_alloc(vm_size_t, u_int);
  276 
  277 /*
  278  * PTE calls.
  279  */
  280 static int              moea_pte_insert(u_int, struct pte *);
  281 
  282 /*
  283  * PVO calls.
  284  */
  285 static int      moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
  286                     vm_offset_t, vm_offset_t, u_int, int);
  287 static void     moea_pvo_remove(struct pvo_entry *, int);
  288 static struct   pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
  289 static struct   pte *moea_pvo_to_pte(const struct pvo_entry *, int);
  290 
  291 /*
  292  * Utility routines.
  293  */
  294 static void             moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
  295                             vm_prot_t, boolean_t);
  296 static struct           pvo_entry *moea_rkva_alloc(mmu_t);
  297 static void             moea_pa_map(struct pvo_entry *, vm_offset_t,
  298                             struct pte *, int *);
  299 static void             moea_pa_unmap(struct pvo_entry *, struct pte *, int *);
  300 static void             moea_syncicache(vm_offset_t, vm_size_t);
  301 static boolean_t        moea_query_bit(vm_page_t, int);
  302 static u_int            moea_clear_bit(vm_page_t, int, int *);
  303 static void             moea_kremove(mmu_t, vm_offset_t);
  304 static void             tlbia(void);
  305 int             moea_pte_spill(vm_offset_t);
  306 
  307 /*
  308  * Kernel MMU interface
  309  */
  310 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
  311 void moea_clear_modify(mmu_t, vm_page_t);
  312 void moea_clear_reference(mmu_t, vm_page_t);
  313 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
  314 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
  315 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
  316     vm_prot_t);
  317 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
  318 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
  319 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
  320 void moea_init(mmu_t);
  321 boolean_t moea_is_modified(mmu_t, vm_page_t);
  322 boolean_t moea_ts_referenced(mmu_t, vm_page_t);
  323 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_offset_t, vm_offset_t, int);
  324 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
  325 void moea_pinit(mmu_t, pmap_t);
  326 void moea_pinit0(mmu_t, pmap_t);
  327 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
  328 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
  329 void moea_qremove(mmu_t, vm_offset_t, int);
  330 void moea_release(mmu_t, pmap_t);
  331 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
  332 void moea_remove_all(mmu_t, vm_page_t);
  333 void moea_remove_write(mmu_t, vm_page_t);
  334 void moea_zero_page(mmu_t, vm_page_t);
  335 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
  336 void moea_zero_page_idle(mmu_t, vm_page_t);
  337 void moea_activate(mmu_t, struct thread *);
  338 void moea_deactivate(mmu_t, struct thread *);
  339 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
  340 void *moea_mapdev(mmu_t, vm_offset_t, vm_size_t);
  341 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
  342 vm_offset_t moea_kextract(mmu_t, vm_offset_t);
  343 void moea_kenter(mmu_t, vm_offset_t, vm_offset_t);
  344 boolean_t moea_dev_direct_mapped(mmu_t, vm_offset_t, vm_size_t);
  345 boolean_t moea_page_executable(mmu_t, vm_page_t);
  346 
  347 static mmu_method_t moea_methods[] = {
  348         MMUMETHOD(mmu_change_wiring,    moea_change_wiring),
  349         MMUMETHOD(mmu_clear_modify,     moea_clear_modify),
  350         MMUMETHOD(mmu_clear_reference,  moea_clear_reference),
  351         MMUMETHOD(mmu_copy_page,        moea_copy_page),
  352         MMUMETHOD(mmu_enter,            moea_enter),
  353         MMUMETHOD(mmu_enter_object,     moea_enter_object),
  354         MMUMETHOD(mmu_enter_quick,      moea_enter_quick),
  355         MMUMETHOD(mmu_extract,          moea_extract),
  356         MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
  357         MMUMETHOD(mmu_init,             moea_init),
  358         MMUMETHOD(mmu_is_modified,      moea_is_modified),
  359         MMUMETHOD(mmu_ts_referenced,    moea_ts_referenced),
  360         MMUMETHOD(mmu_map,              moea_map),
  361         MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
  362         MMUMETHOD(mmu_pinit,            moea_pinit),
  363         MMUMETHOD(mmu_pinit0,           moea_pinit0),
  364         MMUMETHOD(mmu_protect,          moea_protect),
  365         MMUMETHOD(mmu_qenter,           moea_qenter),
  366         MMUMETHOD(mmu_qremove,          moea_qremove),
  367         MMUMETHOD(mmu_release,          moea_release),
  368         MMUMETHOD(mmu_remove,           moea_remove),
  369         MMUMETHOD(mmu_remove_all,       moea_remove_all),
  370         MMUMETHOD(mmu_remove_write,     moea_remove_write),
  371         MMUMETHOD(mmu_zero_page,        moea_zero_page),
  372         MMUMETHOD(mmu_zero_page_area,   moea_zero_page_area),
  373         MMUMETHOD(mmu_zero_page_idle,   moea_zero_page_idle),
  374         MMUMETHOD(mmu_activate,         moea_activate),
  375         MMUMETHOD(mmu_deactivate,       moea_deactivate),
  376 
  377         /* Internal interfaces */
  378         MMUMETHOD(mmu_bootstrap,        moea_bootstrap),
  379         MMUMETHOD(mmu_mapdev,           moea_mapdev),
  380         MMUMETHOD(mmu_unmapdev,         moea_unmapdev),
  381         MMUMETHOD(mmu_kextract,         moea_kextract),
  382         MMUMETHOD(mmu_kenter,           moea_kenter),
  383         MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
  384         MMUMETHOD(mmu_page_executable,  moea_page_executable),
  385 
  386         { 0, 0 }
  387 };
  388 
  389 static mmu_def_t oea_mmu = {
  390         MMU_TYPE_OEA,
  391         moea_methods,
  392         0
  393 };
  394 MMU_DEF(oea_mmu);
  395 
  396 
  397 static __inline int
  398 va_to_sr(u_int *sr, vm_offset_t va)
  399 {
  400         return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
  401 }
  402 
  403 static __inline u_int
  404 va_to_pteg(u_int sr, vm_offset_t addr)
  405 {
  406         u_int hash;
  407 
  408         hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
  409             ADDR_PIDX_SHFT);
  410         return (hash & moea_pteg_mask);
  411 }
  412 
  413 static __inline struct pvo_head *
  414 pa_to_pvoh(vm_offset_t pa, vm_page_t *pg_p)
  415 {
  416         struct  vm_page *pg;
  417 
  418         pg = PHYS_TO_VM_PAGE(pa);
  419 
  420         if (pg_p != NULL)
  421                 *pg_p = pg;
  422 
  423         if (pg == NULL)
  424                 return (&moea_pvo_unmanaged);
  425 
  426         return (&pg->md.mdpg_pvoh);
  427 }
  428 
  429 static __inline struct pvo_head *
  430 vm_page_to_pvoh(vm_page_t m)
  431 {
  432 
  433         return (&m->md.mdpg_pvoh);
  434 }
  435 
  436 static __inline void
  437 moea_attr_clear(vm_page_t m, int ptebit)
  438 {
  439 
  440         mtx_assert(&vm_page_queue_mtx, MA_OWNED);
  441         m->md.mdpg_attrs &= ~ptebit;
  442 }
  443 
  444 static __inline int
  445 moea_attr_fetch(vm_page_t m)
  446 {
  447 
  448         return (m->md.mdpg_attrs);
  449 }
  450 
  451 static __inline void
  452 moea_attr_save(vm_page_t m, int ptebit)
  453 {
  454 
  455         mtx_assert(&vm_page_queue_mtx, MA_OWNED);
  456         m->md.mdpg_attrs |= ptebit;
  457 }
  458 
  459 static __inline int
  460 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
  461 {
  462         if (pt->pte_hi == pvo_pt->pte_hi)
  463                 return (1);
  464 
  465         return (0);
  466 }
  467 
  468 static __inline int
  469 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
  470 {
  471         return (pt->pte_hi & ~PTE_VALID) ==
  472             (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
  473             ((va >> ADDR_API_SHFT) & PTE_API) | which);
  474 }
  475 
  476 static __inline void
  477 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
  478 {
  479 
  480         mtx_assert(&moea_table_mutex, MA_OWNED);
  481 
  482         /*
  483          * Construct a PTE.  Default to IMB initially.  Valid bit only gets
  484          * set when the real pte is set in memory.
  485          *
  486          * Note: Don't set the valid bit for correct operation of tlb update.
  487          */
  488         pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
  489             (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
  490         pt->pte_lo = pte_lo;
  491 }
  492 
  493 static __inline void
  494 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
  495 {
  496 
  497         mtx_assert(&moea_table_mutex, MA_OWNED);
  498         pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
  499 }
  500 
  501 static __inline void
  502 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
  503 {
  504 
  505         mtx_assert(&moea_table_mutex, MA_OWNED);
  506 
  507         /*
  508          * As shown in Section 7.6.3.2.3
  509          */
  510         pt->pte_lo &= ~ptebit;
  511         TLBIE(va);
  512         EIEIO();
  513         TLBSYNC();
  514         SYNC();
  515 }
  516 
  517 static __inline void
  518 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
  519 {
  520 
  521         mtx_assert(&moea_table_mutex, MA_OWNED);
  522         pvo_pt->pte_hi |= PTE_VALID;
  523 
  524         /*
  525          * Update the PTE as defined in section 7.6.3.1.
  526          * Note that the REF/CHG bits are from pvo_pt and thus should havce
  527          * been saved so this routine can restore them (if desired).
  528          */
  529         pt->pte_lo = pvo_pt->pte_lo;
  530         EIEIO();
  531         pt->pte_hi = pvo_pt->pte_hi;
  532         SYNC();
  533         moea_pte_valid++;
  534 }
  535 
  536 static __inline void
  537 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
  538 {
  539 
  540         mtx_assert(&moea_table_mutex, MA_OWNED);
  541         pvo_pt->pte_hi &= ~PTE_VALID;
  542 
  543         /*
  544          * Force the reg & chg bits back into the PTEs.
  545          */
  546         SYNC();
  547 
  548         /*
  549          * Invalidate the pte.
  550          */
  551         pt->pte_hi &= ~PTE_VALID;
  552 
  553         SYNC();
  554         TLBIE(va);
  555         EIEIO();
  556         TLBSYNC();
  557         SYNC();
  558 
  559         /*
  560          * Save the reg & chg bits.
  561          */
  562         moea_pte_synch(pt, pvo_pt);
  563         moea_pte_valid--;
  564 }
  565 
  566 static __inline void
  567 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
  568 {
  569 
  570         /*
  571          * Invalidate the PTE
  572          */
  573         moea_pte_unset(pt, pvo_pt, va);
  574         moea_pte_set(pt, pvo_pt);
  575 }
  576 
  577 /*
  578  * Quick sort callout for comparing memory regions.
  579  */
  580 static int      mr_cmp(const void *a, const void *b);
  581 static int      om_cmp(const void *a, const void *b);
  582 
  583 static int
  584 mr_cmp(const void *a, const void *b)
  585 {
  586         const struct    mem_region *regiona;
  587         const struct    mem_region *regionb;
  588 
  589         regiona = a;
  590         regionb = b;
  591         if (regiona->mr_start < regionb->mr_start)
  592                 return (-1);
  593         else if (regiona->mr_start > regionb->mr_start)
  594                 return (1);
  595         else
  596                 return (0);
  597 }
  598 
  599 static int
  600 om_cmp(const void *a, const void *b)
  601 {
  602         const struct    ofw_map *mapa;
  603         const struct    ofw_map *mapb;
  604 
  605         mapa = a;
  606         mapb = b;
  607         if (mapa->om_pa < mapb->om_pa)
  608                 return (-1);
  609         else if (mapa->om_pa > mapb->om_pa)
  610                 return (1);
  611         else
  612                 return (0);
  613 }
  614 
  615 void
  616 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
  617 {
  618         ihandle_t       mmui;
  619         phandle_t       chosen, mmu;
  620         int             sz;
  621         int             i, j;
  622         int             ofw_mappings;
  623         vm_size_t       size, physsz, hwphyssz;
  624         vm_offset_t     pa, va, off;
  625         u_int           batl, batu;
  626 
  627         /*
  628          * Set up BAT0 to map the lowest 256 MB area
  629          */
  630         battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
  631         battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
  632 
  633         /*
  634          * Map PCI memory space.
  635          */
  636         battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
  637         battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
  638 
  639         battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
  640         battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
  641 
  642         battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
  643         battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
  644 
  645         battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
  646         battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
  647 
  648         /*
  649          * Map obio devices.
  650          */
  651         battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
  652         battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
  653 
  654         /*
  655          * Use an IBAT and a DBAT to map the bottom segment of memory
  656          * where we are.
  657          */
  658         batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
  659         batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
  660         __asm (".balign 32; \n"
  661                "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
  662                "mtdbatu 0,%0; mtdbatl 0,%1; isync"
  663             :: "r"(batu), "r"(batl));
  664 
  665 #if 0
  666         /* map frame buffer */
  667         batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
  668         batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
  669         __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync"
  670             :: "r"(batu), "r"(batl));
  671 #endif
  672 
  673 #if 1
  674         /* map pci space */
  675         batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
  676         batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
  677         __asm ("mtdbatu 1,%0; mtdbatl 1,%1; isync"
  678             :: "r"(batu), "r"(batl));
  679 #endif
  680 
  681         /*
  682          * Set the start and end of kva.
  683          */
  684         virtual_avail = VM_MIN_KERNEL_ADDRESS;
  685         virtual_end = VM_MAX_KERNEL_ADDRESS;
  686 
  687         mem_regions(&pregions, &pregions_sz, &regions, &regions_sz);
  688         CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
  689 
  690         qsort(pregions, pregions_sz, sizeof(*pregions), mr_cmp);
  691         for (i = 0; i < pregions_sz; i++) {
  692                 vm_offset_t pa;
  693                 vm_offset_t end;
  694 
  695                 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
  696                         pregions[i].mr_start,
  697                         pregions[i].mr_start + pregions[i].mr_size,
  698                         pregions[i].mr_size);
  699                 /*
  700                  * Install entries into the BAT table to allow all
  701                  * of physmem to be convered by on-demand BAT entries.
  702                  * The loop will sometimes set the same battable element
  703                  * twice, but that's fine since they won't be used for
  704                  * a while yet.
  705                  */
  706                 pa = pregions[i].mr_start & 0xf0000000;
  707                 end = pregions[i].mr_start + pregions[i].mr_size;
  708                 do {
  709                         u_int n = pa >> ADDR_SR_SHFT;
  710 
  711                         battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
  712                         battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
  713                         pa += SEGMENT_LENGTH;
  714                 } while (pa < end);
  715         }
  716 
  717         if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
  718                 panic("moea_bootstrap: phys_avail too small");
  719         qsort(regions, regions_sz, sizeof(*regions), mr_cmp);
  720         phys_avail_count = 0;
  721         physsz = 0;
  722         hwphyssz = 0;
  723         TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
  724         for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
  725                 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
  726                     regions[i].mr_start + regions[i].mr_size,
  727                     regions[i].mr_size);
  728                 if (hwphyssz != 0 &&
  729                     (physsz + regions[i].mr_size) >= hwphyssz) {
  730                         if (physsz < hwphyssz) {
  731                                 phys_avail[j] = regions[i].mr_start;
  732                                 phys_avail[j + 1] = regions[i].mr_start +
  733                                     hwphyssz - physsz;
  734                                 physsz = hwphyssz;
  735                                 phys_avail_count++;
  736                         }
  737                         break;
  738                 }
  739                 phys_avail[j] = regions[i].mr_start;
  740                 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
  741                 phys_avail_count++;
  742                 physsz += regions[i].mr_size;
  743         }
  744         physmem = btoc(physsz);
  745 
  746         /*
  747          * Allocate PTEG table.
  748          */
  749 #ifdef PTEGCOUNT
  750         moea_pteg_count = PTEGCOUNT;
  751 #else
  752         moea_pteg_count = 0x1000;
  753 
  754         while (moea_pteg_count < physmem)
  755                 moea_pteg_count <<= 1;
  756 
  757         moea_pteg_count >>= 1;
  758 #endif /* PTEGCOUNT */
  759 
  760         size = moea_pteg_count * sizeof(struct pteg);
  761         CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
  762             size);
  763         moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
  764         CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
  765         bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
  766         moea_pteg_mask = moea_pteg_count - 1;
  767 
  768         /*
  769          * Allocate pv/overflow lists.
  770          */
  771         size = sizeof(struct pvo_head) * moea_pteg_count;
  772         moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
  773             PAGE_SIZE);
  774         CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
  775         for (i = 0; i < moea_pteg_count; i++)
  776                 LIST_INIT(&moea_pvo_table[i]);
  777 
  778         /*
  779          * Initialize the lock that synchronizes access to the pteg and pvo
  780          * tables.
  781          */
  782         mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
  783             MTX_RECURSE);
  784 
  785         /*
  786          * Allocate the message buffer.
  787          */
  788         msgbuf_phys = moea_bootstrap_alloc(MSGBUF_SIZE, 0);
  789 
  790         /*
  791          * Initialise the unmanaged pvo pool.
  792          */
  793         moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
  794                 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
  795         moea_bpvo_pool_index = 0;
  796 
  797         /*
  798          * Make sure kernel vsid is allocated as well as VSID 0.
  799          */
  800         moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
  801                 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
  802         moea_vsid_bitmap[0] |= 1;
  803 
  804         /*
  805          * Set up the Open Firmware pmap and add it's mappings.
  806          */
  807         moea_pinit(mmup, &ofw_pmap);
  808         ofw_pmap.pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
  809         ofw_pmap.pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
  810         if ((chosen = OF_finddevice("/chosen")) == -1)
  811                 panic("moea_bootstrap: can't find /chosen");
  812         OF_getprop(chosen, "mmu", &mmui, 4);
  813         if ((mmu = OF_instance_to_package(mmui)) == -1)
  814                 panic("moea_bootstrap: can't get mmu package");
  815         if ((sz = OF_getproplen(mmu, "translations")) == -1)
  816                 panic("moea_bootstrap: can't get ofw translation count");
  817         translations = NULL;
  818         for (i = 0; phys_avail[i] != 0; i += 2) {
  819                 if (phys_avail[i + 1] >= sz) {
  820                         translations = (struct ofw_map *)phys_avail[i];
  821                         break;
  822                 }
  823         }
  824         if (translations == NULL)
  825                 panic("moea_bootstrap: no space to copy translations");
  826         bzero(translations, sz);
  827         if (OF_getprop(mmu, "translations", translations, sz) == -1)
  828                 panic("moea_bootstrap: can't get ofw translations");
  829         CTR0(KTR_PMAP, "moea_bootstrap: translations");
  830         sz /= sizeof(*translations);
  831         qsort(translations, sz, sizeof (*translations), om_cmp);
  832         for (i = 0, ofw_mappings = 0; i < sz; i++) {
  833                 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
  834                     translations[i].om_pa, translations[i].om_va,
  835                     translations[i].om_len);
  836 
  837                 /*
  838                  * If the mapping is 1:1, let the RAM and device on-demand
  839                  * BAT tables take care of the translation.
  840                  */
  841                 if (translations[i].om_va == translations[i].om_pa)
  842                         continue;
  843 
  844                 /* Enter the pages */
  845                 for (off = 0; off < translations[i].om_len; off += PAGE_SIZE) {
  846                         struct  vm_page m;
  847 
  848                         m.phys_addr = translations[i].om_pa + off;
  849                         PMAP_LOCK(&ofw_pmap);
  850                         moea_enter_locked(&ofw_pmap,
  851                                    translations[i].om_va + off, &m,
  852                                    VM_PROT_ALL, 1);
  853                         PMAP_UNLOCK(&ofw_pmap);
  854                         ofw_mappings++;
  855                 }
  856         }
  857 #ifdef SMP
  858         TLBSYNC();
  859 #endif
  860 
  861         /*
  862          * Initialize the kernel pmap (which is statically allocated).
  863          */
  864         PMAP_LOCK_INIT(kernel_pmap);
  865         for (i = 0; i < 16; i++) {
  866                 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT;
  867         }
  868         kernel_pmap->pm_sr[KERNEL_SR] = KERNEL_SEGMENT;
  869         kernel_pmap->pm_sr[KERNEL2_SR] = KERNEL2_SEGMENT;
  870         kernel_pmap->pm_active = ~0;
  871 
  872         /*
  873          * Allocate a kernel stack with a guard page for thread0 and map it
  874          * into the kernel page map.
  875          */
  876         pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, 0);
  877         kstack0_phys = pa;
  878         kstack0 = virtual_avail + (KSTACK_GUARD_PAGES * PAGE_SIZE);
  879         CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", kstack0_phys,
  880             kstack0);
  881         virtual_avail += (KSTACK_PAGES + KSTACK_GUARD_PAGES) * PAGE_SIZE;
  882         for (i = 0; i < KSTACK_PAGES; i++) {
  883                 pa = kstack0_phys + i * PAGE_SIZE;
  884                 va = kstack0 + i * PAGE_SIZE;
  885                 moea_kenter(mmup, va, pa);
  886                 TLBIE(va);
  887         }
  888 
  889         /*
  890          * Calculate the last available physical address.
  891          */
  892         for (i = 0; phys_avail[i + 2] != 0; i += 2)
  893                 ;
  894         Maxmem = powerpc_btop(phys_avail[i + 1]);
  895 
  896         /*
  897          * Allocate virtual address space for the message buffer.
  898          */
  899         msgbufp = (struct msgbuf *)virtual_avail;
  900         virtual_avail += round_page(MSGBUF_SIZE);
  901 
  902         /*
  903          * Initialize hardware.
  904          */
  905         for (i = 0; i < 16; i++) {
  906                 mtsrin(i << ADDR_SR_SHFT, EMPTY_SEGMENT);
  907         }
  908         __asm __volatile ("mtsr %0,%1"
  909             :: "n"(KERNEL_SR), "r"(KERNEL_SEGMENT));
  910         __asm __volatile ("mtsr %0,%1"
  911             :: "n"(KERNEL2_SR), "r"(KERNEL2_SEGMENT));
  912         __asm __volatile ("sync; mtsdr1 %0; isync"
  913             :: "r"((u_int)moea_pteg_table | (moea_pteg_mask >> 10)));
  914         tlbia();
  915 
  916         pmap_bootstrapped++;
  917 }
  918 
  919 /*
  920  * Activate a user pmap.  The pmap must be activated before it's address
  921  * space can be accessed in any way.
  922  */
  923 void
  924 moea_activate(mmu_t mmu, struct thread *td)
  925 {
  926         pmap_t  pm, pmr;
  927 
  928         /*
  929          * Load all the data we need up front to encourage the compiler to
  930          * not issue any loads while we have interrupts disabled below.
  931          */
  932         pm = &td->td_proc->p_vmspace->vm_pmap;
  933 
  934         if ((pmr = (pmap_t)moea_kextract(mmu, (vm_offset_t)pm)) == NULL)
  935                 pmr = pm;
  936 
  937         pm->pm_active |= PCPU_GET(cpumask);
  938         PCPU_SET(curpmap, pmr);
  939 }
  940 
  941 void
  942 moea_deactivate(mmu_t mmu, struct thread *td)
  943 {
  944         pmap_t  pm;
  945 
  946         pm = &td->td_proc->p_vmspace->vm_pmap;
  947         pm->pm_active &= ~(PCPU_GET(cpumask));
  948         PCPU_SET(curpmap, NULL);
  949 }
  950 
  951 void
  952 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
  953 {
  954         struct  pvo_entry *pvo;
  955 
  956         PMAP_LOCK(pm);
  957         pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
  958 
  959         if (pvo != NULL) {
  960                 if (wired) {
  961                         if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
  962                                 pm->pm_stats.wired_count++;
  963                         pvo->pvo_vaddr |= PVO_WIRED;
  964                 } else {
  965                         if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
  966                                 pm->pm_stats.wired_count--;
  967                         pvo->pvo_vaddr &= ~PVO_WIRED;
  968                 }
  969         }
  970         PMAP_UNLOCK(pm);
  971 }
  972 
  973 void
  974 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
  975 {
  976         vm_offset_t     dst;
  977         vm_offset_t     src;
  978 
  979         dst = VM_PAGE_TO_PHYS(mdst);
  980         src = VM_PAGE_TO_PHYS(msrc);
  981 
  982         kcopy((void *)src, (void *)dst, PAGE_SIZE);
  983 }
  984 
  985 /*
  986  * Zero a page of physical memory by temporarily mapping it into the tlb.
  987  */
  988 void
  989 moea_zero_page(mmu_t mmu, vm_page_t m)
  990 {
  991         vm_offset_t pa = VM_PAGE_TO_PHYS(m);
  992         caddr_t va;
  993 
  994         if (pa < SEGMENT_LENGTH) {
  995                 va = (caddr_t) pa;
  996         } else if (moea_initialized) {
  997                 if (moea_pvo_zeropage == NULL) {
  998                         moea_pvo_zeropage = moea_rkva_alloc(mmu);
  999                         mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page",
 1000                             NULL, MTX_DEF);
 1001                 }
 1002                 mtx_lock(&moea_pvo_zeropage_mtx);
 1003                 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL);
 1004                 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage);
 1005         } else {
 1006                 panic("moea_zero_page: can't zero pa %#x", pa);
 1007         }
 1008 
 1009         bzero(va, PAGE_SIZE);
 1010 
 1011         if (pa >= SEGMENT_LENGTH) {
 1012                 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL);
 1013                 mtx_unlock(&moea_pvo_zeropage_mtx);
 1014         }
 1015 }
 1016 
 1017 void
 1018 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
 1019 {
 1020         vm_offset_t pa = VM_PAGE_TO_PHYS(m);
 1021         caddr_t va;
 1022 
 1023         if (pa < SEGMENT_LENGTH) {
 1024                 va = (caddr_t) pa;
 1025         } else if (moea_initialized) {
 1026                 if (moea_pvo_zeropage == NULL) {
 1027                         moea_pvo_zeropage = moea_rkva_alloc(mmu);
 1028                         mtx_init(&moea_pvo_zeropage_mtx, "pvo zero page",
 1029                             NULL, MTX_DEF);
 1030                 }
 1031                 mtx_lock(&moea_pvo_zeropage_mtx);
 1032                 moea_pa_map(moea_pvo_zeropage, pa, NULL, NULL);
 1033                 va = (caddr_t)PVO_VADDR(moea_pvo_zeropage);
 1034         } else {
 1035                 panic("moea_zero_page: can't zero pa %#x", pa);
 1036         }
 1037 
 1038         bzero(va + off, size);
 1039 
 1040         if (pa >= SEGMENT_LENGTH) {
 1041                 moea_pa_unmap(moea_pvo_zeropage, NULL, NULL);
 1042                 mtx_unlock(&moea_pvo_zeropage_mtx);
 1043         }
 1044 }
 1045 
 1046 void
 1047 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
 1048 {
 1049 
 1050         moea_zero_page(mmu, m);
 1051 }
 1052 
 1053 /*
 1054  * Map the given physical page at the specified virtual address in the
 1055  * target pmap with the protection requested.  If specified the page
 1056  * will be wired down.
 1057  */
 1058 void
 1059 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
 1060            boolean_t wired)
 1061 {
 1062 
 1063         vm_page_lock_queues();
 1064         PMAP_LOCK(pmap);
 1065         moea_enter_locked(pmap, va, m, prot, wired);
 1066         vm_page_unlock_queues();
 1067         PMAP_UNLOCK(pmap);
 1068 }
 1069 
 1070 /*
 1071  * Map the given physical page at the specified virtual address in the
 1072  * target pmap with the protection requested.  If specified the page
 1073  * will be wired down.
 1074  *
 1075  * The page queues and pmap must be locked.
 1076  */
 1077 static void
 1078 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
 1079     boolean_t wired)
 1080 {
 1081         struct          pvo_head *pvo_head;
 1082         uma_zone_t      zone;
 1083         vm_page_t       pg;
 1084         u_int           pte_lo, pvo_flags, was_exec, i;
 1085         int             error;
 1086 
 1087         if (!moea_initialized) {
 1088                 pvo_head = &moea_pvo_kunmanaged;
 1089                 zone = moea_upvo_zone;
 1090                 pvo_flags = 0;
 1091                 pg = NULL;
 1092                 was_exec = PTE_EXEC;
 1093         } else {
 1094                 pvo_head = vm_page_to_pvoh(m);
 1095                 pg = m;
 1096                 zone = moea_mpvo_zone;
 1097                 pvo_flags = PVO_MANAGED;
 1098                 was_exec = 0;
 1099         }
 1100         if (pmap_bootstrapped)
 1101                 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
 1102         PMAP_LOCK_ASSERT(pmap, MA_OWNED);
 1103 
 1104         /* XXX change the pvo head for fake pages */
 1105         if ((m->flags & PG_FICTITIOUS) == PG_FICTITIOUS) {
 1106                 pvo_flags &= ~PVO_MANAGED;
 1107                 pvo_head = &moea_pvo_kunmanaged;
 1108                 zone = moea_upvo_zone;
 1109         }
 1110 
 1111         /*
 1112          * If this is a managed page, and it's the first reference to the page,
 1113          * clear the execness of the page.  Otherwise fetch the execness.
 1114          */
 1115         if ((pg != NULL) && ((m->flags & PG_FICTITIOUS) == 0)) {
 1116                 if (LIST_EMPTY(pvo_head)) {
 1117                         moea_attr_clear(pg, PTE_EXEC);
 1118                 } else {
 1119                         was_exec = moea_attr_fetch(pg) & PTE_EXEC;
 1120                 }
 1121         }
 1122 
 1123         /*
 1124          * Assume the page is cache inhibited and access is guarded unless
 1125          * it's in our available memory array.
 1126          */
 1127         pte_lo = PTE_I | PTE_G;
 1128         for (i = 0; i < pregions_sz; i++) {
 1129                 if ((VM_PAGE_TO_PHYS(m) >= pregions[i].mr_start) &&
 1130                     (VM_PAGE_TO_PHYS(m) < 
 1131                         (pregions[i].mr_start + pregions[i].mr_size))) {
 1132                         pte_lo &= ~(PTE_I | PTE_G);
 1133                         break;
 1134                 }
 1135         }
 1136 
 1137         if (prot & VM_PROT_WRITE) {
 1138                 pte_lo |= PTE_BW;
 1139                 if (pmap_bootstrapped)
 1140                         vm_page_flag_set(m, PG_WRITEABLE);
 1141         } else
 1142                 pte_lo |= PTE_BR;
 1143 
 1144         if (prot & VM_PROT_EXECUTE)
 1145                 pvo_flags |= PVO_EXECUTABLE;
 1146 
 1147         if (wired)
 1148                 pvo_flags |= PVO_WIRED;
 1149 
 1150         if ((m->flags & PG_FICTITIOUS) != 0)
 1151                 pvo_flags |= PVO_FAKE;
 1152 
 1153         error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
 1154             pte_lo, pvo_flags);
 1155 
 1156         /*
 1157          * Flush the real page from the instruction cache if this page is
 1158          * mapped executable and cacheable and was not previously mapped (or
 1159          * was not mapped executable).
 1160          */
 1161         if (error == 0 && (pvo_flags & PVO_EXECUTABLE) &&
 1162             (pte_lo & PTE_I) == 0 && was_exec == 0) {
 1163                 /*
 1164                  * Flush the real memory from the cache.
 1165                  */
 1166                 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
 1167                 if (pg != NULL)
 1168                         moea_attr_save(pg, PTE_EXEC);
 1169         }
 1170 
 1171         /* XXX syncicache always until problems are sorted */
 1172         moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
 1173 }
 1174 
 1175 /*
 1176  * Maps a sequence of resident pages belonging to the same object.
 1177  * The sequence begins with the given page m_start.  This page is
 1178  * mapped at the given virtual address start.  Each subsequent page is
 1179  * mapped at a virtual address that is offset from start by the same
 1180  * amount as the page is offset from m_start within the object.  The
 1181  * last page in the sequence is the page with the largest offset from
 1182  * m_start that can be mapped at a virtual address less than the given
 1183  * virtual address end.  Not every virtual page between start and end
 1184  * is mapped; only those for which a resident page exists with the
 1185  * corresponding offset from m_start are mapped.
 1186  */
 1187 void
 1188 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
 1189     vm_page_t m_start, vm_prot_t prot)
 1190 {
 1191         vm_page_t m;
 1192         vm_pindex_t diff, psize;
 1193 
 1194         psize = atop(end - start);
 1195         m = m_start;
 1196         PMAP_LOCK(pm);
 1197         while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
 1198                 moea_enter_locked(pm, start + ptoa(diff), m, prot &
 1199                     (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
 1200                 m = TAILQ_NEXT(m, listq);
 1201         }
 1202         PMAP_UNLOCK(pm);
 1203 }
 1204 
 1205 void
 1206 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
 1207     vm_prot_t prot)
 1208 {
 1209 
 1210         PMAP_LOCK(pm);
 1211         moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
 1212             FALSE);
 1213         PMAP_UNLOCK(pm);
 1214 
 1215 }
 1216 
 1217 vm_paddr_t
 1218 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
 1219 {
 1220         struct  pvo_entry *pvo;
 1221         vm_paddr_t pa;
 1222 
 1223         PMAP_LOCK(pm);
 1224         pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
 1225         if (pvo == NULL)
 1226                 pa = 0;
 1227         else
 1228                 pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
 1229         PMAP_UNLOCK(pm);
 1230         return (pa);
 1231 }
 1232 
 1233 /*
 1234  * Atomically extract and hold the physical page with the given
 1235  * pmap and virtual address pair if that mapping permits the given
 1236  * protection.
 1237  */
 1238 vm_page_t
 1239 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
 1240 {
 1241         struct  pvo_entry *pvo;
 1242         vm_page_t m;
 1243         
 1244         m = NULL;
 1245         vm_page_lock_queues();
 1246         PMAP_LOCK(pmap);
 1247         pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
 1248         if (pvo != NULL && (pvo->pvo_pte.pte_hi & PTE_VALID) &&
 1249             ((pvo->pvo_pte.pte_lo & PTE_PP) == PTE_RW ||
 1250              (prot & VM_PROT_WRITE) == 0)) {
 1251                 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN);
 1252                 vm_page_hold(m);
 1253         }
 1254         vm_page_unlock_queues();
 1255         PMAP_UNLOCK(pmap);
 1256         return (m);
 1257 }
 1258 
 1259 void
 1260 moea_init(mmu_t mmu)
 1261 {
 1262 
 1263         CTR0(KTR_PMAP, "moea_init");
 1264 
 1265         moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
 1266             NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
 1267             UMA_ZONE_VM | UMA_ZONE_NOFREE);
 1268         moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
 1269             NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
 1270             UMA_ZONE_VM | UMA_ZONE_NOFREE);
 1271         moea_initialized = TRUE;
 1272 }
 1273 
 1274 boolean_t
 1275 moea_is_modified(mmu_t mmu, vm_page_t m)
 1276 {
 1277 
 1278         if ((m->flags & (PG_FICTITIOUS |PG_UNMANAGED)) != 0)
 1279                 return (FALSE);
 1280 
 1281         return (moea_query_bit(m, PTE_CHG));
 1282 }
 1283 
 1284 void
 1285 moea_clear_reference(mmu_t mmu, vm_page_t m)
 1286 {
 1287 
 1288         if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
 1289                 return;
 1290         moea_clear_bit(m, PTE_REF, NULL);
 1291 }
 1292 
 1293 void
 1294 moea_clear_modify(mmu_t mmu, vm_page_t m)
 1295 {
 1296 
 1297         if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
 1298                 return;
 1299         moea_clear_bit(m, PTE_CHG, NULL);
 1300 }
 1301 
 1302 /*
 1303  * Clear the write and modified bits in each of the given page's mappings.
 1304  */
 1305 void
 1306 moea_remove_write(mmu_t mmu, vm_page_t m)
 1307 {
 1308         struct  pvo_entry *pvo;
 1309         struct  pte *pt;
 1310         pmap_t  pmap;
 1311         u_int   lo;
 1312 
 1313         mtx_assert(&vm_page_queue_mtx, MA_OWNED);
 1314         if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 ||
 1315             (m->flags & PG_WRITEABLE) == 0)
 1316                 return;
 1317         lo = moea_attr_fetch(m);
 1318         SYNC();
 1319         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 1320                 pmap = pvo->pvo_pmap;
 1321                 PMAP_LOCK(pmap);
 1322                 if ((pvo->pvo_pte.pte_lo & PTE_PP) != PTE_BR) {
 1323                         pt = moea_pvo_to_pte(pvo, -1);
 1324                         pvo->pvo_pte.pte_lo &= ~PTE_PP;
 1325                         pvo->pvo_pte.pte_lo |= PTE_BR;
 1326                         if (pt != NULL) {
 1327                                 moea_pte_synch(pt, &pvo->pvo_pte);
 1328                                 lo |= pvo->pvo_pte.pte_lo;
 1329                                 pvo->pvo_pte.pte_lo &= ~PTE_CHG;
 1330                                 moea_pte_change(pt, &pvo->pvo_pte,
 1331                                     pvo->pvo_vaddr);
 1332                                 mtx_unlock(&moea_table_mutex);
 1333                         }
 1334                 }
 1335                 PMAP_UNLOCK(pmap);
 1336         }
 1337         if ((lo & PTE_CHG) != 0) {
 1338                 moea_attr_clear(m, PTE_CHG);
 1339                 vm_page_dirty(m);
 1340         }
 1341         vm_page_flag_clear(m, PG_WRITEABLE);
 1342 }
 1343 
 1344 /*
 1345  *      moea_ts_referenced:
 1346  *
 1347  *      Return a count of reference bits for a page, clearing those bits.
 1348  *      It is not necessary for every reference bit to be cleared, but it
 1349  *      is necessary that 0 only be returned when there are truly no
 1350  *      reference bits set.
 1351  *
 1352  *      XXX: The exact number of bits to check and clear is a matter that
 1353  *      should be tested and standardized at some point in the future for
 1354  *      optimal aging of shared pages.
 1355  */
 1356 boolean_t
 1357 moea_ts_referenced(mmu_t mmu, vm_page_t m)
 1358 {
 1359         int count;
 1360 
 1361         if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
 1362                 return (0);
 1363 
 1364         count = moea_clear_bit(m, PTE_REF, NULL);
 1365 
 1366         return (count);
 1367 }
 1368 
 1369 /*
 1370  * Map a wired page into kernel virtual address space.
 1371  */
 1372 void
 1373 moea_kenter(mmu_t mmu, vm_offset_t va, vm_offset_t pa)
 1374 {
 1375         u_int           pte_lo;
 1376         int             error;  
 1377         int             i;
 1378 
 1379 #if 0
 1380         if (va < VM_MIN_KERNEL_ADDRESS)
 1381                 panic("moea_kenter: attempt to enter non-kernel address %#x",
 1382                     va);
 1383 #endif
 1384 
 1385         pte_lo = PTE_I | PTE_G;
 1386         for (i = 0; i < pregions_sz; i++) {
 1387                 if ((pa >= pregions[i].mr_start) &&
 1388                     (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
 1389                         pte_lo &= ~(PTE_I | PTE_G);
 1390                         break;
 1391                 }
 1392         }       
 1393 
 1394         PMAP_LOCK(kernel_pmap);
 1395         error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
 1396             &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
 1397 
 1398         if (error != 0 && error != ENOENT)
 1399                 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
 1400                     pa, error);
 1401 
 1402         /*
 1403          * Flush the real memory from the instruction cache.
 1404          */
 1405         if ((pte_lo & (PTE_I | PTE_G)) == 0) {
 1406                 moea_syncicache(pa, PAGE_SIZE);
 1407         }
 1408         PMAP_UNLOCK(kernel_pmap);
 1409 }
 1410 
 1411 /*
 1412  * Extract the physical page address associated with the given kernel virtual
 1413  * address.
 1414  */
 1415 vm_offset_t
 1416 moea_kextract(mmu_t mmu, vm_offset_t va)
 1417 {
 1418         struct          pvo_entry *pvo;
 1419         vm_paddr_t pa;
 1420 
 1421 #ifdef UMA_MD_SMALL_ALLOC
 1422         /*
 1423          * Allow direct mappings
 1424          */
 1425         if (va < VM_MIN_KERNEL_ADDRESS) {
 1426                 return (va);
 1427         }
 1428 #endif
 1429 
 1430         PMAP_LOCK(kernel_pmap);
 1431         pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
 1432         KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
 1433         pa = (pvo->pvo_pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
 1434         PMAP_UNLOCK(kernel_pmap);
 1435         return (pa);
 1436 }
 1437 
 1438 /*
 1439  * Remove a wired page from kernel virtual address space.
 1440  */
 1441 void
 1442 moea_kremove(mmu_t mmu, vm_offset_t va)
 1443 {
 1444 
 1445         moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
 1446 }
 1447 
 1448 /*
 1449  * Map a range of physical addresses into kernel virtual address space.
 1450  *
 1451  * The value passed in *virt is a suggested virtual address for the mapping.
 1452  * Architectures which can support a direct-mapped physical to virtual region
 1453  * can return the appropriate address within that region, leaving '*virt'
 1454  * unchanged.  We cannot and therefore do not; *virt is updated with the
 1455  * first usable address after the mapped region.
 1456  */
 1457 vm_offset_t
 1458 moea_map(mmu_t mmu, vm_offset_t *virt, vm_offset_t pa_start,
 1459     vm_offset_t pa_end, int prot)
 1460 {
 1461         vm_offset_t     sva, va;
 1462 
 1463         sva = *virt;
 1464         va = sva;
 1465         for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
 1466                 moea_kenter(mmu, va, pa_start);
 1467         *virt = va;
 1468         return (sva);
 1469 }
 1470 
 1471 /*
 1472  * Returns true if the pmap's pv is one of the first
 1473  * 16 pvs linked to from this page.  This count may
 1474  * be changed upwards or downwards in the future; it
 1475  * is only necessary that true be returned for a small
 1476  * subset of pmaps for proper page aging.
 1477  */
 1478 boolean_t
 1479 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
 1480 {
 1481         int loops;
 1482         struct pvo_entry *pvo;
 1483 
 1484         if (!moea_initialized || (m->flags & PG_FICTITIOUS))
 1485                 return FALSE;
 1486 
 1487         loops = 0;
 1488         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 1489                 if (pvo->pvo_pmap == pmap)
 1490                         return (TRUE);
 1491                 if (++loops >= 16)
 1492                         break;
 1493         }
 1494 
 1495         return (FALSE);
 1496 }
 1497 
 1498 static u_int    moea_vsidcontext;
 1499 
 1500 void
 1501 moea_pinit(mmu_t mmu, pmap_t pmap)
 1502 {
 1503         int     i, mask;
 1504         u_int   entropy;
 1505 
 1506         KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
 1507         PMAP_LOCK_INIT(pmap);
 1508 
 1509         entropy = 0;
 1510         __asm __volatile("mftb %0" : "=r"(entropy));
 1511 
 1512         /*
 1513          * Allocate some segment registers for this pmap.
 1514          */
 1515         for (i = 0; i < NPMAPS; i += VSID_NBPW) {
 1516                 u_int   hash, n;
 1517 
 1518                 /*
 1519                  * Create a new value by mutiplying by a prime and adding in
 1520                  * entropy from the timebase register.  This is to make the
 1521                  * VSID more random so that the PT hash function collides
 1522                  * less often.  (Note that the prime casues gcc to do shifts
 1523                  * instead of a multiply.)
 1524                  */
 1525                 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
 1526                 hash = moea_vsidcontext & (NPMAPS - 1);
 1527                 if (hash == 0)          /* 0 is special, avoid it */
 1528                         continue;
 1529                 n = hash >> 5;
 1530                 mask = 1 << (hash & (VSID_NBPW - 1));
 1531                 hash = (moea_vsidcontext & 0xfffff);
 1532                 if (moea_vsid_bitmap[n] & mask) {       /* collision? */
 1533                         /* anything free in this bucket? */
 1534                         if (moea_vsid_bitmap[n] == 0xffffffff) {
 1535                                 entropy = (moea_vsidcontext >> 20);
 1536                                 continue;
 1537                         }
 1538                         i = ffs(~moea_vsid_bitmap[i]) - 1;
 1539                         mask = 1 << i;
 1540                         hash &= 0xfffff & ~(VSID_NBPW - 1);
 1541                         hash |= i;
 1542                 }
 1543                 moea_vsid_bitmap[n] |= mask;
 1544                 for (i = 0; i < 16; i++)
 1545                         pmap->pm_sr[i] = VSID_MAKE(i, hash);
 1546                 return;
 1547         }
 1548 
 1549         panic("moea_pinit: out of segments");
 1550 }
 1551 
 1552 /*
 1553  * Initialize the pmap associated with process 0.
 1554  */
 1555 void
 1556 moea_pinit0(mmu_t mmu, pmap_t pm)
 1557 {
 1558 
 1559         moea_pinit(mmu, pm);
 1560         bzero(&pm->pm_stats, sizeof(pm->pm_stats));
 1561 }
 1562 
 1563 /*
 1564  * Set the physical protection on the specified range of this map as requested.
 1565  */
 1566 void
 1567 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
 1568     vm_prot_t prot)
 1569 {
 1570         struct  pvo_entry *pvo;
 1571         struct  pte *pt;
 1572         int     pteidx;
 1573 
 1574         CTR4(KTR_PMAP, "moea_protect: pm=%p sva=%#x eva=%#x prot=%#x", pm, sva,
 1575             eva, prot);
 1576 
 1577 
 1578         KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
 1579             ("moea_protect: non current pmap"));
 1580 
 1581         if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
 1582                 moea_remove(mmu, pm, sva, eva);
 1583                 return;
 1584         }
 1585 
 1586         vm_page_lock_queues();
 1587         PMAP_LOCK(pm);
 1588         for (; sva < eva; sva += PAGE_SIZE) {
 1589                 pvo = moea_pvo_find_va(pm, sva, &pteidx);
 1590                 if (pvo == NULL)
 1591                         continue;
 1592 
 1593                 if ((prot & VM_PROT_EXECUTE) == 0)
 1594                         pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
 1595 
 1596                 /*
 1597                  * Grab the PTE pointer before we diddle with the cached PTE
 1598                  * copy.
 1599                  */
 1600                 pt = moea_pvo_to_pte(pvo, pteidx);
 1601                 /*
 1602                  * Change the protection of the page.
 1603                  */
 1604                 pvo->pvo_pte.pte_lo &= ~PTE_PP;
 1605                 pvo->pvo_pte.pte_lo |= PTE_BR;
 1606 
 1607                 /*
 1608                  * If the PVO is in the page table, update that pte as well.
 1609                  */
 1610                 if (pt != NULL) {
 1611                         moea_pte_change(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 1612                         mtx_unlock(&moea_table_mutex);
 1613                 }
 1614         }
 1615         vm_page_unlock_queues();
 1616         PMAP_UNLOCK(pm);
 1617 }
 1618 
 1619 /*
 1620  * Map a list of wired pages into kernel virtual address space.  This is
 1621  * intended for temporary mappings which do not need page modification or
 1622  * references recorded.  Existing mappings in the region are overwritten.
 1623  */
 1624 void
 1625 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
 1626 {
 1627         vm_offset_t va;
 1628 
 1629         va = sva;
 1630         while (count-- > 0) {
 1631                 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
 1632                 va += PAGE_SIZE;
 1633                 m++;
 1634         }
 1635 }
 1636 
 1637 /*
 1638  * Remove page mappings from kernel virtual address space.  Intended for
 1639  * temporary mappings entered by moea_qenter.
 1640  */
 1641 void
 1642 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
 1643 {
 1644         vm_offset_t va;
 1645 
 1646         va = sva;
 1647         while (count-- > 0) {
 1648                 moea_kremove(mmu, va);
 1649                 va += PAGE_SIZE;
 1650         }
 1651 }
 1652 
 1653 void
 1654 moea_release(mmu_t mmu, pmap_t pmap)
 1655 {
 1656         int idx, mask;
 1657         
 1658         /*
 1659          * Free segment register's VSID
 1660          */
 1661         if (pmap->pm_sr[0] == 0)
 1662                 panic("moea_release");
 1663 
 1664         idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
 1665         mask = 1 << (idx % VSID_NBPW);
 1666         idx /= VSID_NBPW;
 1667         moea_vsid_bitmap[idx] &= ~mask;
 1668         PMAP_LOCK_DESTROY(pmap);
 1669 }
 1670 
 1671 /*
 1672  * Remove the given range of addresses from the specified map.
 1673  */
 1674 void
 1675 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
 1676 {
 1677         struct  pvo_entry *pvo;
 1678         int     pteidx;
 1679 
 1680         vm_page_lock_queues();
 1681         PMAP_LOCK(pm);
 1682         for (; sva < eva; sva += PAGE_SIZE) {
 1683                 pvo = moea_pvo_find_va(pm, sva, &pteidx);
 1684                 if (pvo != NULL) {
 1685                         moea_pvo_remove(pvo, pteidx);
 1686                 }
 1687         }
 1688         PMAP_UNLOCK(pm);
 1689         vm_page_unlock_queues();
 1690 }
 1691 
 1692 /*
 1693  * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
 1694  * will reflect changes in pte's back to the vm_page.
 1695  */
 1696 void
 1697 moea_remove_all(mmu_t mmu, vm_page_t m)
 1698 {
 1699         struct  pvo_head *pvo_head;
 1700         struct  pvo_entry *pvo, *next_pvo;
 1701         pmap_t  pmap;
 1702 
 1703         mtx_assert(&vm_page_queue_mtx, MA_OWNED);
 1704 
 1705         pvo_head = vm_page_to_pvoh(m);
 1706         for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
 1707                 next_pvo = LIST_NEXT(pvo, pvo_vlink);
 1708 
 1709                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 1710                 pmap = pvo->pvo_pmap;
 1711                 PMAP_LOCK(pmap);
 1712                 moea_pvo_remove(pvo, -1);
 1713                 PMAP_UNLOCK(pmap);
 1714         }
 1715         vm_page_flag_clear(m, PG_WRITEABLE);
 1716 }
 1717 
 1718 /*
 1719  * Allocate a physical page of memory directly from the phys_avail map.
 1720  * Can only be called from moea_bootstrap before avail start and end are
 1721  * calculated.
 1722  */
 1723 static vm_offset_t
 1724 moea_bootstrap_alloc(vm_size_t size, u_int align)
 1725 {
 1726         vm_offset_t     s, e;
 1727         int             i, j;
 1728 
 1729         size = round_page(size);
 1730         for (i = 0; phys_avail[i + 1] != 0; i += 2) {
 1731                 if (align != 0)
 1732                         s = (phys_avail[i] + align - 1) & ~(align - 1);
 1733                 else
 1734                         s = phys_avail[i];
 1735                 e = s + size;
 1736 
 1737                 if (s < phys_avail[i] || e > phys_avail[i + 1])
 1738                         continue;
 1739 
 1740                 if (s == phys_avail[i]) {
 1741                         phys_avail[i] += size;
 1742                 } else if (e == phys_avail[i + 1]) {
 1743                         phys_avail[i + 1] -= size;
 1744                 } else {
 1745                         for (j = phys_avail_count * 2; j > i; j -= 2) {
 1746                                 phys_avail[j] = phys_avail[j - 2];
 1747                                 phys_avail[j + 1] = phys_avail[j - 1];
 1748                         }
 1749 
 1750                         phys_avail[i + 3] = phys_avail[i + 1];
 1751                         phys_avail[i + 1] = s;
 1752                         phys_avail[i + 2] = e;
 1753                         phys_avail_count++;
 1754                 }
 1755 
 1756                 return (s);
 1757         }
 1758         panic("moea_bootstrap_alloc: could not allocate memory");
 1759 }
 1760 
 1761 /*
 1762  * Return an unmapped pvo for a kernel virtual address.
 1763  * Used by pmap functions that operate on physical pages.
 1764  */
 1765 static struct pvo_entry *
 1766 moea_rkva_alloc(mmu_t mmu)
 1767 {
 1768         struct          pvo_entry *pvo;
 1769         struct          pte *pt;
 1770         vm_offset_t     kva;
 1771         int             pteidx;
 1772 
 1773         if (moea_rkva_count == 0)
 1774                 panic("moea_rkva_alloc: no more reserved KVAs");
 1775 
 1776         kva = moea_rkva_start + (PAGE_SIZE * --moea_rkva_count);
 1777         moea_kenter(mmu, kva, 0);
 1778 
 1779         pvo = moea_pvo_find_va(kernel_pmap, kva, &pteidx);
 1780 
 1781         if (pvo == NULL)
 1782                 panic("moea_kva_alloc: moea_pvo_find_va failed");
 1783 
 1784         pt = moea_pvo_to_pte(pvo, pteidx);
 1785 
 1786         if (pt == NULL)
 1787                 panic("moea_kva_alloc: moea_pvo_to_pte failed");
 1788 
 1789         moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 1790         mtx_unlock(&moea_table_mutex);
 1791         PVO_PTEGIDX_CLR(pvo);
 1792 
 1793         moea_pte_overflow++;
 1794 
 1795         return (pvo);
 1796 }
 1797 
 1798 static void
 1799 moea_pa_map(struct pvo_entry *pvo, vm_offset_t pa, struct pte *saved_pt,
 1800     int *depth_p)
 1801 {
 1802         struct  pte *pt;
 1803 
 1804         /*
 1805          * If this pvo already has a valid pte, we need to save it so it can
 1806          * be restored later.  We then just reload the new PTE over the old
 1807          * slot.
 1808          */
 1809         if (saved_pt != NULL) {
 1810                 pt = moea_pvo_to_pte(pvo, -1);
 1811 
 1812                 if (pt != NULL) {
 1813                         moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 1814                         mtx_unlock(&moea_table_mutex);
 1815                         PVO_PTEGIDX_CLR(pvo);
 1816                         moea_pte_overflow++;
 1817                 }
 1818 
 1819                 *saved_pt = pvo->pvo_pte;
 1820 
 1821                 pvo->pvo_pte.pte_lo &= ~PTE_RPGN;
 1822         }
 1823 
 1824         pvo->pvo_pte.pte_lo |= pa;
 1825 
 1826         if (!moea_pte_spill(pvo->pvo_vaddr))
 1827                 panic("moea_pa_map: could not spill pvo %p", pvo);
 1828 
 1829         if (depth_p != NULL)
 1830                 (*depth_p)++;
 1831 }
 1832 
 1833 static void
 1834 moea_pa_unmap(struct pvo_entry *pvo, struct pte *saved_pt, int *depth_p)
 1835 {
 1836         struct  pte *pt;
 1837 
 1838         pt = moea_pvo_to_pte(pvo, -1);
 1839 
 1840         if (pt != NULL) {
 1841                 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 1842                 mtx_unlock(&moea_table_mutex);
 1843                 PVO_PTEGIDX_CLR(pvo);
 1844                 moea_pte_overflow++;
 1845         }
 1846 
 1847         pvo->pvo_pte.pte_lo &= ~PTE_RPGN;
 1848 
 1849         /*
 1850          * If there is a saved PTE and it's valid, restore it and return.
 1851          */
 1852         if (saved_pt != NULL && (saved_pt->pte_lo & PTE_RPGN) != 0) {
 1853                 if (depth_p != NULL && --(*depth_p) == 0)
 1854                         panic("moea_pa_unmap: restoring but depth == 0");
 1855 
 1856                 pvo->pvo_pte = *saved_pt;
 1857 
 1858                 if (!moea_pte_spill(pvo->pvo_vaddr))
 1859                         panic("moea_pa_unmap: could not spill pvo %p", pvo);
 1860         }
 1861 }
 1862 
 1863 static void
 1864 moea_syncicache(vm_offset_t pa, vm_size_t len)
 1865 {
 1866         __syncicache((void *)pa, len);
 1867 }
 1868 
 1869 static void
 1870 tlbia(void)
 1871 {
 1872         caddr_t i;
 1873 
 1874         SYNC();
 1875         for (i = 0; i < (caddr_t)0x00040000; i += 0x00001000) {
 1876                 TLBIE(i);
 1877                 EIEIO();
 1878         }
 1879         TLBSYNC();
 1880         SYNC();
 1881 }
 1882 
 1883 static int
 1884 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
 1885     vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
 1886 {
 1887         struct  pvo_entry *pvo;
 1888         u_int   sr;
 1889         int     first;
 1890         u_int   ptegidx;
 1891         int     i;
 1892         int     bootstrap;
 1893 
 1894         moea_pvo_enter_calls++;
 1895         first = 0;
 1896         bootstrap = 0;
 1897 
 1898         /*
 1899          * Compute the PTE Group index.
 1900          */
 1901         va &= ~ADDR_POFF;
 1902         sr = va_to_sr(pm->pm_sr, va);
 1903         ptegidx = va_to_pteg(sr, va);
 1904 
 1905         /*
 1906          * Remove any existing mapping for this page.  Reuse the pvo entry if
 1907          * there is a mapping.
 1908          */
 1909         mtx_lock(&moea_table_mutex);
 1910         LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
 1911                 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
 1912                         if ((pvo->pvo_pte.pte_lo & PTE_RPGN) == pa &&
 1913                             (pvo->pvo_pte.pte_lo & PTE_PP) ==
 1914                             (pte_lo & PTE_PP)) {
 1915                                 mtx_unlock(&moea_table_mutex);
 1916                                 return (0);
 1917                         }
 1918                         moea_pvo_remove(pvo, -1);
 1919                         break;
 1920                 }
 1921         }
 1922 
 1923         /*
 1924          * If we aren't overwriting a mapping, try to allocate.
 1925          */
 1926         if (moea_initialized) {
 1927                 pvo = uma_zalloc(zone, M_NOWAIT);
 1928         } else {
 1929                 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
 1930                         panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
 1931                               moea_bpvo_pool_index, BPVO_POOL_SIZE, 
 1932                               BPVO_POOL_SIZE * sizeof(struct pvo_entry));
 1933                 }
 1934                 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
 1935                 moea_bpvo_pool_index++;
 1936                 bootstrap = 1;
 1937         }
 1938 
 1939         if (pvo == NULL) {
 1940                 mtx_unlock(&moea_table_mutex);
 1941                 return (ENOMEM);
 1942         }
 1943 
 1944         moea_pvo_entries++;
 1945         pvo->pvo_vaddr = va;
 1946         pvo->pvo_pmap = pm;
 1947         LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
 1948         pvo->pvo_vaddr &= ~ADDR_POFF;
 1949         if (flags & VM_PROT_EXECUTE)
 1950                 pvo->pvo_vaddr |= PVO_EXECUTABLE;
 1951         if (flags & PVO_WIRED)
 1952                 pvo->pvo_vaddr |= PVO_WIRED;
 1953         if (pvo_head != &moea_pvo_kunmanaged)
 1954                 pvo->pvo_vaddr |= PVO_MANAGED;
 1955         if (bootstrap)
 1956                 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
 1957         if (flags & PVO_FAKE)
 1958                 pvo->pvo_vaddr |= PVO_FAKE;
 1959 
 1960         moea_pte_create(&pvo->pvo_pte, sr, va, pa | pte_lo);
 1961 
 1962         /*
 1963          * Remember if the list was empty and therefore will be the first
 1964          * item.
 1965          */
 1966         if (LIST_FIRST(pvo_head) == NULL)
 1967                 first = 1;
 1968         LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
 1969 
 1970         if (pvo->pvo_pte.pte_lo & PVO_WIRED)
 1971                 pm->pm_stats.wired_count++;
 1972         pm->pm_stats.resident_count++;
 1973 
 1974         /*
 1975          * We hope this succeeds but it isn't required.
 1976          */
 1977         i = moea_pte_insert(ptegidx, &pvo->pvo_pte);
 1978         if (i >= 0) {
 1979                 PVO_PTEGIDX_SET(pvo, i);
 1980         } else {
 1981                 panic("moea_pvo_enter: overflow");
 1982                 moea_pte_overflow++;
 1983         }
 1984         mtx_unlock(&moea_table_mutex);
 1985 
 1986         return (first ? ENOENT : 0);
 1987 }
 1988 
 1989 static void
 1990 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
 1991 {
 1992         struct  pte *pt;
 1993 
 1994         /*
 1995          * If there is an active pte entry, we need to deactivate it (and
 1996          * save the ref & cfg bits).
 1997          */
 1998         pt = moea_pvo_to_pte(pvo, pteidx);
 1999         if (pt != NULL) {
 2000                 moea_pte_unset(pt, &pvo->pvo_pte, pvo->pvo_vaddr);
 2001                 mtx_unlock(&moea_table_mutex);
 2002                 PVO_PTEGIDX_CLR(pvo);
 2003         } else {
 2004                 moea_pte_overflow--;
 2005         }
 2006 
 2007         /*
 2008          * Update our statistics.
 2009          */
 2010         pvo->pvo_pmap->pm_stats.resident_count--;
 2011         if (pvo->pvo_pte.pte_lo & PVO_WIRED)
 2012                 pvo->pvo_pmap->pm_stats.wired_count--;
 2013 
 2014         /*
 2015          * Save the REF/CHG bits into their cache if the page is managed.
 2016          */
 2017         if ((pvo->pvo_vaddr & (PVO_MANAGED|PVO_FAKE)) == PVO_MANAGED) {
 2018                 struct  vm_page *pg;
 2019 
 2020                 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte_lo & PTE_RPGN);
 2021                 if (pg != NULL) {
 2022                         moea_attr_save(pg, pvo->pvo_pte.pte_lo &
 2023                             (PTE_REF | PTE_CHG));
 2024                 }
 2025         }
 2026 
 2027         /*
 2028          * Remove this PVO from the PV list.
 2029          */
 2030         LIST_REMOVE(pvo, pvo_vlink);
 2031 
 2032         /*
 2033          * Remove this from the overflow list and return it to the pool
 2034          * if we aren't going to reuse it.
 2035          */
 2036         LIST_REMOVE(pvo, pvo_olink);
 2037         if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
 2038                 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
 2039                     moea_upvo_zone, pvo);
 2040         moea_pvo_entries--;
 2041         moea_pvo_remove_calls++;
 2042 }
 2043 
 2044 static __inline int
 2045 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
 2046 {
 2047         int     pteidx;
 2048 
 2049         /*
 2050          * We can find the actual pte entry without searching by grabbing
 2051          * the PTEG index from 3 unused bits in pte_lo[11:9] and by
 2052          * noticing the HID bit.
 2053          */
 2054         pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
 2055         if (pvo->pvo_pte.pte_hi & PTE_HID)
 2056                 pteidx ^= moea_pteg_mask * 8;
 2057 
 2058         return (pteidx);
 2059 }
 2060 
 2061 static struct pvo_entry *
 2062 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
 2063 {
 2064         struct  pvo_entry *pvo;
 2065         int     ptegidx;
 2066         u_int   sr;
 2067 
 2068         va &= ~ADDR_POFF;
 2069         sr = va_to_sr(pm->pm_sr, va);
 2070         ptegidx = va_to_pteg(sr, va);
 2071 
 2072         mtx_lock(&moea_table_mutex);
 2073         LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
 2074                 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
 2075                         if (pteidx_p)
 2076                                 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
 2077                         break;
 2078                 }
 2079         }
 2080         mtx_unlock(&moea_table_mutex);
 2081 
 2082         return (pvo);
 2083 }
 2084 
 2085 static struct pte *
 2086 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
 2087 {
 2088         struct  pte *pt;
 2089 
 2090         /*
 2091          * If we haven't been supplied the ptegidx, calculate it.
 2092          */
 2093         if (pteidx == -1) {
 2094                 int     ptegidx;
 2095                 u_int   sr;
 2096 
 2097                 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
 2098                 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
 2099                 pteidx = moea_pvo_pte_index(pvo, ptegidx);
 2100         }
 2101 
 2102         pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
 2103         mtx_lock(&moea_table_mutex);
 2104 
 2105         if ((pvo->pvo_pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
 2106                 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
 2107                     "valid pte index", pvo);
 2108         }
 2109 
 2110         if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
 2111                 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
 2112                     "pvo but no valid pte", pvo);
 2113         }
 2114 
 2115         if ((pt->pte_hi ^ (pvo->pvo_pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
 2116                 if ((pvo->pvo_pte.pte_hi & PTE_VALID) == 0) {
 2117                         panic("moea_pvo_to_pte: pvo %p has valid pte in "
 2118                             "moea_pteg_table %p but invalid in pvo", pvo, pt);
 2119                 }
 2120 
 2121                 if (((pt->pte_lo ^ pvo->pvo_pte.pte_lo) & ~(PTE_CHG|PTE_REF))
 2122                     != 0) {
 2123                         panic("moea_pvo_to_pte: pvo %p pte does not match "
 2124                             "pte %p in moea_pteg_table", pvo, pt);
 2125                 }
 2126 
 2127                 mtx_assert(&moea_table_mutex, MA_OWNED);
 2128                 return (pt);
 2129         }
 2130 
 2131         if (pvo->pvo_pte.pte_hi & PTE_VALID) {
 2132                 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
 2133                     "moea_pteg_table but valid in pvo", pvo, pt);
 2134         }
 2135 
 2136         mtx_unlock(&moea_table_mutex);
 2137         return (NULL);
 2138 }
 2139 
 2140 /*
 2141  * XXX: THIS STUFF SHOULD BE IN pte.c?
 2142  */
 2143 int
 2144 moea_pte_spill(vm_offset_t addr)
 2145 {
 2146         struct  pvo_entry *source_pvo, *victim_pvo;
 2147         struct  pvo_entry *pvo;
 2148         int     ptegidx, i, j;
 2149         u_int   sr;
 2150         struct  pteg *pteg;
 2151         struct  pte *pt;
 2152 
 2153         moea_pte_spills++;
 2154 
 2155         sr = mfsrin(addr);
 2156         ptegidx = va_to_pteg(sr, addr);
 2157 
 2158         /*
 2159          * Have to substitute some entry.  Use the primary hash for this.
 2160          * Use low bits of timebase as random generator.
 2161          */
 2162         pteg = &moea_pteg_table[ptegidx];
 2163         mtx_lock(&moea_table_mutex);
 2164         __asm __volatile("mftb %0" : "=r"(i));
 2165         i &= 7;
 2166         pt = &pteg->pt[i];
 2167 
 2168         source_pvo = NULL;
 2169         victim_pvo = NULL;
 2170         LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
 2171                 /*
 2172                  * We need to find a pvo entry for this address.
 2173                  */
 2174                 MOEA_PVO_CHECK(pvo);
 2175                 if (source_pvo == NULL &&
 2176                     moea_pte_match(&pvo->pvo_pte, sr, addr,
 2177                     pvo->pvo_pte.pte_hi & PTE_HID)) {
 2178                         /*
 2179                          * Now found an entry to be spilled into the pteg.
 2180                          * The PTE is now valid, so we know it's active.
 2181                          */
 2182                         j = moea_pte_insert(ptegidx, &pvo->pvo_pte);
 2183 
 2184                         if (j >= 0) {
 2185                                 PVO_PTEGIDX_SET(pvo, j);
 2186                                 moea_pte_overflow--;
 2187                                 MOEA_PVO_CHECK(pvo);
 2188                                 mtx_unlock(&moea_table_mutex);
 2189                                 return (1);
 2190                         }
 2191 
 2192                         source_pvo = pvo;
 2193 
 2194                         if (victim_pvo != NULL)
 2195                                 break;
 2196                 }
 2197 
 2198                 /*
 2199                  * We also need the pvo entry of the victim we are replacing
 2200                  * so save the R & C bits of the PTE.
 2201                  */
 2202                 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
 2203                     moea_pte_compare(pt, &pvo->pvo_pte)) {
 2204                         victim_pvo = pvo;
 2205                         if (source_pvo != NULL)
 2206                                 break;
 2207                 }
 2208         }
 2209 
 2210         if (source_pvo == NULL) {
 2211                 mtx_unlock(&moea_table_mutex);
 2212                 return (0);
 2213         }
 2214 
 2215         if (victim_pvo == NULL) {
 2216                 if ((pt->pte_hi & PTE_HID) == 0)
 2217                         panic("moea_pte_spill: victim p-pte (%p) has no pvo"
 2218                             "entry", pt);
 2219 
 2220                 /*
 2221                  * If this is a secondary PTE, we need to search it's primary
 2222                  * pvo bucket for the matching PVO.
 2223                  */
 2224                 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
 2225                     pvo_olink) {
 2226                         MOEA_PVO_CHECK(pvo);
 2227                         /*
 2228                          * We also need the pvo entry of the victim we are
 2229                          * replacing so save the R & C bits of the PTE.
 2230                          */
 2231                         if (moea_pte_compare(pt, &pvo->pvo_pte)) {
 2232                                 victim_pvo = pvo;
 2233                                 break;
 2234                         }
 2235                 }
 2236 
 2237                 if (victim_pvo == NULL)
 2238                         panic("moea_pte_spill: victim s-pte (%p) has no pvo"
 2239                             "entry", pt);
 2240         }
 2241 
 2242         /*
 2243          * We are invalidating the TLB entry for the EA we are replacing even
 2244          * though it's valid.  If we don't, we lose any ref/chg bit changes
 2245          * contained in the TLB entry.
 2246          */
 2247         source_pvo->pvo_pte.pte_hi &= ~PTE_HID;
 2248 
 2249         moea_pte_unset(pt, &victim_pvo->pvo_pte, victim_pvo->pvo_vaddr);
 2250         moea_pte_set(pt, &source_pvo->pvo_pte);
 2251 
 2252         PVO_PTEGIDX_CLR(victim_pvo);
 2253         PVO_PTEGIDX_SET(source_pvo, i);
 2254         moea_pte_replacements++;
 2255 
 2256         MOEA_PVO_CHECK(victim_pvo);
 2257         MOEA_PVO_CHECK(source_pvo);
 2258 
 2259         mtx_unlock(&moea_table_mutex);
 2260         return (1);
 2261 }
 2262 
 2263 static int
 2264 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
 2265 {
 2266         struct  pte *pt;
 2267         int     i;
 2268 
 2269         mtx_assert(&moea_table_mutex, MA_OWNED);
 2270 
 2271         /*
 2272          * First try primary hash.
 2273          */
 2274         for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
 2275                 if ((pt->pte_hi & PTE_VALID) == 0) {
 2276                         pvo_pt->pte_hi &= ~PTE_HID;
 2277                         moea_pte_set(pt, pvo_pt);
 2278                         return (i);
 2279                 }
 2280         }
 2281 
 2282         /*
 2283          * Now try secondary hash.
 2284          */
 2285         ptegidx ^= moea_pteg_mask;
 2286 
 2287         for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
 2288                 if ((pt->pte_hi & PTE_VALID) == 0) {
 2289                         pvo_pt->pte_hi |= PTE_HID;
 2290                         moea_pte_set(pt, pvo_pt);
 2291                         return (i);
 2292                 }
 2293         }
 2294 
 2295         panic("moea_pte_insert: overflow");
 2296         return (-1);
 2297 }
 2298 
 2299 static boolean_t
 2300 moea_query_bit(vm_page_t m, int ptebit)
 2301 {
 2302         struct  pvo_entry *pvo;
 2303         struct  pte *pt;
 2304 
 2305 #if 0
 2306         if (moea_attr_fetch(m) & ptebit)
 2307                 return (TRUE);
 2308 #endif
 2309 
 2310         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 2311                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2312 
 2313                 /*
 2314                  * See if we saved the bit off.  If so, cache it and return
 2315                  * success.
 2316                  */
 2317                 if (pvo->pvo_pte.pte_lo & ptebit) {
 2318                         moea_attr_save(m, ptebit);
 2319                         MOEA_PVO_CHECK(pvo);    /* sanity check */
 2320                         return (TRUE);
 2321                 }
 2322         }
 2323 
 2324         /*
 2325          * No luck, now go through the hard part of looking at the PTEs
 2326          * themselves.  Sync so that any pending REF/CHG bits are flushed to
 2327          * the PTEs.
 2328          */
 2329         SYNC();
 2330         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 2331                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2332 
 2333                 /*
 2334                  * See if this pvo has a valid PTE.  if so, fetch the
 2335                  * REF/CHG bits from the valid PTE.  If the appropriate
 2336                  * ptebit is set, cache it and return success.
 2337                  */
 2338                 pt = moea_pvo_to_pte(pvo, -1);
 2339                 if (pt != NULL) {
 2340                         moea_pte_synch(pt, &pvo->pvo_pte);
 2341                         mtx_unlock(&moea_table_mutex);
 2342                         if (pvo->pvo_pte.pte_lo & ptebit) {
 2343                                 moea_attr_save(m, ptebit);
 2344                                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2345                                 return (TRUE);
 2346                         }
 2347                 }
 2348         }
 2349 
 2350         return (FALSE);
 2351 }
 2352 
 2353 static u_int
 2354 moea_clear_bit(vm_page_t m, int ptebit, int *origbit)
 2355 {
 2356         u_int   count;
 2357         struct  pvo_entry *pvo;
 2358         struct  pte *pt;
 2359         int     rv;
 2360 
 2361         /*
 2362          * Clear the cached value.
 2363          */
 2364         rv = moea_attr_fetch(m);
 2365         moea_attr_clear(m, ptebit);
 2366 
 2367         /*
 2368          * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
 2369          * we can reset the right ones).  note that since the pvo entries and
 2370          * list heads are accessed via BAT0 and are never placed in the page
 2371          * table, we don't have to worry about further accesses setting the
 2372          * REF/CHG bits.
 2373          */
 2374         SYNC();
 2375 
 2376         /*
 2377          * For each pvo entry, clear the pvo's ptebit.  If this pvo has a
 2378          * valid pte clear the ptebit from the valid pte.
 2379          */
 2380         count = 0;
 2381         LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
 2382                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2383                 pt = moea_pvo_to_pte(pvo, -1);
 2384                 if (pt != NULL) {
 2385                         moea_pte_synch(pt, &pvo->pvo_pte);
 2386                         if (pvo->pvo_pte.pte_lo & ptebit) {
 2387                                 count++;
 2388                                 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
 2389                         }
 2390                         mtx_unlock(&moea_table_mutex);
 2391                 }
 2392                 rv |= pvo->pvo_pte.pte_lo;
 2393                 pvo->pvo_pte.pte_lo &= ~ptebit;
 2394                 MOEA_PVO_CHECK(pvo);    /* sanity check */
 2395         }
 2396 
 2397         if (origbit != NULL) {
 2398                 *origbit = rv;
 2399         }
 2400 
 2401         return (count);
 2402 }
 2403 
 2404 /*
 2405  * Return true if the physical range is encompassed by the battable[idx]
 2406  */
 2407 static int
 2408 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
 2409 {
 2410         u_int prot;
 2411         u_int32_t start;
 2412         u_int32_t end;
 2413         u_int32_t bat_ble;
 2414 
 2415         /*
 2416          * Return immediately if not a valid mapping
 2417          */
 2418         if (!battable[idx].batu & BAT_Vs)
 2419                 return (EINVAL);
 2420 
 2421         /*
 2422          * The BAT entry must be cache-inhibited, guarded, and r/w
 2423          * so it can function as an i/o page
 2424          */
 2425         prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
 2426         if (prot != (BAT_I|BAT_G|BAT_PP_RW))
 2427                 return (EPERM); 
 2428 
 2429         /*
 2430          * The address should be within the BAT range. Assume that the
 2431          * start address in the BAT has the correct alignment (thus
 2432          * not requiring masking)
 2433          */
 2434         start = battable[idx].batl & BAT_PBS;
 2435         bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
 2436         end = start | (bat_ble << 15) | 0x7fff;
 2437 
 2438         if ((pa < start) || ((pa + size) > end))
 2439                 return (ERANGE);
 2440 
 2441         return (0);
 2442 }
 2443 
 2444 boolean_t
 2445 moea_dev_direct_mapped(mmu_t mmu, vm_offset_t pa, vm_size_t size)
 2446 {
 2447         int i;
 2448 
 2449         /*
 2450          * This currently does not work for entries that 
 2451          * overlap 256M BAT segments.
 2452          */
 2453 
 2454         for(i = 0; i < 16; i++)
 2455                 if (moea_bat_mapped(i, pa, size) == 0)
 2456                         return (0);
 2457 
 2458         return (EFAULT);
 2459 }
 2460 
 2461 boolean_t
 2462 moea_page_executable(mmu_t mmu, vm_page_t pg)
 2463 {
 2464         return ((moea_attr_fetch(pg) & PTE_EXEC) == PTE_EXEC);
 2465 }
 2466 
 2467 /*
 2468  * Map a set of physical memory pages into the kernel virtual
 2469  * address space. Return a pointer to where it is mapped. This
 2470  * routine is intended to be used for mapping device memory,
 2471  * NOT real memory.
 2472  */
 2473 void *
 2474 moea_mapdev(mmu_t mmu, vm_offset_t pa, vm_size_t size)
 2475 {
 2476         vm_offset_t va, tmpva, ppa, offset;
 2477         int i;
 2478 
 2479         ppa = trunc_page(pa);
 2480         offset = pa & PAGE_MASK;
 2481         size = roundup(offset + size, PAGE_SIZE);
 2482         
 2483         GIANT_REQUIRED;
 2484 
 2485         /*
 2486          * If the physical address lies within a valid BAT table entry,
 2487          * return the 1:1 mapping. This currently doesn't work
 2488          * for regions that overlap 256M BAT segments.
 2489          */
 2490         for (i = 0; i < 16; i++) {
 2491                 if (moea_bat_mapped(i, pa, size) == 0)
 2492                         return ((void *) pa);
 2493         }
 2494 
 2495         va = kmem_alloc_nofault(kernel_map, size);
 2496         if (!va)
 2497                 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
 2498 
 2499         for (tmpva = va; size > 0;) {
 2500                 moea_kenter(mmu, tmpva, ppa);
 2501                 TLBIE(tmpva); /* XXX or should it be invalidate-all ? */
 2502                 size -= PAGE_SIZE;
 2503                 tmpva += PAGE_SIZE;
 2504                 ppa += PAGE_SIZE;
 2505         }
 2506 
 2507         return ((void *)(va + offset));
 2508 }
 2509 
 2510 void
 2511 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
 2512 {
 2513         vm_offset_t base, offset;
 2514 
 2515         /*
 2516          * If this is outside kernel virtual space, then it's a
 2517          * battable entry and doesn't require unmapping
 2518          */
 2519         if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
 2520                 base = trunc_page(va);
 2521                 offset = va & PAGE_MASK;
 2522                 size = roundup(offset + size, PAGE_SIZE);
 2523                 kmem_free(kernel_map, base, size);
 2524         }
 2525 }

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