1 /*-
2 * Copyright (c) 2008 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/ktr.h>
34 #include <sys/bus.h>
35 #include <sys/cpuset.h>
36 #include <sys/lock.h>
37 #include <sys/malloc.h>
38 #include <sys/mutex.h>
39 #include <sys/pcpu.h>
40 #include <sys/proc.h>
41 #include <sys/sched.h>
42 #include <sys/smp.h>
43
44 #include <vm/vm.h>
45 #include <vm/vm_param.h>
46 #include <vm/pmap.h>
47 #include <vm/vm_map.h>
48 #include <vm/vm_extern.h>
49 #include <vm/vm_kern.h>
50
51 #include <machine/bus.h>
52 #include <machine/cpu.h>
53 #include <machine/intr_machdep.h>
54 #include <machine/pcb.h>
55 #include <machine/platform.h>
56 #include <machine/md_var.h>
57 #include <machine/setjmp.h>
58 #include <machine/smp.h>
59
60 #include "pic_if.h"
61
62 extern struct pcpu __pcpu[MAXCPU];
63
64 volatile static int ap_awake;
65 volatile static u_int ap_letgo;
66 volatile static u_quad_t ap_timebase;
67 static u_int ipi_msg_cnt[32];
68 static struct mtx ap_boot_mtx;
69 struct pcb stoppcbs[MAXCPU];
70 int longfault(faultbuf, int);
71
72 void
73 machdep_ap_bootstrap(void)
74 {
75
76 /* Set PIR */
77 PCPU_SET(pir, mfspr(SPR_PIR));
78 PCPU_SET(awake, 1);
79 __asm __volatile("msync; isync");
80
81 while (ap_letgo == 0)
82 ;
83
84 /* Initialize DEC and TB, sync with the BSP values */
85 #ifdef __powerpc64__
86 /* Writing to the time base register is hypervisor-privileged */
87 if (mfmsr() & PSL_HV)
88 mttb(ap_timebase);
89 #else
90 mttb(ap_timebase);
91 #endif
92 decr_ap_init();
93
94 /* Give platform code a chance to do anything necessary */
95 platform_smp_ap_init();
96
97 /* Serialize console output and AP count increment */
98 mtx_lock_spin(&ap_boot_mtx);
99 ap_awake++;
100 printf("SMP: AP CPU #%d launched\n", PCPU_GET(cpuid));
101 mtx_unlock_spin(&ap_boot_mtx);
102
103 /* Start per-CPU event timers. */
104 cpu_initclocks_ap();
105
106 /* Announce ourselves awake, and enter the scheduler */
107 sched_throw(NULL);
108 }
109
110 void
111 cpu_mp_setmaxid(void)
112 {
113 struct cpuref cpuref;
114 int error;
115
116 mp_ncpus = 0;
117 error = platform_smp_first_cpu(&cpuref);
118 while (!error) {
119 mp_ncpus++;
120 error = platform_smp_next_cpu(&cpuref);
121 }
122 /* Sanity. */
123 if (mp_ncpus == 0)
124 mp_ncpus = 1;
125
126 /*
127 * Set the largest cpuid we're going to use. This is necessary
128 * for VM initialization.
129 */
130 mp_maxid = min(mp_ncpus, MAXCPU) - 1;
131 }
132
133 int
134 cpu_mp_probe(void)
135 {
136
137 /*
138 * We're not going to enable SMP if there's only 1 processor.
139 */
140 return (mp_ncpus > 1);
141 }
142
143 void
144 cpu_mp_start(void)
145 {
146 struct cpuref bsp, cpu;
147 struct pcpu *pc;
148 int error;
149
150 error = platform_smp_get_bsp(&bsp);
151 KASSERT(error == 0, ("Don't know BSP"));
152 KASSERT(bsp.cr_cpuid == 0, ("%s: cpuid != 0", __func__));
153
154 error = platform_smp_first_cpu(&cpu);
155 while (!error) {
156 if (cpu.cr_cpuid >= MAXCPU) {
157 printf("SMP: cpu%d: skipped -- ID out of range\n",
158 cpu.cr_cpuid);
159 goto next;
160 }
161 if (CPU_ISSET(cpu.cr_cpuid, &all_cpus)) {
162 printf("SMP: cpu%d: skipped - duplicate ID\n",
163 cpu.cr_cpuid);
164 goto next;
165 }
166 if (cpu.cr_cpuid != bsp.cr_cpuid) {
167 void *dpcpu;
168
169 pc = &__pcpu[cpu.cr_cpuid];
170 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
171 M_WAITOK | M_ZERO);
172 pcpu_init(pc, cpu.cr_cpuid, sizeof(*pc));
173 dpcpu_init(dpcpu, cpu.cr_cpuid);
174 } else {
175 pc = pcpup;
176 pc->pc_cpuid = bsp.cr_cpuid;
177 pc->pc_bsp = 1;
178 }
179 pc->pc_hwref = cpu.cr_hwref;
180 CPU_SET(pc->pc_cpuid, &all_cpus);
181 next:
182 error = platform_smp_next_cpu(&cpu);
183 }
184 }
185
186 void
187 cpu_mp_announce(void)
188 {
189 struct pcpu *pc;
190 int i;
191
192 for (i = 0; i <= mp_maxid; i++) {
193 pc = pcpu_find(i);
194 if (pc == NULL)
195 continue;
196 printf("cpu%d: dev=%x", i, (int)pc->pc_hwref);
197 if (pc->pc_bsp)
198 printf(" (BSP)");
199 printf("\n");
200 }
201 }
202
203 static void
204 cpu_mp_unleash(void *dummy)
205 {
206 struct pcpu *pc;
207 int cpus, timeout;
208
209 if (mp_ncpus <= 1)
210 return;
211
212 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
213
214 cpus = 0;
215 smp_cpus = 0;
216 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
217 cpus++;
218 if (!pc->pc_bsp) {
219 if (bootverbose)
220 printf("Waking up CPU %d (dev=%x)\n",
221 pc->pc_cpuid, (int)pc->pc_hwref);
222
223 platform_smp_start_cpu(pc);
224
225 timeout = 2000; /* wait 2sec for the AP */
226 while (!pc->pc_awake && --timeout > 0)
227 DELAY(1000);
228
229 } else {
230 PCPU_SET(pir, mfspr(SPR_PIR));
231 pc->pc_awake = 1;
232 }
233 if (pc->pc_awake) {
234 if (bootverbose)
235 printf("Adding CPU %d, pir=%x, awake=%x\n",
236 pc->pc_cpuid, pc->pc_pir, pc->pc_awake);
237 smp_cpus++;
238 } else
239 CPU_SET(pc->pc_cpuid, &stopped_cpus);
240 }
241
242 ap_awake = 1;
243
244 /* Provide our current DEC and TB values for APs */
245 ap_timebase = mftb() + 10;
246 __asm __volatile("msync; isync");
247
248 /* Let APs continue */
249 atomic_store_rel_int(&ap_letgo, 1);
250
251 #ifdef __powerpc64__
252 /* Writing to the time base register is hypervisor-privileged */
253 if (mfmsr() & PSL_HV)
254 mttb(ap_timebase);
255 #else
256 mttb(ap_timebase);
257 #endif
258
259 while (ap_awake < smp_cpus)
260 ;
261
262 if (smp_cpus != cpus || cpus != mp_ncpus) {
263 printf("SMP: %d CPUs found; %d CPUs usable; %d CPUs woken\n",
264 mp_ncpus, cpus, smp_cpus);
265 }
266
267 /* Let the APs get into the scheduler */
268 DELAY(10000);
269
270 /* XXX Atomic set operation? */
271 smp_started = 1;
272 }
273
274 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, cpu_mp_unleash, NULL);
275
276 int
277 powerpc_ipi_handler(void *arg)
278 {
279 u_int cpuid;
280 uint32_t ipimask;
281 int msg;
282
283 CTR2(KTR_SMP, "%s: MSR 0x%08x", __func__, mfmsr());
284
285 ipimask = atomic_readandclear_32(&(pcpup->pc_ipimask));
286 if (ipimask == 0)
287 return (FILTER_STRAY);
288 while ((msg = ffs(ipimask) - 1) != -1) {
289 ipimask &= ~(1u << msg);
290 ipi_msg_cnt[msg]++;
291 switch (msg) {
292 case IPI_AST:
293 CTR1(KTR_SMP, "%s: IPI_AST", __func__);
294 break;
295 case IPI_PREEMPT:
296 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
297 sched_preempt(curthread);
298 break;
299 case IPI_RENDEZVOUS:
300 CTR1(KTR_SMP, "%s: IPI_RENDEZVOUS", __func__);
301 smp_rendezvous_action();
302 break;
303 case IPI_STOP:
304
305 /*
306 * IPI_STOP_HARD is mapped to IPI_STOP so it is not
307 * necessary to add such case in the switch.
308 */
309 CTR1(KTR_SMP, "%s: IPI_STOP or IPI_STOP_HARD (stop)",
310 __func__);
311 cpuid = PCPU_GET(cpuid);
312 savectx(&stoppcbs[cpuid]);
313 savectx(PCPU_GET(curpcb));
314 CPU_SET_ATOMIC(cpuid, &stopped_cpus);
315 while (!CPU_ISSET(cpuid, &started_cpus))
316 cpu_spinwait();
317 CPU_CLR_ATOMIC(cpuid, &stopped_cpus);
318 CPU_CLR_ATOMIC(cpuid, &started_cpus);
319 CTR1(KTR_SMP, "%s: IPI_STOP (restart)", __func__);
320 break;
321 case IPI_HARDCLOCK:
322 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
323 hardclockintr();
324 break;
325 }
326 }
327
328 return (FILTER_HANDLED);
329 }
330
331 static void
332 ipi_send(struct pcpu *pc, int ipi)
333 {
334
335 CTR4(KTR_SMP, "%s: pc=%p, targetcpu=%d, IPI=%d", __func__,
336 pc, pc->pc_cpuid, ipi);
337
338 atomic_set_32(&pc->pc_ipimask, (1 << ipi));
339 powerpc_sync();
340 PIC_IPI(root_pic, pc->pc_cpuid);
341
342 CTR1(KTR_SMP, "%s: sent", __func__);
343 }
344
345 /* Send an IPI to a set of cpus. */
346 void
347 ipi_selected(cpuset_t cpus, int ipi)
348 {
349 struct pcpu *pc;
350
351 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
352 if (CPU_ISSET(pc->pc_cpuid, &cpus))
353 ipi_send(pc, ipi);
354 }
355 }
356
357 /* Send an IPI to a specific CPU. */
358 void
359 ipi_cpu(int cpu, u_int ipi)
360 {
361
362 ipi_send(cpuid_to_pcpu[cpu], ipi);
363 }
364
365 /* Send an IPI to all CPUs EXCEPT myself. */
366 void
367 ipi_all_but_self(int ipi)
368 {
369 struct pcpu *pc;
370
371 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
372 if (pc != pcpup)
373 ipi_send(pc, ipi);
374 }
375 }
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