openpic.c

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
    1 /*-
    2  * Copyright (C) 2002 Benno Rice.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
   15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   17  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   18  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
   19  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
   20  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   21  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
   22  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
   23  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   24  *
   25  * $FreeBSD: releng/9.1/sys/powerpc/powerpc/openpic.c 222813 2011-06-07 08:46:13Z attilio $
   26  */
   27 
   28 #include <sys/param.h>
   29 #include <sys/systm.h>
   30 #include <sys/bus.h>
   31 #include <sys/conf.h>
   32 #include <sys/kernel.h>
   33 #include <sys/proc.h>
   34 #include <sys/rman.h>
   35 #include <sys/sched.h>
   36 
   37 #include <machine/bus.h>
   38 #include <machine/intr_machdep.h>
   39 #include <machine/md_var.h>
   40 #include <machine/pio.h>
   41 #include <machine/resource.h>
   42 
   43 #include <vm/vm.h>
   44 #include <vm/pmap.h>
   45 
   46 #include <machine/openpicreg.h>
   47 #include <machine/openpicvar.h>
   48 
   49 #include "pic_if.h"
   50 
   51 devclass_t openpic_devclass;
   52 
   53 /*
   54  * Local routines
   55  */
   56 static int openpic_intr(void *arg);
   57 
   58 static __inline uint32_t
   59 openpic_read(struct openpic_softc *sc, u_int reg)
   60 {
   61         return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
   62 }
   63 
   64 static __inline void
   65 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
   66 {
   67         bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
   68 }
   69 
   70 static __inline void
   71 openpic_set_priority(struct openpic_softc *sc, int pri)
   72 {
   73         u_int tpr;
   74         uint32_t x;
   75 
   76         sched_pin();
   77         tpr = OPENPIC_PCPU_TPR((sc->sc_dev == root_pic) ? PCPU_GET(cpuid) : 0);
   78         x = openpic_read(sc, tpr);
   79         x &= ~OPENPIC_TPR_MASK;
   80         x |= pri;
   81         openpic_write(sc, tpr, x);
   82         sched_unpin();
   83 }
   84 
   85 int
   86 openpic_common_attach(device_t dev, uint32_t node)
   87 {
   88         struct openpic_softc *sc;
   89         u_int     cpu, ipi, irq;
   90         u_int32_t x;
   91 
   92         sc = device_get_softc(dev);
   93         sc->sc_dev = dev;
   94 
   95         sc->sc_rid = 0;
   96         sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
   97             RF_ACTIVE);
   98 
   99         if (sc->sc_memr == NULL) {
  100                 device_printf(dev, "Could not alloc mem resource!\n");
  101                 return (ENXIO);
  102         }
  103 
  104         sc->sc_bt = rman_get_bustag(sc->sc_memr);
  105         sc->sc_bh = rman_get_bushandle(sc->sc_memr);
  106 
  107         /* Reset the PIC */
  108         x = openpic_read(sc, OPENPIC_CONFIG);
  109         x |= OPENPIC_CONFIG_RESET;
  110         openpic_write(sc, OPENPIC_CONFIG, x);
  111 
  112         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
  113                 powerpc_sync();
  114                 DELAY(100);
  115         }
  116 
  117         /* Check if this is a cascaded PIC */
  118         sc->sc_irq = 0;
  119         sc->sc_intr = NULL;
  120         do {
  121                 struct resource_list *rl;
  122 
  123                 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
  124                 if (rl == NULL)
  125                         break;
  126                 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
  127                         break;
  128 
  129                 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  130                     &sc->sc_irq, RF_ACTIVE);
  131 
  132                 /* XXX Cascaded PICs pass NULL trapframes! */
  133                 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
  134                     openpic_intr, NULL, dev, &sc->sc_icookie);
  135         } while (0);
  136 
  137         /* Reset the PIC */
  138         x = openpic_read(sc, OPENPIC_CONFIG);
  139         x |= OPENPIC_CONFIG_RESET;
  140         openpic_write(sc, OPENPIC_CONFIG, x);
  141 
  142         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
  143                 powerpc_sync();
  144                 DELAY(100);
  145         }
  146 
  147         x = openpic_read(sc, OPENPIC_FEATURE);
  148         switch (x & OPENPIC_FEATURE_VERSION_MASK) {
  149         case 1:
  150                 sc->sc_version = "1.0";
  151                 break;
  152         case 2:
  153                 sc->sc_version = "1.2";
  154                 break;
  155         case 3:
  156                 sc->sc_version = "1.3";
  157                 break;
  158         default:
  159                 sc->sc_version = "unknown";
  160                 break;
  161         }
  162 
  163         sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
  164             OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
  165         sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
  166             OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
  167 
  168         /*
  169          * PSIM seems to report 1 too many IRQs and CPUs
  170          */
  171         if (sc->sc_psim) {
  172                 sc->sc_nirq--;
  173                 sc->sc_ncpu--;
  174         }
  175 
  176         if (bootverbose)
  177                 device_printf(dev,
  178                     "Version %s, supports %d CPUs and %d irqs\n",
  179                     sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
  180 
  181         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
  182                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
  183 
  184         /* Reset and disable all interrupts. */
  185         for (irq = 0; irq < sc->sc_nirq; irq++) {
  186                 x = irq;                /* irq == vector. */
  187                 x |= OPENPIC_IMASK;
  188                 x |= OPENPIC_POLARITY_NEGATIVE;
  189                 x |= OPENPIC_SENSE_LEVEL;
  190                 x |= 8 << OPENPIC_PRIORITY_SHIFT;
  191                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  192         }
  193 
  194         /* Reset and disable all IPIs. */
  195         for (ipi = 0; ipi < 4; ipi++) {
  196                 x = sc->sc_nirq + ipi;
  197                 x |= OPENPIC_IMASK;
  198                 x |= 15 << OPENPIC_PRIORITY_SHIFT;
  199                 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
  200         }
  201 
  202         /* we don't need 8259 passthrough mode */
  203         x = openpic_read(sc, OPENPIC_CONFIG);
  204         x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
  205         openpic_write(sc, OPENPIC_CONFIG, x);
  206 
  207         /* send all interrupts to cpu 0 */
  208         for (irq = 0; irq < sc->sc_nirq; irq++)
  209                 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
  210 
  211         /* clear all pending interrupts from cpu 0 */
  212         for (irq = 0; irq < sc->sc_nirq; irq++) {
  213                 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
  214                 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
  215         }
  216 
  217         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
  218                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
  219 
  220         powerpc_register_pic(dev, node, sc->sc_nirq, 4, FALSE);
  221 
  222         /* If this is not a cascaded PIC, it must be the root PIC */
  223         if (sc->sc_intr == NULL)
  224                 root_pic = dev;
  225 
  226         return (0);
  227 }
  228 
  229 /*
  230  * PIC I/F methods
  231  */
  232 
  233 void
  234 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask)
  235 {
  236         struct openpic_softc *sc;
  237 
  238         /* If we aren't directly connected to the CPU, this won't work */
  239         if (dev != root_pic)
  240                 return;
  241 
  242         sc = device_get_softc(dev);
  243 
  244         /*
  245          * XXX: openpic_write() is very special and just needs a 32 bits mask.
  246          * For the moment, just play dirty and get the first half word.
  247          */
  248         openpic_write(sc, OPENPIC_IDEST(irq), cpumask.__bits[0] & 0xffffffff);
  249 }
  250 
  251 void
  252 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
  253     enum intr_polarity pol)
  254 {
  255         struct openpic_softc *sc;
  256         uint32_t x;
  257 
  258         sc = device_get_softc(dev);
  259         x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
  260         if (pol == INTR_POLARITY_LOW)
  261                 x &= ~OPENPIC_POLARITY_POSITIVE;
  262         else
  263                 x |= OPENPIC_POLARITY_POSITIVE;
  264         if (trig == INTR_TRIGGER_EDGE)
  265                 x &= ~OPENPIC_SENSE_LEVEL;
  266         else
  267                 x |= OPENPIC_SENSE_LEVEL;
  268         openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  269 }
  270 
  271 static int
  272 openpic_intr(void *arg)
  273 {
  274         device_t dev = (device_t)(arg);
  275 
  276         /* XXX Cascaded PICs do not pass non-NULL trapframes! */
  277         openpic_dispatch(dev, NULL);
  278 
  279         return (FILTER_HANDLED);
  280 }
  281 
  282 void
  283 openpic_dispatch(device_t dev, struct trapframe *tf)
  284 {
  285         struct openpic_softc *sc;
  286         u_int cpuid, vector;
  287 
  288         CTR1(KTR_INTR, "%s: got interrupt", __func__);
  289 
  290         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
  291 
  292         sc = device_get_softc(dev);
  293         while (1) {
  294                 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
  295                 vector &= OPENPIC_VECTOR_MASK;
  296                 if (vector == 255)
  297                         break;
  298                 powerpc_dispatch_intr(vector, tf);
  299         }
  300 }
  301 
  302 void
  303 openpic_enable(device_t dev, u_int irq, u_int vector)
  304 {
  305         struct openpic_softc *sc;
  306         uint32_t x;
  307 
  308         sc = device_get_softc(dev);
  309         if (irq < sc->sc_nirq) {
  310                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
  311                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
  312                 x |= vector;
  313                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  314         } else {
  315                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
  316                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
  317                 x |= vector;
  318                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
  319         }
  320 }
  321 
  322 void
  323 openpic_eoi(device_t dev, u_int irq __unused)
  324 {
  325         struct openpic_softc *sc;
  326         u_int cpuid;
  327 
  328         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
  329 
  330         sc = device_get_softc(dev);
  331         openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
  332 }
  333 
  334 void
  335 openpic_ipi(device_t dev, u_int cpu)
  336 {
  337         struct openpic_softc *sc;
  338 
  339         KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
  340 
  341         sc = device_get_softc(dev);
  342         sched_pin();
  343         openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
  344             1u << cpu);
  345         sched_unpin();
  346 }
  347 
  348 void
  349 openpic_mask(device_t dev, u_int irq)
  350 {
  351         struct openpic_softc *sc;
  352         uint32_t x;
  353 
  354         sc = device_get_softc(dev);
  355         if (irq < sc->sc_nirq) {
  356                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
  357                 x |= OPENPIC_IMASK;
  358                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  359         } else {
  360                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
  361                 x |= OPENPIC_IMASK;
  362                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
  363         }
  364 }
  365 
  366 void
  367 openpic_unmask(device_t dev, u_int irq)
  368 {
  369         struct openpic_softc *sc;
  370         uint32_t x;
  371 
  372         sc = device_get_softc(dev);
  373         if (irq < sc->sc_nirq) {
  374                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
  375                 x &= ~OPENPIC_IMASK;
  376                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  377         } else {
  378                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
  379                 x &= ~OPENPIC_IMASK;
  380                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
  381         }
  382 }
Cache object: c403a70a24f4f36958d6973f11845dcc
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.
FreeBSD/Linux Kernel Cross Reference sys/powerpc/powerpc/openpic.c

FreeBSD/Linux Kernel Cross Reference
sys/powerpc/powerpc/openpic.c
