openpic.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (C) 2002 Benno Rice.
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
   17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   19  * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   20  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
   21  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
   22  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   23  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
   24  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
   25  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   26  *
   27  * $FreeBSD$
   28  */
   29 
   30 #include <sys/param.h>
   31 #include <sys/systm.h>
   32 #include <sys/bus.h>
   33 #include <sys/conf.h>
   34 #include <sys/kernel.h>
   35 #include <sys/ktr.h>
   36 #include <sys/proc.h>
   37 #include <sys/rman.h>
   38 #include <sys/sched.h>
   39 #include <sys/smp.h>
   40 
   41 #include <machine/bus.h>
   42 #include <machine/intr_machdep.h>
   43 #include <machine/md_var.h>
   44 #include <machine/pio.h>
   45 #include <machine/resource.h>
   46 
   47 #include <vm/vm.h>
   48 #include <vm/pmap.h>
   49 
   50 #include <machine/openpicreg.h>
   51 #include <machine/openpicvar.h>
   52 
   53 #include "pic_if.h"
   54 
   55 #define OPENPIC_NIPIS           4
   56 
   57 devclass_t openpic_devclass;
   58 
   59 /*
   60  * Local routines
   61  */
   62 static int openpic_intr(void *arg);
   63 
   64 static __inline uint32_t
   65 openpic_read(struct openpic_softc *sc, u_int reg)
   66 {
   67         return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg));
   68 }
   69 
   70 static __inline void
   71 openpic_write(struct openpic_softc *sc, u_int reg, uint32_t val)
   72 {
   73         bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val);
   74 }
   75 
   76 int
   77 openpic_common_attach(device_t dev, uint32_t node)
   78 {
   79         struct openpic_softc *sc;
   80         u_int     cpu, ipi, irq;
   81         u_int32_t x;
   82 
   83         sc = device_get_softc(dev);
   84         sc->sc_dev = dev;
   85 
   86         sc->sc_rid = 0;
   87         sc->sc_memr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
   88             RF_ACTIVE);
   89 
   90         if (sc->sc_memr == NULL) {
   91                 device_printf(dev, "Could not alloc mem resource!\n");
   92                 return (ENXIO);
   93         }
   94 
   95         sc->sc_bt = rman_get_bustag(sc->sc_memr);
   96         sc->sc_bh = rman_get_bushandle(sc->sc_memr);
   97 
   98         /* Reset the PIC */
   99         x = openpic_read(sc, OPENPIC_CONFIG);
  100         x |= OPENPIC_CONFIG_RESET;
  101         openpic_write(sc, OPENPIC_CONFIG, x);
  102 
  103         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
  104                 powerpc_sync();
  105                 DELAY(100);
  106         }
  107 
  108         /* Check if this is a cascaded PIC */
  109         sc->sc_irq = 0;
  110         sc->sc_intr = NULL;
  111         do {
  112                 struct resource_list *rl;
  113 
  114                 rl = BUS_GET_RESOURCE_LIST(device_get_parent(dev), dev);
  115                 if (rl == NULL)
  116                         break;
  117                 if (resource_list_find(rl, SYS_RES_IRQ, 0) == NULL)
  118                         break;
  119 
  120                 sc->sc_intr = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  121                     &sc->sc_irq, RF_ACTIVE);
  122 
  123                 /* XXX Cascaded PICs pass NULL trapframes! */
  124                 bus_setup_intr(dev, sc->sc_intr, INTR_TYPE_MISC | INTR_MPSAFE,
  125                     openpic_intr, NULL, dev, &sc->sc_icookie);
  126         } while (0);
  127 
  128         /* Reset the PIC */
  129         x = openpic_read(sc, OPENPIC_CONFIG);
  130         x |= OPENPIC_CONFIG_RESET;
  131         openpic_write(sc, OPENPIC_CONFIG, x);
  132 
  133         while (openpic_read(sc, OPENPIC_CONFIG) & OPENPIC_CONFIG_RESET) {
  134                 powerpc_sync();
  135                 DELAY(100);
  136         }
  137 
  138         x = openpic_read(sc, OPENPIC_FEATURE);
  139         switch (x & OPENPIC_FEATURE_VERSION_MASK) {
  140         case 1:
  141                 sc->sc_version = "1.0";
  142                 break;
  143         case 2:
  144                 sc->sc_version = "1.2";
  145                 break;
  146         case 3:
  147                 sc->sc_version = "1.3";
  148                 break;
  149         default:
  150                 sc->sc_version = "unknown";
  151                 break;
  152         }
  153 
  154         sc->sc_ncpu = ((x & OPENPIC_FEATURE_LAST_CPU_MASK) >>
  155             OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
  156         sc->sc_nirq = ((x & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
  157             OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
  158 
  159         /*
  160          * PSIM seems to report 1 too many IRQs and CPUs
  161          */
  162         if (sc->sc_psim) {
  163                 sc->sc_nirq--;
  164                 sc->sc_ncpu--;
  165         }
  166 
  167         if (bootverbose)
  168                 device_printf(dev,
  169                     "Version %s, supports %d CPUs and %d irqs\n",
  170                     sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
  171 
  172         /*
  173          * Allow more IRQs than what the PIC says it handles.  Some Freescale PICs
  174          * have MSIs that show up above the PIC's self-described 196 IRQs
  175          * (P5020 starts MSI IRQs at 224).
  176          */
  177         if (sc->sc_quirks & OPENPIC_QUIRK_HIDDEN_IRQS)
  178                 sc->sc_nirq = OPENPIC_IRQMAX - OPENPIC_NIPIS;
  179 
  180         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
  181                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
  182 
  183         /* Reset and disable all interrupts. */
  184         for (irq = 0; irq < sc->sc_nirq; irq++) {
  185                 x = irq;                /* irq == vector. */
  186                 x |= OPENPIC_IMASK;
  187                 x |= OPENPIC_POLARITY_NEGATIVE;
  188                 x |= OPENPIC_SENSE_LEVEL;
  189                 x |= 8 << OPENPIC_PRIORITY_SHIFT;
  190                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  191         }
  192 
  193         /* Reset and disable all IPIs. */
  194         for (ipi = 0; ipi < OPENPIC_NIPIS; ipi++) {
  195                 x = sc->sc_nirq + ipi;
  196                 x |= OPENPIC_IMASK;
  197                 x |= 15 << OPENPIC_PRIORITY_SHIFT;
  198                 openpic_write(sc, OPENPIC_IPI_VECTOR(ipi), x);
  199         }
  200 
  201         /* we don't need 8259 passthrough mode */
  202         x = openpic_read(sc, OPENPIC_CONFIG);
  203         x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
  204         openpic_write(sc, OPENPIC_CONFIG, x);
  205 
  206         /* send all interrupts to cpu 0 */
  207         for (irq = 0; irq < sc->sc_nirq; irq++)
  208                 openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
  209 
  210         /* clear all pending interrupts from cpu 0 */
  211         for (irq = 0; irq < sc->sc_nirq; irq++) {
  212                 (void)openpic_read(sc, OPENPIC_PCPU_IACK(0));
  213                 openpic_write(sc, OPENPIC_PCPU_EOI(0), 0);
  214         }
  215 
  216         for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
  217                 openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
  218 
  219         powerpc_register_pic(dev, node, sc->sc_nirq, OPENPIC_NIPIS, FALSE);
  220 
  221         /* If this is not a cascaded PIC, it must be the root PIC */
  222         if (sc->sc_intr == NULL)
  223                 root_pic = dev;
  224 
  225         return (0);
  226 }
  227 
  228 /*
  229  * PIC I/F methods
  230  */
  231 
  232 void
  233 openpic_bind(device_t dev, u_int irq, cpuset_t cpumask, void **priv __unused)
  234 {
  235         struct openpic_softc *sc;
  236         uint32_t mask;
  237 
  238         /* If we aren't directly connected to the CPU, this won't work */
  239         if (dev != root_pic)
  240                 return;
  241 
  242         sc = device_get_softc(dev);
  243 
  244         /*
  245          * XXX: openpic_write() is very special and just needs a 32 bits mask.
  246          * For the moment, just play dirty and get the first half word.
  247          */
  248         mask = cpumask.__bits[0] & 0xffffffff;
  249         if (sc->sc_quirks & OPENPIC_QUIRK_SINGLE_BIND) {
  250                 int i = mftb() % CPU_COUNT(&cpumask);
  251                 int cpu, ncpu;
  252 
  253                 ncpu = 0;
  254                 CPU_FOREACH(cpu) {
  255                         if (!(mask & (1 << cpu)))
  256                                 continue;
  257                         if (ncpu == i)
  258                                 break;
  259                         ncpu++;
  260                 }
  261                 mask &= (1 << cpu);
  262         }
  263 
  264         openpic_write(sc, OPENPIC_IDEST(irq), mask);
  265 }
  266 
  267 void
  268 openpic_config(device_t dev, u_int irq, enum intr_trigger trig,
  269     enum intr_polarity pol)
  270 {
  271         struct openpic_softc *sc;
  272         uint32_t x;
  273 
  274         sc = device_get_softc(dev);
  275         x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
  276         if (pol == INTR_POLARITY_LOW)
  277                 x &= ~OPENPIC_POLARITY_POSITIVE;
  278         else
  279                 x |= OPENPIC_POLARITY_POSITIVE;
  280         if (trig == INTR_TRIGGER_EDGE)
  281                 x &= ~OPENPIC_SENSE_LEVEL;
  282         else
  283                 x |= OPENPIC_SENSE_LEVEL;
  284         openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  285 }
  286 
  287 static int
  288 openpic_intr(void *arg)
  289 {
  290         device_t dev = (device_t)(arg);
  291 
  292         /* XXX Cascaded PICs do not pass non-NULL trapframes! */
  293         openpic_dispatch(dev, NULL);
  294 
  295         return (FILTER_HANDLED);
  296 }
  297 
  298 void
  299 openpic_dispatch(device_t dev, struct trapframe *tf)
  300 {
  301         struct openpic_softc *sc;
  302         u_int cpuid, vector;
  303 
  304         CTR1(KTR_INTR, "%s: got interrupt", __func__);
  305 
  306         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
  307 
  308         sc = device_get_softc(dev);
  309         while (1) {
  310                 vector = openpic_read(sc, OPENPIC_PCPU_IACK(cpuid));
  311                 vector &= OPENPIC_VECTOR_MASK;
  312                 if (vector == 255)
  313                         break;
  314                 powerpc_dispatch_intr(vector, tf);
  315         }
  316 }
  317 
  318 void
  319 openpic_enable(device_t dev, u_int irq, u_int vector, void **priv __unused)
  320 {
  321         struct openpic_softc *sc;
  322         uint32_t x;
  323 
  324         sc = device_get_softc(dev);
  325         if (irq < sc->sc_nirq) {
  326                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
  327                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
  328                 x |= vector;
  329                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  330         } else {
  331                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
  332                 x &= ~(OPENPIC_IMASK | OPENPIC_VECTOR_MASK);
  333                 x |= vector;
  334                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
  335         }
  336 }
  337 
  338 void
  339 openpic_eoi(device_t dev, u_int irq __unused, void *priv __unused)
  340 {
  341         struct openpic_softc *sc;
  342         u_int cpuid;
  343 
  344         cpuid = (dev == root_pic) ? PCPU_GET(cpuid) : 0;
  345 
  346         sc = device_get_softc(dev);
  347         openpic_write(sc, OPENPIC_PCPU_EOI(cpuid), 0);
  348 }
  349 
  350 void
  351 openpic_ipi(device_t dev, u_int cpu)
  352 {
  353         struct openpic_softc *sc;
  354 
  355         KASSERT(dev == root_pic, ("Cannot send IPIs from non-root OpenPIC"));
  356 
  357         sc = device_get_softc(dev);
  358         sched_pin();
  359         openpic_write(sc, OPENPIC_PCPU_IPI_DISPATCH(PCPU_GET(cpuid), 0),
  360             1u << cpu);
  361         sched_unpin();
  362 }
  363 
  364 void
  365 openpic_mask(device_t dev, u_int irq, void *priv __unused)
  366 {
  367         struct openpic_softc *sc;
  368         uint32_t x;
  369 
  370         sc = device_get_softc(dev);
  371         if (irq < sc->sc_nirq) {
  372                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
  373                 x |= OPENPIC_IMASK;
  374                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  375         } else {
  376                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
  377                 x |= OPENPIC_IMASK;
  378                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
  379         }
  380 }
  381 
  382 void
  383 openpic_unmask(device_t dev, u_int irq, void *priv __unused)
  384 {
  385         struct openpic_softc *sc;
  386         uint32_t x;
  387 
  388         sc = device_get_softc(dev);
  389         if (irq < sc->sc_nirq) {
  390                 x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
  391                 x &= ~OPENPIC_IMASK;
  392                 openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
  393         } else {
  394                 x = openpic_read(sc, OPENPIC_IPI_VECTOR(0));
  395                 x &= ~OPENPIC_IMASK;
  396                 openpic_write(sc, OPENPIC_IPI_VECTOR(0), x);
  397         }
  398 }
  399 
  400 int
  401 openpic_suspend(device_t dev)
  402 {
  403         struct openpic_softc *sc;
  404         int i;
  405 
  406         sc = device_get_softc(dev);
  407 
  408         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
  409         for (i = 0; i < OPENPIC_NIPIS; i++) {
  410                 sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
  411         }
  412 
  413         for (i = 0; i < 4; i++) {
  414                 sc->sc_saved_prios[i] = bus_read_4(sc->sc_memr, OPENPIC_PCPU_TPR(i));
  415         }
  416 
  417         for (i = 0; i < OPENPIC_TIMERS; i++) {
  418                 sc->sc_saved_timers[i].tcnt = bus_read_4(sc->sc_memr, OPENPIC_TCNT(i));
  419                 sc->sc_saved_timers[i].tbase = bus_read_4(sc->sc_memr, OPENPIC_TBASE(i));
  420                 sc->sc_saved_timers[i].tvec = bus_read_4(sc->sc_memr, OPENPIC_TVEC(i));
  421                 sc->sc_saved_timers[i].tdst = bus_read_4(sc->sc_memr, OPENPIC_TDST(i));
  422         }
  423 
  424         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
  425                 sc->sc_saved_vectors[i] =
  426                     bus_read_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i)) & ~OPENPIC_ACTIVITY;
  427 
  428         return (0);
  429 }
  430 
  431 int
  432 openpic_resume(device_t dev)
  433 {
  434         struct openpic_softc *sc;
  435         int i;
  436 
  437         sc = device_get_softc(dev);
  438 
  439         sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
  440         for (i = 0; i < OPENPIC_NIPIS; i++) {
  441                 bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
  442         }
  443 
  444         for (i = 0; i < 4; i++) {
  445                 bus_write_4(sc->sc_memr, OPENPIC_PCPU_TPR(i), sc->sc_saved_prios[i]);
  446         }
  447 
  448         for (i = 0; i < OPENPIC_TIMERS; i++) {
  449                 bus_write_4(sc->sc_memr, OPENPIC_TCNT(i), sc->sc_saved_timers[i].tcnt);
  450                 bus_write_4(sc->sc_memr, OPENPIC_TBASE(i), sc->sc_saved_timers[i].tbase);
  451                 bus_write_4(sc->sc_memr, OPENPIC_TVEC(i), sc->sc_saved_timers[i].tvec);
  452                 bus_write_4(sc->sc_memr, OPENPIC_TDST(i), sc->sc_saved_timers[i].tdst);
  453         }
  454 
  455         for (i = 0; i < OPENPIC_SRC_VECTOR_COUNT; i++)
  456                 bus_write_4(sc->sc_memr, OPENPIC_SRC_VECTOR(i), sc->sc_saved_vectors[i]);
  457 
  458         return (0);
  459 }
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FreeBSD/Linux Kernel Cross Reference sys/powerpc/powerpc/openpic.c

FreeBSD/Linux Kernel Cross Reference
sys/powerpc/powerpc/openpic.c
