FreeBSD/Linux Kernel Cross Reference
sys/ppc/blast.h
1 /*
2 * Here, we define everything that is specific for the blast board from Crawford Hill
3 */
4
5
6 /* Clock speed of the blast board */
7 #define CLKIN 72000000
8
9 /*
10 * Blast memory layout:
11 * CS0: FE000000 -> FFFFFFFF (Flash)
12 * CS1: FC000000 -> FCFFFFFF (DSP hpi)
13 * CS2: 00000000 -> 03FFFFFF (60x sdram)
14 * CS3: 04000000 -> 04FFFFFF (FPGA)
15 * CS4: 05000000 -> 06FFFFFF (local bus sdram)
16 * CS5: 07000000 -> 070FFFFF (eeprom - not populated)
17 * CS6: E0000000 -> E0FFFFFF (FPGA)
18 *
19 * Main Board memory lay out:
20 * CS0: FE000000 -> FEFFFFFF (16 M FLASH)
21 * CS1: FC000000 -> FCFFFFFF (16 M DSP1)
22 * CS2: 00000000 -> 03FFFFFF (64 M SDRAM)
23 * CS3: 04000000 -> 04FFFFFF (16M DSP2)
24 * CS4: 05000000 -> 06FFFFFF (32 M Local SDRAM)
25 * CS5: 07000000 -> 070FFFFF (eeprom - not populated)
26 * CS6: E0000000 -> E0FFFFFF (16 M FPGA)
27 *
28 * CS2, CS3, CS4, (and CS5) are covered by DBAT 0, CS0 and CS1 by DBAT 3, CS6 by DBAT 2
29 */
30 #define FLASHMEM 0xfe000000
31 #define FLASHSIZE 0x01000000
32 #define DSP1BASE 0xfc000000
33 #define DSP1SIZE 0x01000000
34 #define MEM1BASE 0x00000000
35 #define MEM1SIZE 0x04000000
36 #define DSP2BASE 0x04000000
37 #define DSP2SIZE 0x01000000
38 #define MEM2BASE 0x05000000
39 /* #define MEM2SIZE 0x02000000 */
40 #define MEM2SIZE 0
41 #define FPGABASE 0xe0000000
42 #define FPGASIZE 0x01000000
43
44 #define PLAN9INI 0x00460000
45
46 #define TLBENTRIES 32
47 /*
48 * PTE bits for fault.c. These belong to the second PTE word. Validity is
49 * implied for putmmu(), and we always set PTE0_V. PTEVALID is used
50 * here to set cache policy bits on a global basis.
51 */
52 #define PTEVALID PTE1_M
53 #define PTEWRITE (PTE1_RW|PTE1_C)
54 #define PTERONLY PTE1_RO
55 #define PTEUNCACHED PTE1_I
56
57 /* SMC Uart configuration */
58 #define SMC1PORT 3 /* Port D */
59 #define SMTXD1 BIT(9)
60 #define SMRXD1 BIT(8)
61
62 /* Ethernet FCC configuration */
63 #define A1txer 0x00000004
64 #define A1rxdv 0x00000010
65 #define A1txen 0x00000008
66 #define A1rxer 0x00000020
67 #define A1col 0x00000001
68 #define A1crs 0x00000002
69 #define A1txdat 0x00003c00
70 #define A1rxdat 0x0003c000
71 #define B2txer 0x00000001
72 #define B2rxdv 0x00000002
73 #define B2txen 0x00000004
74 #define B2rxer 0x00000008
75 #define B2col 0x00000010
76 #define B2crs 0x00000020
77 #define B2txdat 0x000003c0
78 #define B2rxdat 0x00003c00
79 #define B3rxdv 0x00004000
80 #define B3rxer 0x00008000
81 #define B3txer 0x00010000
82 #define B3txen 0x00020000
83 #define B3col 0x00040000
84 #define B3crs 0x00080000
85 #define B3txdat 0x0f000000
86 #define B3rxdat 0x00f00000
87
88 #define A1psor0 (A1rxdat | A1txdat)
89 #define A1psor1 (A1col | A1crs | A1txer | A1txen | A1rxdv | A1rxer)
90 #define A1dir0 (A1rxdat | A1crs | A1col | A1rxer | A1rxdv)
91 #define A1dir1 (A1txdat | A1txen | A1txer)
92 #define B2psor0 (B2rxdat | B2txdat | B2crs | B2col | B2rxer | B2rxdv | B2txer)
93 #define B2psor1 (B2txen)
94 #define B2dir0 (B2rxdat | B2crs | B2col | B2rxer | B2rxdv)
95 #define B2dir1 (B2txdat | B2txen | B2txer)
96 #define B3psor0 (B3rxdat | B3txdat | B3crs | B3col | B3rxer | B3rxdv | B3txer | B3txen)
97 #define B3psor1 0
98 #define B3dir0 (B3rxdat | B3crs | B3col | B3rxer | B3rxdv)
99 #define B3dir1 (B3txdat | B3txen | B3txer)
Cache object: 4c654edb26dc75332ff745b1904ed730
|