The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/riscv/include/riscv_opcode.h

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    1 /*-
    2  * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * Portions of this software were developed by SRI International and the
    6  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
    7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
    8  *
    9  * Portions of this software were developed by the University of Cambridge
   10  * Computer Laboratory as part of the CTSRD Project, with support from the
   11  * UK Higher Education Innovation Fund (HEIF).
   12  *
   13  * Redistribution and use in source and binary forms, with or without
   14  * modification, are permitted provided that the following conditions
   15  * are met:
   16  * 1. Redistributions of source code must retain the above copyright
   17  *    notice, this list of conditions and the following disclaimer.
   18  * 2. Redistributions in binary form must reproduce the above copyright
   19  *    notice, this list of conditions and the following disclaimer in the
   20  *    documentation and/or other materials provided with the distribution.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  *
   34  * $FreeBSD$
   35  */
   36 
   37 #ifndef _MACHINE_RISCV_OPCODE_H_
   38 #define _MACHINE_RISCV_OPCODE_H_
   39 
   40 /*
   41  * Define the instruction formats and opcode values for the
   42  * RISC-V instruction set.
   43  */
   44 #include <machine/endian.h>
   45 
   46 /*
   47  * Define the instruction formats.
   48  */
   49 typedef union {
   50         unsigned word;
   51 
   52         struct {
   53                 unsigned opcode: 7;
   54                 unsigned rd: 5;
   55                 unsigned funct3: 3;
   56                 unsigned rs1: 5;
   57                 unsigned rs2: 5;
   58                 unsigned funct7: 7;
   59         } RType;
   60 
   61         struct {
   62                 unsigned opcode: 7;
   63                 unsigned rd: 5;
   64                 unsigned funct3: 3;
   65                 unsigned rs1: 5;
   66                 unsigned rs2: 6;
   67                 unsigned funct7: 6;
   68         } R2Type;
   69 
   70         struct {
   71                 unsigned opcode: 7;
   72                 unsigned rd: 5;
   73                 unsigned funct3: 3;
   74                 unsigned rs1: 5;
   75                 unsigned imm: 12;
   76         } IType;
   77 
   78         struct {
   79                 unsigned opcode: 7;
   80                 unsigned imm0_4: 5;
   81                 unsigned funct3: 3;
   82                 unsigned rs1: 5;
   83                 unsigned rs2: 5;
   84                 unsigned imm5_11: 7;
   85         } SType;
   86 
   87         struct {
   88                 unsigned opcode: 7;
   89                 unsigned imm11: 1;
   90                 unsigned imm1_4: 4;
   91                 unsigned funct3: 3;
   92                 unsigned rs1: 5;
   93                 unsigned rs2: 5;
   94                 unsigned imm5_10: 6;
   95                 unsigned imm12: 1;
   96         } SBType;
   97 
   98         struct {
   99                 unsigned opcode: 7;
  100                 unsigned rd: 5;
  101                 unsigned imm12_31: 20;
  102         } UType;
  103 
  104         struct {
  105                 unsigned opcode: 7;
  106                 unsigned rd: 5;
  107                 unsigned imm12_19: 8;
  108                 unsigned imm11: 1;
  109                 unsigned imm1_10: 10;
  110                 unsigned imm20: 1;
  111         } UJType;
  112 } InstFmt;
  113 
  114 #define RISCV_OPCODE(r)         (r & 0x7f)
  115 
  116 #endif /* !_MACHINE_RISCV_OPCODE_H_ */

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