1 /*-
2 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35 #include <machine/asm.h>
36
37 __FBSDID("$FreeBSD: releng/12.0/sys/riscv/riscv/bus_space_asm.S 298635 2016-04-26 12:45:01Z br $");
38
39 ENTRY(generic_bs_r_1)
40 add a3, a1, a2
41 lb a0, 0(a3)
42 ret
43 END(generic_bs_r_1)
44
45 ENTRY(generic_bs_r_2)
46 add a3, a1, a2
47 lh a0, 0(a3)
48 ret
49 END(generic_bs_r_2)
50
51 ENTRY(generic_bs_r_4)
52 add a3, a1, a2
53 lw a0, 0(a3)
54 ret
55 END(generic_bs_r_4)
56
57 ENTRY(generic_bs_r_8)
58 add a3, a1, a2
59 ld a0, 0(a3)
60 ret
61 END(generic_bs_r_8)
62
63 ENTRY(generic_bs_w_1)
64 add a4, a1, a2
65 sb a3, 0(a4)
66 ret
67 END(generic_bs_w_1)
68
69 ENTRY(generic_bs_w_2)
70 add a4, a1, a2
71 sh a3, 0(a4)
72 ret
73 END(generic_bs_w_2)
74
75 ENTRY(generic_bs_w_4)
76 add a4, a1, a2
77 sw a3, 0(a4)
78 ret
79 END(generic_bs_w_4)
80
81 ENTRY(generic_bs_w_8)
82 add a4, a1, a2
83 sd a3, 0(a4)
84 ret
85 END(generic_bs_w_8)
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