The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/riscv/riscv/cpufunc_asm.S

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    1 /*-
    2  * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * Portions of this software were developed by SRI International and the
    6  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
    7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
    8  *
    9  * Portions of this software were developed by the University of Cambridge
   10  * Computer Laboratory as part of the CTSRD Project, with support from the
   11  * UK Higher Education Innovation Fund (HEIF).
   12  *
   13  * Redistribution and use in source and binary forms, with or without
   14  * modification, are permitted provided that the following conditions
   15  * are met:
   16  * 1. Redistributions of source code must retain the above copyright
   17  *    notice, this list of conditions and the following disclaimer.
   18  * 2. Redistributions in binary form must reproduce the above copyright
   19  *    notice, this list of conditions and the following disclaimer in the
   20  *    documentation and/or other materials provided with the distribution.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  */
   34 
   35 #include <machine/asm.h>
   36 #include <machine/param.h>
   37 __FBSDID("$FreeBSD: releng/11.0/sys/riscv/riscv/cpufunc_asm.S 295972 2016-02-24 16:50:34Z br $");
   38 
   39         .text
   40         .align  2
   41 
   42 .Lpage_mask:
   43         .word   PAGE_MASK
   44 
   45 ENTRY(riscv_nullop)
   46         ret
   47 END(riscv_nullop)
   48 
   49 /*
   50  * Generic functions to read/modify/write the internal coprocessor registers
   51  */
   52 
   53 ENTRY(riscv_tlb_flushID)
   54         sfence.vm
   55         ret
   56 END(riscv_tlb_flushID)
   57 
   58 ENTRY(riscv_tlb_flushID_SE)
   59         sfence.vm
   60         ret
   61 END(riscv_tlb_flushID_SE)
   62 
   63 /*
   64  * void riscv_dcache_wb_range(vm_offset_t, vm_size_t)
   65  */
   66 ENTRY(riscv_dcache_wb_range)
   67         sfence.vm
   68         ret
   69 END(riscv_dcache_wb_range)
   70 
   71 /*
   72  * void riscv_dcache_wbinv_range(vm_offset_t, vm_size_t)
   73  */
   74 ENTRY(riscv_dcache_wbinv_range)
   75         sfence.vm
   76         ret
   77 END(riscv_dcache_wbinv_range)
   78 
   79 /*
   80  * void riscv_dcache_inv_range(vm_offset_t, vm_size_t)
   81  */
   82 ENTRY(riscv_dcache_inv_range)
   83         sfence.vm
   84         ret
   85 END(riscv_dcache_inv_range)
   86 
   87 /*
   88  * void riscv_idcache_wbinv_range(vm_offset_t, vm_size_t)
   89  */
   90 ENTRY(riscv_idcache_wbinv_range)
   91         fence.i
   92         sfence.vm
   93         ret
   94 END(riscv_idcache_wbinv_range)
   95 
   96 /*
   97  * void riscv_icache_sync_range(vm_offset_t, vm_size_t)
   98  */
   99 ENTRY(riscv_icache_sync_range)
  100         fence.i
  101         ret
  102 END(riscv_icache_sync_range)

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