1 /*-
2 * Copyright (c) 2015 The FreeBSD Foundation
3 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
4 * All rights reserved.
5 *
6 * Portions of this software were developed by Andrew Turner under
7 * sponsorship from the FreeBSD Foundation.
8 *
9 * Portions of this software were developed by SRI International and the
10 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
12 *
13 * Portions of this software were developed by the University of Cambridge
14 * Computer Laboratory as part of the CTSRD Project, with support from the
15 * UK Higher Education Innovation Fund (HEIF).
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39 #include "opt_kstack_pages.h"
40 #include "opt_platform.h"
41
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/bus.h>
48 #include <sys/cpu.h>
49 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
53 #include <sys/proc.h>
54 #include <sys/sched.h>
55 #include <sys/smp.h>
56
57 #include <vm/vm.h>
58 #include <vm/pmap.h>
59 #include <vm/vm_extern.h>
60 #include <vm/vm_kern.h>
61
62 #include <machine/intr.h>
63 #include <machine/smp.h>
64 #ifdef VFP
65 #include <machine/vfp.h>
66 #endif
67
68 #ifdef FDT
69 #include <dev/ofw/openfirm.h>
70 #include <dev/ofw/ofw_cpu.h>
71 #endif
72
73 boolean_t ofw_cpu_reg(phandle_t node, u_int, cell_t *);
74
75 extern struct pcpu __pcpu[];
76
77 uint32_t __riscv_boot_ap[MAXCPU];
78
79 static enum {
80 CPUS_UNKNOWN,
81 #ifdef FDT
82 CPUS_FDT,
83 #endif
84 } cpu_enum_method;
85
86 static device_identify_t riscv64_cpu_identify;
87 static device_probe_t riscv64_cpu_probe;
88 static device_attach_t riscv64_cpu_attach;
89
90 static int ipi_handler(void *);
91
92 struct mtx ap_boot_mtx;
93 struct pcb stoppcbs[MAXCPU];
94
95 #ifdef INVARIANTS
96 static uint32_t cpu_reg[MAXCPU][2];
97 #endif
98 static device_t cpu_list[MAXCPU];
99
100 void mpentry(unsigned long cpuid);
101 void init_secondary(uint64_t);
102
103 uint8_t secondary_stacks[MAXCPU - 1][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
104
105 /* Set to 1 once we're ready to let the APs out of the pen. */
106 volatile int aps_ready = 0;
107
108 /* Temporary variables for init_secondary() */
109 void *dpcpu[MAXCPU - 1];
110
111 static device_method_t riscv64_cpu_methods[] = {
112 /* Device interface */
113 DEVMETHOD(device_identify, riscv64_cpu_identify),
114 DEVMETHOD(device_probe, riscv64_cpu_probe),
115 DEVMETHOD(device_attach, riscv64_cpu_attach),
116
117 DEVMETHOD_END
118 };
119
120 static devclass_t riscv64_cpu_devclass;
121 static driver_t riscv64_cpu_driver = {
122 "riscv64_cpu",
123 riscv64_cpu_methods,
124 0
125 };
126
127 DRIVER_MODULE(riscv64_cpu, cpu, riscv64_cpu_driver, riscv64_cpu_devclass, 0, 0);
128
129 static void
130 riscv64_cpu_identify(driver_t *driver, device_t parent)
131 {
132
133 if (device_find_child(parent, "riscv64_cpu", -1) != NULL)
134 return;
135 if (BUS_ADD_CHILD(parent, 0, "riscv64_cpu", -1) == NULL)
136 device_printf(parent, "add child failed\n");
137 }
138
139 static int
140 riscv64_cpu_probe(device_t dev)
141 {
142 u_int cpuid;
143
144 cpuid = device_get_unit(dev);
145 if (cpuid >= MAXCPU || cpuid > mp_maxid)
146 return (EINVAL);
147
148 device_quiet(dev);
149 return (0);
150 }
151
152 static int
153 riscv64_cpu_attach(device_t dev)
154 {
155 const uint32_t *reg;
156 size_t reg_size;
157 u_int cpuid;
158 int i;
159
160 cpuid = device_get_unit(dev);
161
162 if (cpuid >= MAXCPU || cpuid > mp_maxid)
163 return (EINVAL);
164 KASSERT(cpu_list[cpuid] == NULL, ("Already have cpu %u", cpuid));
165
166 reg = cpu_get_cpuid(dev, ®_size);
167 if (reg == NULL)
168 return (EINVAL);
169
170 if (bootverbose) {
171 device_printf(dev, "register <");
172 for (i = 0; i < reg_size; i++)
173 printf("%s%x", (i == 0) ? "" : " ", reg[i]);
174 printf(">\n");
175 }
176
177 /* Set the device to start it later */
178 cpu_list[cpuid] = dev;
179
180 return (0);
181 }
182
183 static void
184 release_aps(void *dummy __unused)
185 {
186 int cpu, i;
187
188 if (mp_ncpus == 1)
189 return;
190
191 /* Setup the IPI handler */
192 riscv_setup_ipihandler(ipi_handler);
193
194 atomic_store_rel_int(&aps_ready, 1);
195
196 printf("Release APs\n");
197
198 for (i = 0; i < 2000; i++) {
199 if (smp_started) {
200 for (cpu = 0; cpu <= mp_maxid; cpu++) {
201 if (CPU_ABSENT(cpu))
202 continue;
203 }
204 return;
205 }
206 DELAY(1000);
207 }
208
209 printf("APs not started\n");
210 }
211 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
212
213 void
214 init_secondary(uint64_t cpu)
215 {
216 struct pcpu *pcpup;
217
218 /* Setup the pcpu pointer */
219 pcpup = &__pcpu[cpu];
220 __asm __volatile("mv gp, %0" :: "r"(pcpup));
221
222 /* Spin until the BSP releases the APs */
223 while (!aps_ready)
224 __asm __volatile("wfi");
225
226 /* Initialize curthread */
227 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
228 pcpup->pc_curthread = pcpup->pc_idlethread;
229 pcpup->pc_curpcb = pcpup->pc_idlethread->td_pcb;
230
231 /*
232 * Identify current CPU. This is necessary to setup
233 * affinity registers and to provide support for
234 * runtime chip identification.
235 */
236 identify_cpu();
237
238 /* Enable software interrupts */
239 riscv_unmask_ipi();
240
241 /* Start per-CPU event timers. */
242 cpu_initclocks_ap();
243
244 #ifdef VFP
245 /* TODO: init FPU */
246 #endif
247
248 /* Enable interrupts */
249 intr_enable();
250
251 mtx_lock_spin(&ap_boot_mtx);
252
253 atomic_add_rel_32(&smp_cpus, 1);
254
255 if (smp_cpus == mp_ncpus) {
256 /* enable IPI's, tlb shootdown, freezes etc */
257 atomic_store_rel_int(&smp_started, 1);
258 }
259
260 mtx_unlock_spin(&ap_boot_mtx);
261
262 /* Enter the scheduler */
263 sched_throw(NULL);
264
265 panic("scheduler returned us to init_secondary");
266 /* NOTREACHED */
267 }
268
269 static int
270 ipi_handler(void *arg)
271 {
272 u_int ipi_bitmap;
273 u_int cpu, ipi;
274 int bit;
275
276 /*
277 * We have shared interrupt line for both IPI and HTIF,
278 * so we don't really need to clear pending bit here
279 * as it will be cleared later in htif_intr.
280 * But lets assume HTIF is optional part, so do clear
281 * pending bit if there is no new entires in htif_ring.
282 */
283 machine_command(ECALL_CLEAR_IPI, 0);
284
285 cpu = PCPU_GET(cpuid);
286
287 mb();
288
289 ipi_bitmap = atomic_readandclear_int(PCPU_PTR(pending_ipis));
290 if (ipi_bitmap == 0)
291 return (FILTER_HANDLED);
292
293 while ((bit = ffs(ipi_bitmap))) {
294 bit = (bit - 1);
295 ipi = (1 << bit);
296 ipi_bitmap &= ~ipi;
297
298 mb();
299
300 switch (ipi) {
301 case IPI_AST:
302 CTR0(KTR_SMP, "IPI_AST");
303 break;
304 case IPI_PREEMPT:
305 CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
306 sched_preempt(curthread);
307 break;
308 case IPI_RENDEZVOUS:
309 CTR0(KTR_SMP, "IPI_RENDEZVOUS");
310 smp_rendezvous_action();
311 break;
312 case IPI_STOP:
313 case IPI_STOP_HARD:
314 CTR0(KTR_SMP, (ipi == IPI_STOP) ? "IPI_STOP" : "IPI_STOP_HARD");
315 savectx(&stoppcbs[cpu]);
316
317 /* Indicate we are stopped */
318 CPU_SET_ATOMIC(cpu, &stopped_cpus);
319
320 /* Wait for restart */
321 while (!CPU_ISSET(cpu, &started_cpus))
322 cpu_spinwait();
323
324 CPU_CLR_ATOMIC(cpu, &started_cpus);
325 CPU_CLR_ATOMIC(cpu, &stopped_cpus);
326 CTR0(KTR_SMP, "IPI_STOP (restart)");
327 break;
328 case IPI_HARDCLOCK:
329 CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
330 hardclockintr();
331 break;
332 default:
333 panic("Unknown IPI %#0x on cpu %d", ipi, curcpu);
334 }
335 }
336
337 return (FILTER_HANDLED);
338 }
339
340 struct cpu_group *
341 cpu_topo(void)
342 {
343
344 return (smp_topo_none());
345 }
346
347 /* Determine if we running MP machine */
348 int
349 cpu_mp_probe(void)
350 {
351
352 return (mp_ncpus > 1);
353 }
354
355 #ifdef FDT
356 static boolean_t
357 cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
358 {
359 uint64_t target_cpu;
360 struct pcpu *pcpup;
361
362 /* Check we are able to start this cpu */
363 if (id > mp_maxid)
364 return (0);
365
366 KASSERT(id < MAXCPU, ("Too many CPUs"));
367
368 KASSERT(addr_size == 1 || addr_size == 2, ("Invalid register size"));
369 #ifdef INVARIANTS
370 cpu_reg[id][0] = reg[0];
371 if (addr_size == 2)
372 cpu_reg[id][1] = reg[1];
373 #endif
374
375 target_cpu = reg[0];
376 if (addr_size == 2) {
377 target_cpu <<= 32;
378 target_cpu |= reg[1];
379 }
380
381 pcpup = &__pcpu[id];
382
383 /* We are already running on cpu 0 */
384 if (id == 0) {
385 pcpup->pc_reg = target_cpu;
386 return (1);
387 }
388
389 pcpu_init(pcpup, id, sizeof(struct pcpu));
390 pcpup->pc_reg = target_cpu;
391
392 dpcpu[id - 1] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
393 M_WAITOK | M_ZERO);
394 dpcpu_init(dpcpu[id - 1], id);
395
396 printf("Starting CPU %u (%lx)\n", id, target_cpu);
397 __riscv_boot_ap[id] = 1;
398
399 CPU_SET(id, &all_cpus);
400
401 return (1);
402 }
403 #endif
404
405 /* Initialize and fire up non-boot processors */
406 void
407 cpu_mp_start(void)
408 {
409
410 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
411
412 CPU_SET(0, &all_cpus);
413
414 switch(cpu_enum_method) {
415 #ifdef FDT
416 case CPUS_FDT:
417 ofw_cpu_early_foreach(cpu_init_fdt, true);
418 break;
419 #endif
420 case CPUS_UNKNOWN:
421 break;
422 }
423 }
424
425 /* Introduce rest of cores to the world */
426 void
427 cpu_mp_announce(void)
428 {
429 }
430
431 void
432 cpu_mp_setmaxid(void)
433 {
434 #ifdef FDT
435 int cores;
436
437 cores = ofw_cpu_early_foreach(NULL, false);
438 if (cores > 0) {
439 cores = MIN(cores, MAXCPU);
440 if (bootverbose)
441 printf("Found %d CPUs in the device tree\n", cores);
442 mp_ncpus = cores;
443 mp_maxid = cores - 1;
444 cpu_enum_method = CPUS_FDT;
445 return;
446 }
447 #endif
448
449 if (bootverbose)
450 printf("No CPU data, limiting to 1 core\n");
451 mp_ncpus = 1;
452 mp_maxid = 0;
453 }
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