The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/riscv/riscv/plic.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
    5  * All rights reserved.
    6  * Copyright (c) 2019 Mitchell Horne <mhorne@FreeBSD.org>
    7  *
    8  * Portions of this software were developed by SRI International and the
    9  * University of Cambridge Computer Laboratory (Department of Computer Science
   10  * and Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of
   11  * the DARPA SSITH research programme.
   12  *
   13  * Redistribution and use in source and binary forms, with or without
   14  * modification, are permitted provided that the following conditions
   15  * are met:
   16  * 1. Redistributions of source code must retain the above copyright
   17  *    notice, this list of conditions and the following disclaimer.
   18  * 2. Redistributions in binary form must reproduce the above copyright
   19  *    notice, this list of conditions and the following disclaimer in the
   20  *    documentation and/or other materials provided with the distribution.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  */
   34 
   35 #include <sys/cdefs.h>
   36 __FBSDID("$FreeBSD$");
   37 
   38 #include <sys/param.h>
   39 #include <sys/systm.h>
   40 #include <sys/bus.h>
   41 #include <sys/kernel.h>
   42 #include <sys/ktr.h>
   43 #include <sys/module.h>
   44 #include <sys/proc.h>
   45 #include <sys/rman.h>
   46 #include <sys/smp.h>
   47 
   48 #include <machine/bus.h>
   49 #include <machine/intr.h>
   50 
   51 #include <dev/ofw/openfirm.h>
   52 #include <dev/ofw/ofw_bus.h>
   53 #include <dev/ofw/ofw_bus_subr.h>
   54 
   55 #include "pic_if.h"
   56 
   57 #define PLIC_MAX_IRQS           1024
   58 
   59 #define PLIC_PRIORITY_BASE      0x000000U
   60 
   61 #define PLIC_ENABLE_BASE        0x002000U
   62 #define PLIC_ENABLE_STRIDE      0x80U
   63 
   64 #define PLIC_CONTEXT_BASE       0x200000U
   65 #define PLIC_CONTEXT_STRIDE     0x1000U
   66 #define PLIC_CONTEXT_THRESHOLD  0x0U
   67 #define PLIC_CONTEXT_CLAIM      0x4U
   68 
   69 #define PLIC_PRIORITY(n)        (PLIC_PRIORITY_BASE + (n) * sizeof(uint32_t))
   70 #define PLIC_ENABLE(sc, n, h)                                           \
   71     (sc->contexts[h].enable_offset + ((n) / 32) * sizeof(uint32_t))
   72 #define PLIC_THRESHOLD(sc, h)                                           \
   73     (sc->contexts[h].context_offset + PLIC_CONTEXT_THRESHOLD)
   74 #define PLIC_CLAIM(sc, h)                                               \
   75     (sc->contexts[h].context_offset + PLIC_CONTEXT_CLAIM)
   76 
   77 static pic_disable_intr_t       plic_disable_intr;
   78 static pic_enable_intr_t        plic_enable_intr;
   79 static pic_map_intr_t           plic_map_intr;
   80 static pic_setup_intr_t         plic_setup_intr;
   81 static pic_post_ithread_t       plic_post_ithread;
   82 static pic_pre_ithread_t        plic_pre_ithread;
   83 static pic_bind_intr_t          plic_bind_intr;
   84 
   85 struct plic_irqsrc {
   86         struct intr_irqsrc      isrc;
   87         u_int                   irq;
   88 };
   89 
   90 struct plic_context {
   91         bus_size_t enable_offset;
   92         bus_size_t context_offset;
   93 };
   94 
   95 struct plic_softc {
   96         device_t                dev;
   97         struct resource *       intc_res;
   98         struct plic_irqsrc      isrcs[PLIC_MAX_IRQS];
   99         struct plic_context     contexts[MAXCPU];
  100         int                     ndev;
  101 };
  102 
  103 #define RD4(sc, reg)                            \
  104     bus_read_4(sc->intc_res, (reg))
  105 #define WR4(sc, reg, val)                       \
  106     bus_write_4(sc->intc_res, (reg), (val))
  107 
  108 static u_int plic_irq_cpu;
  109 
  110 static int
  111 riscv_hartid_to_cpu(int hartid)
  112 {
  113         int i;
  114 
  115         CPU_FOREACH(i) {
  116                 if (pcpu_find(i)->pc_hart == hartid)
  117                         return (i);
  118         }
  119 
  120         return (-1);
  121 }
  122 
  123 static int
  124 plic_get_hartid(device_t dev, phandle_t intc)
  125 {
  126         int hart;
  127 
  128         /* Check the interrupt controller layout. */
  129         if (OF_searchencprop(intc, "#interrupt-cells", &hart,
  130             sizeof(hart)) == -1) {
  131                 device_printf(dev,
  132                     "Could not find #interrupt-cells for phandle %u\n", intc);
  133                 return (-1);
  134         }
  135 
  136         /*
  137          * The parent of the interrupt-controller is the CPU we are
  138          * interested in, so search for its hart ID.
  139          */
  140         if (OF_searchencprop(OF_parent(intc), "reg", (pcell_t *)&hart,
  141             sizeof(hart)) == -1) {
  142                 device_printf(dev, "Could not find hartid\n");
  143                 return (-1);
  144         }
  145 
  146         return (hart);
  147 }
  148 
  149 static inline void
  150 plic_irq_dispatch(struct plic_softc *sc, u_int irq,
  151     struct trapframe *tf)
  152 {
  153         struct plic_irqsrc *src;
  154 
  155         src = &sc->isrcs[irq];
  156 
  157         if (intr_isrc_dispatch(&src->isrc, tf) != 0)
  158                 device_printf(sc->dev, "Stray irq %u detected\n", irq);
  159 }
  160 
  161 static int
  162 plic_intr(void *arg)
  163 {
  164         struct plic_softc *sc;
  165         struct trapframe *tf;
  166         uint32_t pending;
  167         uint32_t cpu;
  168 
  169         sc = arg;
  170         cpu = PCPU_GET(cpuid);
  171 
  172         pending = RD4(sc, PLIC_CLAIM(sc, cpu));
  173         if (pending) {
  174                 tf = curthread->td_intr_frame;
  175                 plic_irq_dispatch(sc, pending, tf);
  176                 WR4(sc, PLIC_CLAIM(sc, cpu), pending);
  177         }
  178 
  179         return (FILTER_HANDLED);
  180 }
  181 
  182 static void
  183 plic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
  184 {
  185         struct plic_softc *sc;
  186         struct plic_irqsrc *src;
  187 
  188         sc = device_get_softc(dev);
  189         src = (struct plic_irqsrc *)isrc;
  190 
  191         WR4(sc, PLIC_PRIORITY(src->irq), 0);
  192 }
  193 
  194 static void
  195 plic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
  196 {
  197         struct plic_softc *sc;
  198         struct plic_irqsrc *src;
  199 
  200         sc = device_get_softc(dev);
  201         src = (struct plic_irqsrc *)isrc;
  202 
  203         WR4(sc, PLIC_PRIORITY(src->irq), 1);
  204 }
  205 
  206 static int
  207 plic_map_intr(device_t dev, struct intr_map_data *data,
  208     struct intr_irqsrc **isrcp)
  209 {
  210         struct intr_map_data_fdt *daf;
  211         struct plic_softc *sc;
  212 
  213         sc = device_get_softc(dev);
  214 
  215         if (data->type != INTR_MAP_DATA_FDT)
  216                 return (ENOTSUP);
  217 
  218         daf = (struct intr_map_data_fdt *)data;
  219         if (daf->ncells != 1 || daf->cells[0] > sc->ndev)
  220                 return (EINVAL);
  221 
  222         *isrcp = &sc->isrcs[daf->cells[0]].isrc;
  223 
  224         return (0);
  225 }
  226 
  227 static int
  228 plic_probe(device_t dev)
  229 {
  230 
  231         if (!ofw_bus_status_okay(dev))
  232                 return (ENXIO);
  233 
  234         if (!ofw_bus_is_compatible(dev, "riscv,plic0") &&
  235             !ofw_bus_is_compatible(dev, "sifive,plic-1.0.0"))
  236                 return (ENXIO);
  237 
  238         device_set_desc(dev, "RISC-V PLIC");
  239 
  240         return (BUS_PROBE_DEFAULT);
  241 }
  242 
  243 static int
  244 plic_attach(device_t dev)
  245 {
  246         struct plic_irqsrc *isrcs;
  247         struct plic_softc *sc;
  248         struct intr_pic *pic;
  249         pcell_t *cells;
  250         uint32_t irq;
  251         const char *name;
  252         phandle_t node;
  253         phandle_t xref;
  254         uint32_t cpu;
  255         int error;
  256         int rid;
  257         int nintr;
  258         int context;
  259         int i;
  260         int hart;
  261 
  262         sc = device_get_softc(dev);
  263 
  264         sc->dev = dev;
  265 
  266         node = ofw_bus_get_node(dev);
  267         if ((OF_getencprop(node, "riscv,ndev", &sc->ndev,
  268             sizeof(sc->ndev))) < 0) {
  269                 device_printf(dev,
  270                     "Error: could not get number of devices\n");
  271                 return (ENXIO);
  272         }
  273 
  274         if (sc->ndev >= PLIC_MAX_IRQS) {
  275                 device_printf(dev,
  276                     "Error: invalid ndev (%d)\n", sc->ndev);
  277                 return (ENXIO);
  278         }
  279 
  280         /* Request memory resources */
  281         rid = 0;
  282         sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  283             RF_ACTIVE);
  284         if (sc->intc_res == NULL) {
  285                 device_printf(dev,
  286                     "Error: could not allocate memory resources\n");
  287                 return (ENXIO);
  288         }
  289 
  290         /* Register the interrupt sources */
  291         isrcs = sc->isrcs;
  292         name = device_get_nameunit(sc->dev);
  293         for (irq = 1; irq <= sc->ndev; irq++) {
  294                 isrcs[irq].irq = irq;
  295                 error = intr_isrc_register(&isrcs[irq].isrc, sc->dev,
  296                     0, "%s,%u", name, irq);
  297                 if (error != 0)
  298                         return (error);
  299 
  300                 WR4(sc, PLIC_PRIORITY(irq), 0);
  301         }
  302 
  303         /*
  304          * Calculate the per-cpu enable and context register offsets.
  305          *
  306          * This is tricky for a few reasons. The PLIC divides the interrupt
  307          * enable, threshold, and claim bits by "context", where each context
  308          * routes to a Core-Local Interrupt Controller (CLIC).
  309          *
  310          * The tricky part is that the PLIC spec imposes no restrictions on how
  311          * these contexts are laid out. So for example, there is no guarantee
  312          * that each CPU will have both a machine mode and supervisor context,
  313          * or that different PLIC implementations will organize the context
  314          * registers in the same way. On top of this, we must handle the fact
  315          * that cpuid != hartid, as they may have been renumbered during boot.
  316          * We perform the following steps:
  317          *
  318          * 1. Examine the PLIC's "interrupts-extended" property and skip any
  319          *    entries that are not for supervisor external interrupts.
  320          *
  321          * 2. Walk up the device tree to find the corresponding CPU, and grab
  322          *    it's hart ID.
  323          *
  324          * 3. Convert the hart to a cpuid, and calculate the register offsets
  325          *    based on the context number.
  326          */
  327         nintr = OF_getencprop_alloc_multi(node, "interrupts-extended",
  328             sizeof(uint32_t), (void **)&cells);
  329         if (nintr <= 0) {
  330                 device_printf(dev, "Could not read interrupts-extended\n");
  331                 return (ENXIO);
  332         }
  333 
  334         /* interrupts-extended is a list of phandles and interrupt types. */
  335         for (i = 0, context = 0; i < nintr; i += 2, context++) {
  336                 /* Skip M-mode external interrupts */
  337                 if (cells[i + 1] != IRQ_EXTERNAL_SUPERVISOR)
  338                         continue;
  339 
  340                 /* Get the hart ID from the CLIC's phandle. */
  341                 hart = plic_get_hartid(dev, OF_node_from_xref(cells[i]));
  342                 if (hart < 0) {
  343                         OF_prop_free(cells);
  344                         return (ENXIO);
  345                 }
  346 
  347                 /* Get the corresponding cpuid. */
  348                 cpu = riscv_hartid_to_cpu(hart);
  349                 if (cpu < 0) {
  350                         device_printf(dev, "Invalid hart!\n");
  351                         OF_prop_free(cells);
  352                         return (ENXIO);
  353                 }
  354 
  355                 /* Set the enable and context register offsets for the CPU. */
  356                 sc->contexts[cpu].enable_offset = PLIC_ENABLE_BASE +
  357                     context * PLIC_ENABLE_STRIDE;
  358                 sc->contexts[cpu].context_offset = PLIC_CONTEXT_BASE +
  359                     context * PLIC_CONTEXT_STRIDE;
  360         }
  361         OF_prop_free(cells);
  362 
  363         /* Set the threshold for each CPU to accept all priorities. */
  364         CPU_FOREACH(cpu)
  365                 WR4(sc, PLIC_THRESHOLD(sc, cpu), 0);
  366 
  367         xref = OF_xref_from_node(node);
  368         pic = intr_pic_register(sc->dev, xref);
  369         if (pic == NULL)
  370                 return (ENXIO);
  371 
  372         csr_set(sie, SIE_SEIE);
  373 
  374         return (intr_pic_claim_root(sc->dev, xref, plic_intr, sc, 0));
  375 }
  376 
  377 static void
  378 plic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
  379 {
  380 
  381         plic_disable_intr(dev, isrc);
  382 }
  383 
  384 static void
  385 plic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
  386 {
  387 
  388         plic_enable_intr(dev, isrc);
  389 }
  390 
  391 static int
  392 plic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
  393     struct resource *res, struct intr_map_data *data)
  394 {
  395         struct plic_softc *sc;
  396         struct plic_irqsrc *src;
  397 
  398         sc = device_get_softc(dev);
  399         src = (struct plic_irqsrc *)isrc;
  400 
  401         /* Bind to the boot CPU for now. */
  402         CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
  403         plic_bind_intr(dev, isrc);
  404 
  405         return (0);
  406 }
  407 
  408 static int
  409 plic_bind_intr(device_t dev, struct intr_irqsrc *isrc)
  410 {
  411         struct plic_softc *sc;
  412         struct plic_irqsrc *src;
  413         uint32_t reg;
  414         u_int cpu;
  415 
  416         sc = device_get_softc(dev);
  417         src = (struct plic_irqsrc *)isrc;
  418 
  419         /* Disable the interrupt source on all CPUs. */
  420         CPU_FOREACH(cpu) {
  421                 reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu));
  422                 reg &= ~(1 << (src->irq % 32));
  423                 WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg);
  424         }
  425 
  426         if (CPU_EMPTY(&isrc->isrc_cpu)) {
  427                 cpu = plic_irq_cpu = intr_irq_next_cpu(plic_irq_cpu, &all_cpus);
  428                 CPU_SETOF(cpu, &isrc->isrc_cpu);
  429         } else {
  430                 /*
  431                  * We will only bind to a single CPU so select the first
  432                  * CPU found.
  433                  */
  434                 cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
  435         }
  436 
  437         /* Enable the interrupt on the selected CPU only. */
  438         reg = RD4(sc, PLIC_ENABLE(sc, src->irq, cpu));
  439         reg |= (1 << (src->irq % 32));
  440         WR4(sc, PLIC_ENABLE(sc, src->irq, cpu), reg);
  441 
  442         return (0);
  443 }
  444 
  445 static device_method_t plic_methods[] = {
  446         DEVMETHOD(device_probe,         plic_probe),
  447         DEVMETHOD(device_attach,        plic_attach),
  448 
  449         DEVMETHOD(pic_disable_intr,     plic_disable_intr),
  450         DEVMETHOD(pic_enable_intr,      plic_enable_intr),
  451         DEVMETHOD(pic_map_intr,         plic_map_intr),
  452         DEVMETHOD(pic_pre_ithread,      plic_pre_ithread),
  453         DEVMETHOD(pic_post_ithread,     plic_post_ithread),
  454         DEVMETHOD(pic_setup_intr,       plic_setup_intr),
  455         DEVMETHOD(pic_bind_intr,        plic_bind_intr),
  456 
  457         DEVMETHOD_END
  458 };
  459 
  460 static driver_t plic_driver = {
  461         "plic",
  462         plic_methods,
  463         sizeof(struct plic_softc),
  464 };
  465 
  466 static devclass_t plic_devclass;
  467 
  468 EARLY_DRIVER_MODULE(plic, simplebus, plic_driver, plic_devclass,
  469     0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);

Cache object: cdf30e10ce1d51fee2962bc8e36bf7e2


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