timer.c

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    1 /*-
    2  * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * Portions of this software were developed by SRI International and the
    6  * University of Cambridge Computer Laboratory under DARPA/AFRL contract
    7  * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
    8  *
    9  * Portions of this software were developed by the University of Cambridge
   10  * Computer Laboratory as part of the CTSRD Project, with support from the
   11  * UK Higher Education Innovation Fund (HEIF).
   12  *
   13  * Redistribution and use in source and binary forms, with or without
   14  * modification, are permitted provided that the following conditions
   15  * are met:
   16  * 1. Redistributions of source code must retain the above copyright
   17  *    notice, this list of conditions and the following disclaimer.
   18  * 2. Redistributions in binary form must reproduce the above copyright
   19  *    notice, this list of conditions and the following disclaimer in the
   20  *    documentation and/or other materials provided with the distribution.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  */
   34 
   35 /*
   36  * RISC-V Timer
   37  */
   38 
   39 #include "opt_platform.h"
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: releng/11.0/sys/riscv/riscv/timer.c 295892 2016-02-22 14:19:45Z br $");
   43 
   44 #include <sys/param.h>
   45 #include <sys/systm.h>
   46 #include <sys/bus.h>
   47 #include <sys/kernel.h>
   48 #include <sys/module.h>
   49 #include <sys/malloc.h>
   50 #include <sys/rman.h>
   51 #include <sys/timeet.h>
   52 #include <sys/timetc.h>
   53 #include <sys/watchdog.h>
   54 
   55 #include <sys/proc.h>
   56 
   57 #include <machine/bus.h>
   58 #include <machine/cpu.h>
   59 #include <machine/intr.h>
   60 #include <machine/asm.h>
   61 #include <machine/trap.h>
   62 
   63 #include <dev/fdt/fdt_common.h>
   64 #include <dev/ofw/openfirm.h>
   65 #include <dev/ofw/ofw_bus.h>
   66 #include <dev/ofw/ofw_bus_subr.h>
   67 
   68 #define DEFAULT_FREQ    1000000
   69 
   70 struct riscv_tmr_softc {
   71         struct resource         *res[1];
   72         void                    *ihl[1];
   73         uint32_t                clkfreq;
   74         struct eventtimer       et;
   75 };
   76 
   77 static struct riscv_tmr_softc *riscv_tmr_sc = NULL;
   78 
   79 static struct resource_spec timer_spec[] = {
   80         { SYS_RES_IRQ,          0,      RF_ACTIVE },
   81         { -1, 0 }
   82 };
   83 
   84 static timecounter_get_t riscv_tmr_get_timecount;
   85 
   86 static struct timecounter riscv_tmr_timecount = {
   87         .tc_name           = "RISC-V Timecounter",
   88         .tc_get_timecount  = riscv_tmr_get_timecount,
   89         .tc_poll_pps       = NULL,
   90         .tc_counter_mask   = ~0u,
   91         .tc_frequency      = 0,
   92         .tc_quality        = 1000,
   93 };
   94 
   95 static long
   96 get_counts(void)
   97 {
   98 
   99         return (csr_read(stime));
  100 }
  101 
  102 static unsigned
  103 riscv_tmr_get_timecount(struct timecounter *tc)
  104 {
  105 
  106         return (get_counts());
  107 }
  108 
  109 static int
  110 riscv_tmr_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
  111 {
  112         struct riscv_tmr_softc *sc;
  113         int counts;
  114 
  115         sc = (struct riscv_tmr_softc *)et->et_priv;
  116 
  117         if (first != 0) {
  118                 counts = ((uint32_t)et->et_frequency * first) >> 32;
  119                 machine_command(ECALL_MTIMECMP, counts);
  120                 return (0);
  121         }
  122 
  123         return (EINVAL);
  124 
  125 }
  126 
  127 static int
  128 riscv_tmr_stop(struct eventtimer *et)
  129 {
  130         struct riscv_tmr_softc *sc;
  131 
  132         sc = (struct riscv_tmr_softc *)et->et_priv;
  133 
  134         /* TODO */
  135 
  136         return (0);
  137 }
  138 
  139 static int
  140 riscv_tmr_intr(void *arg)
  141 {
  142         struct riscv_tmr_softc *sc;
  143 
  144         sc = (struct riscv_tmr_softc *)arg;
  145 
  146         /*
  147          * Clear interrupt pending bit.
  148          * Note: SIP_STIP bit is not implemented in sip register
  149          * in Spike simulator, so use machine command to clear
  150          * interrupt pending bit in mip.
  151          */
  152         machine_command(ECALL_CLEAR_PENDING, 0);
  153 
  154         if (sc->et.et_active)
  155                 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
  156 
  157         return (FILTER_HANDLED);
  158 }
  159 
  160 static int
  161 riscv_tmr_fdt_probe(device_t dev)
  162 {
  163 
  164         if (!ofw_bus_status_okay(dev))
  165                 return (ENXIO);
  166 
  167         if (ofw_bus_is_compatible(dev, "riscv,timer")) {
  168                 device_set_desc(dev, "RISC-V Timer");
  169                 return (BUS_PROBE_DEFAULT);
  170         }
  171 
  172         return (ENXIO);
  173 }
  174 
  175 static int
  176 riscv_tmr_attach(device_t dev)
  177 {
  178         struct riscv_tmr_softc *sc;
  179         phandle_t node;
  180         pcell_t clock;
  181         int error;
  182 
  183         sc = device_get_softc(dev);
  184         if (riscv_tmr_sc)
  185                 return (ENXIO);
  186 
  187         /* Get the base clock frequency */
  188         node = ofw_bus_get_node(dev);
  189         if (node > 0) {
  190                 error = OF_getprop(node, "clock-frequency", &clock,
  191                     sizeof(clock));
  192                 if (error > 0) {
  193                         sc->clkfreq = fdt32_to_cpu(clock);
  194                 }
  195         }
  196 
  197         if (sc->clkfreq == 0)
  198                 sc->clkfreq = DEFAULT_FREQ;
  199 
  200         if (sc->clkfreq == 0) {
  201                 device_printf(dev, "No clock frequency specified\n");
  202                 return (ENXIO);
  203         }
  204 
  205         if (bus_alloc_resources(dev, timer_spec, sc->res)) {
  206                 device_printf(dev, "could not allocate resources\n");
  207                 return (ENXIO);
  208         }
  209 
  210         riscv_tmr_sc = sc;
  211 
  212         /* Setup IRQs handler */
  213         error = bus_setup_intr(dev, sc->res[0], INTR_TYPE_CLK,
  214             riscv_tmr_intr, NULL, sc, &sc->ihl[0]);
  215         if (error) {
  216                 device_printf(dev, "Unable to alloc int resource.\n");
  217                 return (ENXIO);
  218         }
  219 
  220         riscv_tmr_timecount.tc_frequency = sc->clkfreq;
  221         tc_init(&riscv_tmr_timecount);
  222 
  223         sc->et.et_name = "RISC-V Eventtimer";
  224         sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
  225         sc->et.et_quality = 1000;
  226 
  227         sc->et.et_frequency = sc->clkfreq;
  228         sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
  229         sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
  230         sc->et.et_start = riscv_tmr_start;
  231         sc->et.et_stop = riscv_tmr_stop;
  232         sc->et.et_priv = sc;
  233         et_register(&sc->et);
  234 
  235         return (0);
  236 }
  237 
  238 static device_method_t riscv_tmr_fdt_methods[] = {
  239         DEVMETHOD(device_probe,         riscv_tmr_fdt_probe),
  240         DEVMETHOD(device_attach,        riscv_tmr_attach),
  241         { 0, 0 }
  242 };
  243 
  244 static driver_t riscv_tmr_fdt_driver = {
  245         "timer",
  246         riscv_tmr_fdt_methods,
  247         sizeof(struct riscv_tmr_softc),
  248 };
  249 
  250 static devclass_t riscv_tmr_fdt_devclass;
  251 
  252 EARLY_DRIVER_MODULE(timer, simplebus, riscv_tmr_fdt_driver, riscv_tmr_fdt_devclass,
  253     0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
  254 EARLY_DRIVER_MODULE(timer, ofwbus, riscv_tmr_fdt_driver, riscv_tmr_fdt_devclass,
  255     0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);
  256 
  257 void
  258 DELAY(int usec)
  259 {
  260         int32_t counts, counts_per_usec;
  261         uint32_t first, last;
  262 
  263         /*
  264          * Check the timers are setup, if not just
  265          * use a for loop for the meantime
  266          */
  267         if (riscv_tmr_sc == NULL) {
  268                 for (; usec > 0; usec--)
  269                         for (counts = 200; counts > 0; counts--)
  270                                 /*
  271                                  * Prevent the compiler from optimizing
  272                                  * out the loop
  273                                  */
  274                                 cpufunc_nullop();
  275                 return;
  276         }
  277 
  278         /* Get the number of times to count */
  279         counts_per_usec = ((riscv_tmr_timecount.tc_frequency / 1000000) + 1);
  280 
  281         /*
  282          * Clamp the timeout at a maximum value (about 32 seconds with
  283          * a 66MHz clock). *Nobody* should be delay()ing for anywhere
  284          * near that length of time and if they are, they should be hung
  285          * out to dry.
  286          */
  287         if (usec >= (0x80000000U / counts_per_usec))
  288                 counts = (0x80000000U / counts_per_usec) - 1;
  289         else
  290                 counts = usec * counts_per_usec;
  291 
  292         first = get_counts();
  293 
  294         while (counts > 0) {
  295                 last = get_counts();
  296                 counts -= (int32_t)(last - first);
  297                 first = last;
  298         }
  299 }

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FreeBSD/Linux Kernel Cross Reference sys/riscv/riscv/timer.c

FreeBSD/Linux Kernel Cross Reference
sys/riscv/riscv/timer.c