1 /*-
2 * Copyright (c) 2004 Jason L. Wright (jason@thought.net)
3 * Copyright (c) 2006 Marius Strobl <marius@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 *
27 * from: OpenBSD: clkbrdreg.h,v 1.2 2004/10/01 15:36:30 jason Exp
28 *
29 * $FreeBSD$
30 */
31
32 #ifndef _SPARC64_FHC_CLKBRDREG_H_
33 #define _SPARC64_FHC_CLKBRDREG_H_
34
35 /* register bank 0 */
36 #define CLK_CF_REG2 0x20 /* clock frequency register 2 */
37 #define CLK_CF_REG2_REN_RCONS 0x80 /* reset enable: remote console */
38 #define CLK_CF_REG2_REN_GEN 0x40 /* reset enable: frequency change */
39 #define CLK_CF_REG2_REN_WDOG 0x20 /* reset enable: watchdog */
40 #define CLK_CF_REG2_DIV1 0x10 /* CPU module divisor bit 1 */
41 #define CLK_CF_REG2_RANGE 0x0c /* clock range */
42 #define CLK_CF_REG2_DIV0 0x02 /* CPU module divisor bit 0 */
43 #define CLK_CF_REG2_FREQ8 0x01 /* frequency bit 8 */
44
45 /* register bank 1 */
46 #define CLK_CTRL 0x00 /* system control register */
47 #define CLK_CTRL_IEN_FAN 0x80 /* intr enable: fan failure */
48 #define CLK_CTRL_IEN_DC 0x40 /* intr enable: power supply DC */
49 #define CLK_CTRL_IEN_AC 0x20 /* intr enable: AC power */
50 #define CLK_CTRL_IEN_BRD 0x10 /* intr enable: board insert */
51 #define CLK_CTRL_POFF 0x08 /* turn off system power */
52 #define CLK_CTRL_LLED 0x04 /* left led (reversed) */
53 #define CLK_CTRL_MLED 0x02 /* middle led */
54 #define CLK_CTRL_RLED 0x01 /* right led */
55 #define CLK_STS1 0x10 /* system status register 1 */
56 #define CLK_STS1_SLOTS_MASK 0xc0 /* system status 1 slots mask */
57 #define CLK_STS1_SLOTS_16 0x40 /* 16 slots */
58 #define CLK_STS1_SLOTS_8 0xc0 /* 8 slots */
59 #define CLK_STS1_SLOTS_4 0x80 /* 4 slots */
60 #define CLK_STS1_SLOTS_TESTBED 0x00 /* test machine */
61 #define CLK_STS1_SECURE 0x20 /* key in position secure (reversed) */
62 #define CLK_STS1_FAN 0x10 /* fan tray present (reversed) */
63 #define CLK_STS1_BRD 0x08 /* board inserted (reversed) */
64 #define CLK_STS1_PS0 0x04 /* power supply 0 present (reversed) */
65 #define CLK_STS1_RST_WDOG 0x02 /* rst by: watchdog (reversed) */
66 #define CLK_STS1_RST_GEN 0x01 /* rst by: freq change (reversed) */
67 #define CLK_STS2 0x20 /* system status register 2 */
68 #define CLK_STS2_RST_RCONS 0x80 /* rst by: remote console (reversed) */
69 #define CLK_STS2_OK_PS0 0x40 /* ok: power supply 0 */
70 #define CLK_STS2_OK_33V 0x20 /* ok: 3.3V on clock board */
71 #define CLK_STS2_OK_50V 0x10 /* ok: 5.0V on clock board */
72 #define CLK_STS2_FAIL_AC 0x08 /* failed: AC power */
73 #define CLK_STS2_FAIL_FAN 0x04 /* failed: rack fans */
74 #define CLK_STS2_OK_ACFAN 0x02 /* ok: 4 AC box fans */
75 #define CLK_STS2_OK_KEYFAN 0x01 /* ok: keyswitch fans */
76 #define CLK_PSTS1 0x30 /* power supply 1 status register */
77 #define CLK_PSTS1_PS 0x80 /* power supply 1 present (reversed) */
78 #define CLK_PPRES 0x40 /* power supply presence register */
79 #define CLK_PPRES_CSHARE 0x80 /* current share backplane */
80 #define CLK_PPRES_OK_MASK 0x7f /* precharge and peripheral pwr mask */
81 #define CLK_PPRES_OK_P_5V 0x40 /* ok: peripheral 5V */
82 #define CLK_PPRES_OK_P_12V 0x20 /* ok: peripheral 12V */
83 #define CLK_PPRES_OK_AUX_5V 0x10 /* ok: auxiliary 5V */
84 #define CLK_PPRES_OK_PP_5V 0x08 /* ok: peripheral 5V precharge */
85 #define CLK_PPRES_OK_PP_12V 0x04 /* ok: peripheral 12V precharge */
86 #define CLK_PPRES_OK_SP_3V 0x02 /* ok: system 3.3V precharge */
87 #define CLK_PPRES_OK_SP_5V 0x01 /* ok: system 5V precharge */
88 #define CLK_TEMP 0x50 /* temperature register */
89 #define CLK_IDIAG 0x60 /* interrupt diagnostic register */
90 #define CLK_PSTS2 0x70 /* power supply 2 status register */
91
92 /* register bank 2 */
93 #define CLKVER_SLOTS 0x00 /* clock version slots register */
94 #define CLKVER_SLOTS_MASK 0x80 /* clock version slots mask */
95 #define CLKVER_SLOTS_PLUS 0x00 /* plus system (reversed) */
96
97 #endif /* !_SPARC64_FHC_CLKBRDREG_H_ */
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