1 /*-
2 * Copyright (c) 1997 Berkeley Software Design, Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. Berkeley Software Design Inc's name may not be used to endorse or
13 * promote products derived from this software without specific prior
14 * written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY BERKELEY SOFTWARE DESIGN INC ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BERKELEY SOFTWARE DESIGN INC BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * from: BSDI: asi.h,v 1.3 1997/08/08 14:31:42 torek
29 * $FreeBSD: releng/6.0/sys/sparc64/include/asi.h 100180 2002-07-16 16:22:25Z tmm $
30 */
31
32 #ifndef _MACHINE_ASI_H_
33 #define _MACHINE_ASI_H_
34
35 /*
36 * Standard v9 asis
37 */
38 #define ASI_N 0x4
39 #define ASI_NL 0xc
40 #define ASI_AIUP 0x10
41 #define ASI_AIUS 0x11
42 #define ASI_AIUPL 0x18
43 #define ASI_AIUSL 0x19
44 #define ASI_P 0x80
45 #define ASI_S 0x81
46 #define ASI_PNF 0x82
47 #define ASI_SNF 0x83
48 #define ASI_PL 0x88
49 #define ASI_SL 0x89
50 #define ASI_PNFL 0x8a
51 #define ASI_SNFL 0x8b
52
53 /*
54 * UltraSPARC extensions. ASIs limited to a certain family are annotated.
55 */
56 #define ASI_PHYS_USE_EC 0x14
57 #define ASI_PHYS_BYPASS_EC_WITH_EBIT 0x15
58 #define ASI_PHYS_USE_EC_L 0x1c
59 #define ASI_PHYS_BYPASS_EC_WITH_EBIT_L 0x1d
60
61 #define ASI_NUCLEUS_QUAD_LDD 0x24
62 #define ASI_NUCLEUS_QUAD_LDD_L 0x2c
63
64 #define ASI_PCACHE_STATUS_DATA 0x30 /* US-III Cu */
65 #define ASI_PCACHE_DATA 0x31 /* US-III Cu */
66 #define ASI_PCACHE_TAG 0x32 /* US-III Cu */
67 #define ASI_PCACHE_SNOOP_TAG 0x33 /* US-III Cu */
68
69 #define ASI_ATOMIC_QUAD_LDD_PHYS 0x34 /* US-III Cu */
70
71 #define ASI_WCACHE_VALID_BITS 0x38 /* US-III Cu */
72 #define ASI_WCACHE_DATA 0x39 /* US-III Cu */
73 #define ASI_WCACHE_TAG 0x3a /* US-III Cu */
74 #define ASI_WCACHE_SNOOP_TAG 0x3b /* US-III Cu */
75
76 #define ASI_ATOMIC_QUAD_LDD_PHYS_L 0x3c /* US-III Cu */
77
78 #define ASI_SRAM_FAST_INIT 0x40 /* US-III Cu */
79
80 #define ASI_DCACHE_INVALIDATE 0x42 /* US-III Cu */
81 #define ASI_DCACHE_UTAG 0x43 /* US-III Cu */
82 #define ASI_DCACHE_SNOOP_TAG 0x44 /* US-III Cu */
83
84 /* Named ASI_DCUCR on US-III, but is mostly identical except for added bits. */
85 #define ASI_LSU_CTL_REG 0x45
86
87 #define ASI_DCACHE_DATA 0x46
88 #define ASI_DCACHE_TAG 0x47
89
90 #define ASI_INTR_DISPATCH_STATUS 0x48
91 #define ASI_INTR_RECEIVE 0x49
92 #define ASI_UPA_CONFIG_REG 0x4a /* US-I, II */
93
94 #define ASI_FIREPLANE_CONFIG_REG 0x4a /* US-III Cu */
95 #define AA_FIREPLANE_CONFIG 0x0 /* US-III Cu */
96 #define AA_FIREPLANE_ADDRESS 0x8 /* US-III Cu */
97
98 #define ASI_ESTATE_ERROR_EN_REG 0x4b
99 #define ASI_AFSR 0x4c
100 #define ASI_AFAR 0x4d
101
102 #define ASI_ECACHE_TAG_DATA 0x4e
103
104 #define ASI_IMMU_TAG_TARGET_REG 0x50
105 #define ASI_IMMU 0x50
106 #define AA_IMMU_TTR 0x0
107 #define AA_IMMU_SFSR 0x18
108 #define AA_IMMU_TSB 0x28
109 #define AA_IMMU_TAR 0x30
110 #define AA_IMMU_TSB_PEXT_REG 0x48 /* US-III family */
111 #define AA_IMMU_TSB_SEXT_REG 0x50 /* US-III family */
112 #define AA_IMMU_TSB_NEXT_REG 0x58 /* US-III family */
113
114 #define ASI_IMMU_TSB_8KB_PTR_REG 0x51
115 #define ASI_IMMU_TSB_64KB_PTR_REG 0x52
116
117 #define ASI_SERIAL_ID 0x53 /* US-III family */
118
119 #define ASI_ITLB_DATA_IN_REG 0x54
120 /* US-III Cu: also ASI_ITLB_CAM_ADDRESS_REG */
121 #define ASI_ITLB_DATA_ACCESS_REG 0x55
122 #define ASI_ITLB_TAG_READ_REG 0x56
123 #define ASI_IMMU_DEMAP 0x57
124
125 #define ASI_DMMU_TAG_TARGET_REG 0x58
126 #define ASI_DMMU 0x58
127 #define AA_DMMU_TTR 0x0
128 #define AA_DMMU_PCXR 0x8
129 #define AA_DMMU_SCXR 0x10
130 #define AA_DMMU_SFSR 0x18
131 #define AA_DMMU_SFAR 0x20
132 #define AA_DMMU_TSB 0x28
133 #define AA_DMMU_TAR 0x30
134 #define AA_DMMU_VWPR 0x38
135 #define AA_DMMU_PWPR 0x40
136 #define AA_DMMU_TSB_PEXT_REG 0x48
137 #define AA_DMMU_TSB_SEXT_REG 0x50
138 #define AA_DMMU_TSB_NEXT_REG 0x58
139
140 #define ASI_DMMU_TSB_8KB_PTR_REG 0x59
141 #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
142 #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
143 #define ASI_DTLB_DATA_IN_REG 0x5c
144 /* US-III Cu: also ASI_DTLB_CAM_ADDRESS_REG */
145 #define ASI_DTLB_DATA_ACCESS_REG 0x5d
146 #define ASI_DTLB_TAG_READ_REG 0x5e
147 #define ASI_DMMU_DEMAP 0x5f
148
149 #define ASI_IIU_INST_TRAP 0x60 /* US-III family */
150
151 #define ASI_ICACHE_INSTR 0x66
152 #define ASI_ICACHE_TAG 0x67
153 #define ASI_ICACHE_SNOOP_TAG 0x68 /* US-III family */
154 #define ASI_ICACHE_PRE_DECODE 0x6e /* US-I, II */
155 #define ASI_ICACHE_PRE_NEXT_FIELD 0x6f /* US-I, II */
156
157 #define ASI_BLK_AUIP 0x70
158 #define ASI_BLK_AIUS 0x71
159
160 #define ASI_MCU_CONFIG_REG 0x72 /* US-III Cu */
161 #define AA_MCU_TIMING1_REG 0x0 /* US-III Cu */
162 #define AA_MCU_TIMING2_REG 0x8 /* US-III Cu */
163 #define AA_MCU_TIMING3_REG 0x10 /* US-III Cu */
164 #define AA_MCU_TIMING4_REG 0x18 /* US-III Cu */
165 #define AA_MCU_DEC1_REG 0x20 /* US-III Cu */
166 #define AA_MCU_DEC2_REG 0x28 /* US-III Cu */
167 #define AA_MCU_DEC3_REG 0x30 /* US-III Cu */
168 #define AA_MCU_DEC4_REG 0x38 /* US-III Cu */
169 #define AA_MCU_ADDR_CNTL_REG 0x40 /* US-III Cu */
170
171 #define ASI_ECACHE_DATA 0x74 /* US-III Cu */
172 #define ASI_ECACHE_CONTROL 0x75 /* US-III Cu */
173 #define ASI_ECACHE_W 0x76
174
175 /*
176 * With the advent of the US-III, the numbering has changed, as additional
177 * registers were inserted in between. We retain the original ordering for
178 * now, and append an A to the inserted registers.
179 * Exceptions are AA_SDB_INTR_D6 and AA_SDB_INTR_D7, which were appended
180 * at the end.
181 */
182 #define ASI_SDB_INTR_W 0x77
183 #define AA_SDB_INTR_D0 0x40
184 #define AA_SDB_INTR_D0A 0x48 /* US-III family */
185 #define AA_SDB_INTR_D1 0x50
186 #define AA_SDB_INTR_D1A 0x5A /* US-III family */
187 #define AA_SDB_INTR_D2 0x60
188 #define AA_SDB_INTR_D2A 0x68 /* US-III family */
189 #define AA_INTR_SEND 0x70
190 #define AA_SDB_INTR_D6 0x80 /* US-III family */
191 #define AA_SDB_INTR_D7 0x88 /* US-III family */
192
193 #define ASI_BLK_AIUPL 0x78
194 #define ASI_BLK_AIUSL 0x79
195
196 #define ASI_ECACHE_R 0x7e
197
198 #define ASI_SDB_INTR_R 0x7f
199
200 #define ASI_PST8_P 0xc0
201 #define ASI_PST8_S 0xc1
202 #define ASI_PST16_P 0xc2
203 #define ASI_PST16_S 0xc3
204 #define ASI_PST32_P 0xc4
205 #define ASI_PST32_S 0xc5
206
207 #define ASI_PST8_PL 0xc8
208 #define ASI_PST8_SL 0xc9
209 #define ASI_PST16_PL 0xca
210 #define ASI_PST16_SL 0xcb
211 #define ASI_PST32_PL 0xcc
212 #define ASI_PST32_SL 0xcd
213
214 #define ASI_FL8_P 0xd0
215 #define ASI_FL8_S 0xd1
216 #define ASI_FL16_P 0xd2
217 #define ASI_FL16_S 0xd3
218 #define ASI_FL8_PL 0xd8
219 #define ASI_FL8_SL 0xd9
220 #define ASI_FL16_PL 0xda
221 #define ASI_FL16_SL 0xdb
222
223 #define ASI_BLK_COMMIT_P 0xe0
224 #define ASI_BLK_COMMIT_S 0xe1
225 #define ASI_BLK_P 0xf0
226 #define ASI_BLK_S 0xf1
227 #define ASI_BLK_PL 0xf8
228 #define ASI_BLK_SL 0xf9
229
230 #endif /* !_MACHINE_ASI_H_ */
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