The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/sparc64/include/dcr.h

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    1 /*-
    2  * Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/10.1/sys/sparc64/include/dcr.h 206450 2010-04-10 11:13:51Z marius $
   27  */
   28 
   29 #ifndef _MACHINE_DCR_H_
   30 #define _MACHINE_DCR_H_
   31 
   32 /*
   33  * Definitions for the UltraSPARC-III Depatch Control Register (ASR 18).
   34  */
   35 #define DCR_MS                  (1UL << 0)
   36 #define DCR_IFPOE               (1UL << 1)
   37 #define DCR_SI                  (1UL << 3)
   38 #define DCR_RPE                 (1UL << 4)
   39 #define DCR_BPE                 (1UL << 5)
   40 
   41 #define DCR_OBSDATA_SHIFT       6
   42 #define DCR_OBSDATA_CT_BITS     8
   43 #define DCR_OBSDATA_CT_MASK                                             \
   44         (((1UL << DCR_OBSDATA_CT_BITS) - 1) << DCR_OBSDATA_SHIFT)
   45 
   46 /* The following bits are valid for the UltraSPARC-III++/IV+ only. */
   47 #define DCR_IPE                 (1UL << 2)
   48 
   49 #define DCR_OBSDATA_CTP_BITS    6
   50 #define DCR_OBSDATA_CTP_MASK                                            \
   51         (((1UL << DCR_OBSDATA_CTP_BITS) - 1) << DCR_OBSDATA_SHIFT)
   52 
   53 #define DCR_DPE                 (1UL << 12)
   54 
   55 /* The following bits are valid for the UltraSPARC-IV+ only. */
   56 #define DCR_BPM_SHIFT           13
   57 #define DCR_BPM_BITS            2
   58 #define DCR_BPM_MASK                                                    \
   59         (((1UL << DCR_BPM_BITS) - 1) << DCR_BPM_SHIFT)
   60 #define DCR_BPM_1HIST_GSHARE    (0UL << DCR_BPM_SHIFT)
   61 #define DCR_BPM_2HIST_GSHARE    (1UL << DCR_BPM_SHIFT)
   62 #define DCR_BPM_PC              (2UL << DCR_BPM_SHIFT)
   63 #define DCR_BPM_2HIST_MIXED     (3UL << DCR_BPM_SHIFT)
   64 
   65 #define DCR_JPE                 (1UL << 15)
   66 #define DCR_ITPE                (1UL << 16)
   67 #define DCR_DTPE                (1UL << 17)
   68 #define DCR_PPE                 (1UL << 18)
   69 
   70 #endif  /* _MACHINE_DCR_H_ */

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