Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/sparc64/include/instr.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 1994 David S. Miller, davem@nadzieja.rutgers.edu 3 * Copyright (c) 1995 Paul Kranenburg 4 * Copyright (c) 2001 Thomas Moestl <tmm@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by David Miller. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * from: NetBSD: db_disasm.c,v 1.9 2000/08/16 11:29:42 pk Exp 33 * 34 * $FreeBSD: releng/6.4/sys/sparc64/include/instr.h 139825 2005-01-07 02:29:27Z imp $ 35 */ 36 37 #ifndef _MACHINE_INSTR_H_ 38 #define _MACHINE_INSTR_H_ 39 40 /* 41 * Definitions for all instruction formats 42 */ 43 #define IF_OP_SHIFT 30 44 #define IF_OP_BITS 2 45 #define IF_IMM_SHIFT 0 /* Immediate/Displacement */ 46 47 /* 48 * Definitions for format 2 49 */ 50 #define IF_F2_RD_SHIFT 25 51 #define IF_F2_RD_BITS 5 52 #define IF_F2_A_SHIFT 29 53 #define IF_F2_A_BITS 1 54 #define IF_F2_COND_SHIFT 25 55 #define IF_F2_COND_BITS 4 56 #define IF_F2_RCOND_SHIFT 25 57 #define IF_F2_RCOND_BITS 3 58 #define IF_F2_OP2_SHIFT 22 59 #define IF_F2_OP2_BITS 3 60 #define IF_F2_CC1_SHIFT 21 61 #define IF_F2_CC1_BITS 1 62 #define IF_F2_CC0_SHIFT 20 63 #define IF_F2_CC0_BITS 1 64 #define IF_F2_CC_SHIFT 20 /* CC0 and CC1 combined. */ 65 #define IF_F2_CC_BITS 2 66 #define IF_F2_D16HI_SHIFT 20 67 #define IF_F2_D16HI_BITS 2 68 #define IF_F2_P_SHIFT 19 69 #define IF_F2_P_BITS 1 70 #define IF_F2_RS1_SHIFT 14 71 #define IF_F2_RS1_BITS 5 72 73 /* 74 * Definitions for format 3 75 */ 76 #define IF_F3_OP3_SHIFT 19 77 #define IF_F3_OP3_BITS 6 78 #define IF_F3_RD_SHIFT IF_F2_RD_SHIFT 79 #define IF_F3_RD_BITS IF_F2_RD_BITS 80 #define IF_F3_FCN_SHIFT 25 81 #define IF_F3_FCN_BITS 5 82 #define IF_F3_CC1_SHIFT 26 83 #define IF_F3_CC1_BITS 1 84 #define IF_F3_CC0_SHIFT 25 85 #define IF_F3_CC0_BITS 1 86 #define IF_F3_CC_SHIFT 25 /* CC0 and CC1 combined. */ 87 #define IF_F3_CC_BITS 2 88 #define IF_F3_RS1_SHIFT IF_F2_RS1_SHIFT 89 #define IF_F3_RS1_BITS IF_F2_RS1_BITS 90 #define IF_F3_I_SHIFT 13 91 #define IF_F3_I_BITS 1 92 #define IF_F3_X_SHIFT 12 93 #define IF_F3_X_BITS 1 94 #define IF_F3_RCOND_SHIFT 10 95 #define IF_F3_RCOND_BITS 3 96 #define IF_F3_IMM_ASI_SHIFT 5 97 #define IF_F3_IMM_ASI_BITS 8 98 #define IF_F3_OPF_SHIFT 5 99 #define IF_F3_OPF_BITS 9 100 #define IF_F3_CMASK_SHIFT 4 101 #define IF_F3_CMASK_BITS 3 102 #define IF_F3_RS2_SHIFT 0 103 #define IF_F3_RS2_BITS 5 104 #define IF_F3_SHCNT32_SHIFT 0 105 #define IF_F3_SHCNT32_BITS 5 106 #define IF_F3_SHCNT64_SHIFT 0 107 #define IF_F3_SHCNT64_BITS 6 108 109 /* 110 * Definitions for format 4 111 */ 112 #define IF_F4_OP3_SHIFT IF_F3_OP3_SHIFT 113 #define IF_F4_OP3_BITS IF_F3_OP3_BITS 114 #define IF_F4_RD_SHIFT IF_F2_RD_SHIFT 115 #define IF_F4_RD_BITS IF_F2_RD_BITS 116 #define IF_F4_RS1_SHIFT IF_F2_RS1_SHIFT 117 #define IF_F4_RS1_BITS IF_F2_RS1_BITS 118 #define IF_F4_TCOND_SHIFT IF_F2_COND_SHIFT /* cond for Tcc */ 119 #define IF_F4_TCOND_BITS IF_F2_COND_BITS 120 #define IF_F4_CC2_SHIFT 18 121 #define IF_F4_CC2_BITS 1 122 #define IF_F4_COND_SHIFT 14 123 #define IF_F4_COND_BITS 4 124 #define IF_F4_I_SHIFT IF_F3_I_SHIFT 125 #define IF_F4_I_BITS IF_F3_I_BITS 126 #define IF_F4_OPF_CC_SHIFT 11 127 #define IF_F4_OPF_CC_BITS 3 128 #define IF_F4_CC1_SHIFT 12 129 #define IF_F4_CC1_BITS 1 130 #define IF_F4_CC0_SHIFT 11 131 #define IF_F4_CC0_BITS 1 132 #define IF_F4_RCOND_SHIFT IF_F3_RCOND_SHIFT 133 #define IF_F4_RCOND_BITS IF_F3_RCOND_BITS 134 #define IF_F4_OPF_LOW_SHIFT 5 135 #define IF_F4_RS2_SHIFT IF_F3_RS2_SHIFT 136 #define IF_F4_RS2_BITS IF_F3_RS2_BITS 137 #define IF_F4_SW_TRAP_SHIFT 0 138 #define IF_F4_SW_TRAP_BITS 7 139 140 /* 141 * Macros to decode instructions 142 */ 143 /* Extract a field */ 144 #define IF_MASK(s, w) (((1 << (w)) - 1) << (s)) 145 #define IF_EXTRACT(x, s, w) (((x) & IF_MASK((s), (w))) >> (s)) 146 #define IF_DECODE(x, f) \ 147 IF_EXTRACT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 148 149 /* Sign-extend a field of width W */ 150 #define IF_SEXT(x, w) \ 151 (((x) & (1L << ((w) - 1))) != 0 ? \ 152 (-1L - ((x) ^ ((1L << (w)) - 1))) : (x)) 153 154 #if 0 155 /* 156 * The following C variant is from db_disassemble.c, and surely faster, but it 157 * relies on behaviour that is undefined by the C standard (>> in conjunction 158 * with signed negative arguments). 159 */ 160 #define IF_SEXT(v, w) ((((long long)(v)) << (64 - w)) >> (64 - w)) 161 /* Assembler version of the above */ 162 #define IF_SEXT(v, w) \ 163 { u_long t; ( __asm __volatile("sllx %1, %2, %0; srax %0, %2, %0" : 164 "=r" (t) : "r" (v) : "i" (64 - w)); t)} 165 #endif 166 167 /* All instruction formats */ 168 #define IF_OP(i) IF_DECODE(i, OP) 169 170 /* Instruction format 2 */ 171 #define IF_F2_RD(i) IF_DECODE((i), F2_RD) 172 #define IF_F2_A(i) IF_DECODE((i), F2_A) 173 #define IF_F2_COND(i) IF_DECODE((i), F2_COND) 174 #define IF_F2_RCOND(i) IF_DECODE((i), F2_RCOND) 175 #define IF_F2_OP2(i) IF_DECODE((i), F2_OP2) 176 #define IF_F2_CC1(i) IF_DECODE((i), F2_CC1) 177 #define IF_F2_CC0(i) IF_DECODE((i), F2_CC0) 178 #define IF_F2_CC(i) IF_DECODE((i), F2_CC) 179 #define IF_F2_D16HI(i) IF_DECODE((i), F2_D16HI) 180 #define IF_F2_P(i) IF_DECODE((i), F2_P) 181 #define IF_F2_RS1(i) IF_DECODE((i), F2_RS1) 182 183 /* Instruction format 3 */ 184 #define IF_F3_OP3(i) IF_DECODE((i), F3_OP3) 185 #define IF_F3_RD(i) IF_F2_RD((i)) 186 #define IF_F3_FCN(i) IF_DECODE((i), F3_FCN) 187 #define IF_F3_CC1(i) IF_DECODE((i), F3_CC1) 188 #define IF_F3_CC0(i) IF_DECODE((i), F3_CC0) 189 #define IF_F3_CC(i) IF_DECODE((i), F3_CC) 190 #define IF_F3_RS1(i) IF_F2_RS1((i)) 191 #define IF_F3_I(i) IF_DECODE((i), F3_I) 192 #define IF_F3_X(i) IF_DECODE((i), F3_X) 193 #define IF_F3_RCOND(i) IF_DECODE((i), F3_RCOND) 194 #define IF_F3_IMM_ASI(i) IF_DECODE((i), F3_IMM_ASI) 195 #define IF_F3_OPF(i) IF_DECODE((i), F3_OPF) 196 #define IF_F3_CMASK(i) IF_DECODE((i), F3_CMASK) 197 #define IF_F3_RS2(i) IF_DECODE((i), F3_RS2) 198 #define IF_F3_SHCNT32(i) IF_DECODE((i), F3_SHCNT32) 199 #define IF_F3_SHCNT64(i) IF_DECODE((i), F3_SHCNT64) 200 201 /* Instruction format 4 */ 202 #define IF_F4_OP3(i) IF_F3_OP3((i)) 203 #define IF_F4_RD(i) IF_F3_RD((i)) 204 #define IF_F4_TCOND(i) IF_DECODE((i), F4_TCOND) 205 #define IF_F4_RS1(i) IF_F3_RS1((i)) 206 #define IF_F4_CC2(i) IF_DECODE((i), F4_CC2) 207 #define IF_F4_COND(i) IF_DECODE((i), F4_COND) 208 #define IF_F4_I(i) IF_F3_I((i)) 209 #define IF_F4_OPF_CC(i) IF_DECODE((i), F4_OPF_CC) 210 #define IF_F4_RCOND(i) IF_F3_RCOND((i)) 211 #define IF_F4_OPF_LOW(i, w) IF_EXTRACT((i), IF_F4_OPF_LOW_SHIFT, (w)) 212 #define IF_F4_RS2(i) IF_F3_RS2((i)) 213 #define IF_F4_SW_TRAP(i) IF_DECODE((i), F4_SW_TRAP) 214 215 /* Extract an immediate from an instruction, with an without sign extension */ 216 #define IF_IMM(i, w) IF_EXTRACT((i), IF_IMM_SHIFT, (w)) 217 #define IF_SIMM(i, w) ({ u_long b = (w), x = IF_IMM((i), b); IF_SEXT((x), b); }) 218 219 /* 220 * Macros to encode instructions 221 */ 222 #define IF_INSERT(x, s, w) (((x) & ((1 << (w)) - 1)) << (s)) 223 #define IF_ENCODE(x, f) \ 224 IF_INSERT((x), IF_ ## f ## _SHIFT, IF_ ## f ## _BITS) 225 226 /* All instruction formats */ 227 #define EIF_OP(x) IF_ENCODE((x), OP) 228 229 /* Instruction format 2 */ 230 #define EIF_F2_RD(x) IF_ENCODE((x), F2_RD) 231 #define EIF_F2_A(x) IF_ENCODE((x), F2_A) 232 #define EIF_F2_COND(x) IF_ENCODE((x), F2_COND) 233 #define EIF_F2_RCOND(x) IF_ENCODE((x), F2_RCOND) 234 #define EIF_F2_OP2(x) IF_ENCODE((x), F2_OP2) 235 #define EIF_F2_CC1(x) IF_ENCODE((x), F2_CC1) 236 #define EIF_F2_CC0(x) IF_ENCODE((x), F2_CC0) 237 #define EIF_F2_D16HI(x) IF_ENCODE((x), F2_D16HI) 238 #define EIF_F2_P(x) IF_ENCODE((x), F2_P) 239 #define EIF_F2_RS1(x) IF_ENCODE((x), F2_RS1) 240 241 /* Instruction format 3 */ 242 #define EIF_F3_OP3(x) IF_ENCODE((x), F3_OP3) 243 #define EIF_F3_RD(x) EIF_F2_RD((x)) 244 #define EIF_F3_FCN(x) IF_ENCODE((x), F3_FCN) 245 #define EIF_F3_CC1(x) IF_ENCODE((x), F3_CC1) 246 #define EIF_F3_CC0(x) IF_ENCODE((x), F3_CC0) 247 #define EIF_F3_RS1(x) EIF_F2_RS1((x)) 248 #define EIF_F3_I(x) IF_ENCODE((x), F3_I) 249 #define EIF_F3_X(x) IF_ENCODE((x), F3_X) 250 #define EIF_F3_RCOND(x) IF_ENCODE((x), F3_RCOND) 251 #define EIF_F3_IMM_ASI(x) IF_ENCODE((x), F3_IMM_ASI) 252 #define EIF_F3_OPF(x) IF_ENCODE((x), F3_OPF) 253 #define EIF_F3_CMASK(x) IF_ENCODE((x), F3_CMASK) 254 #define EIF_F3_RS2(x) IF_ENCODE((x), F3_RS2) 255 #define EIF_F3_SHCNT32(x) IF_ENCODE((x), F3_SHCNT32) 256 #define EIF_F3_SHCNT64(x) IF_ENCODE((x), F3_SHCNT64) 257 258 /* Instruction format 4 */ 259 #define EIF_F4_OP3(x) EIF_F3_OP3((x)) 260 #define EIF_F4_RD(x) EIF_F2_RD((x)) 261 #define EIF_F4_TCOND(x) IF_ENCODE((x), F4_TCOND) 262 #define EIF_F4_RS1(x) EIF_F2_RS1((x)) 263 #define EIF_F4_CC2(x) IF_ENCODE((x), F4_CC2) 264 #define EIF_F4_COND(x) IF_ENCODE((x), F4_COND) 265 #define EIF_F4_I(x) EIF_F3_I((x)) 266 #define EIF_F4_OPF_CC(x) IF_ENCODE((x), F4_OPF_CC) 267 #define EIF_F4_RCOND(x) EIF_F3_RCOND((x)) 268 #define EIF_F4_OPF_LOW(i, w) IF_INSERT((x), IF_F4_OPF_CC_SHIFT, (w)) 269 #define EIF_F4_RS2(x) EIF_F3_RS2((x)) 270 #define EIF_F4_SW_TRAP(x) IF_ENCODE((x), F4_SW_TRAP) 271 272 /* Immediates */ 273 #define EIF_IMM(x, w) IF_INSERT((x), IF_IMM_SHIFT, (w)) 274 #define EIF_SIMM(x, w) IF_EIMM((x), (w)) 275 276 /* 277 * OP field values (specifying the instruction format) 278 */ 279 #define IOP_FORM2 0x00 /* Format 2: sethi, branches */ 280 #define IOP_CALL 0x01 /* Format 1: call */ 281 #define IOP_MISC 0x02 /* Format 3 or 4: arith & misc */ 282 #define IOP_LDST 0x03 /* Format 4: loads and stores */ 283 284 /* 285 * OP2/OP3 values (specifying the actual instruction) 286 */ 287 /* OP2 values for format 2 (OP = 0) */ 288 #define INS0_ILLTRAP 0x00 289 #define INS0_BPcc 0x01 290 #define INS0_Bicc 0x02 291 #define INS0_BPr 0x03 292 #define INS0_SETHI 0x04 /* with rd = 0 and imm22 = 0, nop */ 293 #define INS0_FBPfcc 0x05 294 #define INS0_FBfcc 0x06 295 /* undefined 0x07 */ 296 297 /* OP3 values for Format 3 and 4 (OP = 2) */ 298 #define INS2_ADD 0x00 299 #define INS2_AND 0x01 300 #define INS2_OR 0x02 301 #define INS2_XOR 0x03 302 #define INS2_SUB 0x04 303 #define INS2_ANDN 0x05 304 #define INS2_ORN 0x06 305 #define INS2_XNOR 0x07 306 #define INS2_ADDC 0x08 307 #define INS2_MULX 0x09 308 #define INS2_UMUL 0x0a 309 #define INS2_SMUL 0x0b 310 #define INS2_SUBC 0x0c 311 #define INS2_UDIVX 0x0d 312 #define INS2_UDIV 0x0e 313 #define INS2_SDIV 0x0f 314 #define INS2_ADDcc 0x10 315 #define INS2_ANDcc 0x11 316 #define INS2_ORcc 0x12 317 #define INS2_XORcc 0x13 318 #define INS2_SUBcc 0x14 319 #define INS2_ANDNcc 0x15 320 #define INS2_ORNcc 0x16 321 #define INS2_XNORcc 0x17 322 #define INS2_ADDCcc 0x18 323 /* undefined 0x19 */ 324 #define INS2_UMULcc 0x1a 325 #define INS2_SMULcc 0x1b 326 #define INS2_SUBCcc 0x1c 327 /* undefined 0x1d */ 328 #define INS2_UDIVcc 0x1e 329 #define INS2_SDIVcc 0x1f 330 #define INS2_TADDcc 0x20 331 #define INS2_TSUBcc 0x21 332 #define INS2_TADDccTV 0x22 333 #define INS2_TSUBccTV 0x23 334 #define INS2_MULScc 0x24 335 #define INS2_SSL 0x25 /* SLLX when IF_X(i) == 1 */ 336 #define INS2_SRL 0x26 /* SRLX when IF_X(i) == 1 */ 337 #define INS2_SRA 0x27 /* SRAX when IF_X(i) == 1 */ 338 #define INS2_RD 0x28 /* and MEMBAR, STBAR */ 339 /* undefined 0x29 */ 340 #define INS2_RDPR 0x2a 341 #define INS2_FLUSHW 0x2b 342 #define INS2_MOVcc 0x2c 343 #define INS2_SDIVX 0x2d 344 #define INS2_POPC 0x2e /* undefined if IF_RS1(i) != 0 */ 345 #define INS2_MOVr 0x2f 346 #define INS2_WR 0x30 /* and SIR */ 347 #define INS2_SV_RSTR 0x31 /* saved, restored */ 348 #define INS2_WRPR 0x32 349 /* undefined 0x33 */ 350 #define INS2_FPop1 0x34 /* further encoded in opf field */ 351 #define INS2_FPop2 0x35 /* further encoded in opf field */ 352 #define INS2_IMPLDEP1 0x36 353 #define INS2_IMPLDEP2 0x37 354 #define INS2_JMPL 0x38 355 #define INS2_RETURN 0x39 356 #define INS2_Tcc 0x3a 357 #define INS2_FLUSH 0x3b 358 #define INS2_SAVE 0x3c 359 #define INS2_RESTORE 0x3d 360 #define INS2_DONE_RETR 0x3e /* done, retry */ 361 /* undefined 0x3f */ 362 363 /* OP3 values for format 3 (OP = 3) */ 364 #define INS3_LDUW 0x00 365 #define INS3_LDUB 0x01 366 #define INS3_LDUH 0x02 367 #define INS3_LDD 0x03 368 #define INS3_STW 0x04 369 #define INS3_STB 0x05 370 #define INS3_STH 0x06 371 #define INS3_STD 0x07 372 #define INS3_LDSW 0x08 373 #define INS3_LDSB 0x09 374 #define INS3_LDSH 0x0a 375 #define INS3_LDX 0x0b 376 /* undefined 0x0c */ 377 #define INS3_LDSTUB 0x0d 378 #define INS3_STX 0x0e 379 #define INS3_SWAP 0x0f 380 #define INS3_LDUWA 0x10 381 #define INS3_LDUBA 0x11 382 #define INS3_LDUHA 0x12 383 #define INS3_LDDA 0x13 384 #define INS3_STWA 0x14 385 #define INS3_STBA 0x15 386 #define INS3_STHA 0x16 387 #define INS3_STDA 0x17 388 #define INS3_LDSWA 0x18 389 #define INS3_LDSBA 0x19 390 #define INS3_LDSHA 0x1a 391 #define INS3_LDXA 0x1b 392 /* undefined 0x1c */ 393 #define INS3_LDSTUBA 0x1d 394 #define INS3_STXA 0x1e 395 #define INS3_SWAPA 0x1f 396 #define INS3_LDF 0x20 397 #define INS3_LDFSR 0x21 /* and LDXFSR */ 398 #define INS3_LDQF 0x22 399 #define INS3_LDDF 0x23 400 #define INS3_STF 0x24 401 #define INS3_STFSR 0x25 /* and STXFSR */ 402 #define INS3_STQF 0x26 403 #define INS3_STDF 0x27 404 /* undefined 0x28 - 0x2c */ 405 #define INS3_PREFETCH 0x2d 406 /* undefined 0x2e - 0x2f */ 407 #define INS3_LDFA 0x30 408 /* undefined 0x31 */ 409 #define INS3_LDQFA 0x32 410 #define INS3_LDDFA 0x33 411 #define INS3_STFA 0x34 412 /* undefined 0x35 */ 413 #define INS3_STQFA 0x36 414 #define INS3_STDFA 0x37 415 /* undefined 0x38 - 0x3b */ 416 #define INS3_CASA 0x39 417 #define INS3_PREFETCHA 0x3a 418 #define INS3_CASXA 0x3b 419 420 /* 421 * OPF values (floating point instructions, IMPLDEP) 422 */ 423 /* 424 * These values are or'ed to the FPop values to get the instructions. 425 * They describe the operand type(s). 426 */ 427 #define INSFP_i 0x000 /* 32-bit int */ 428 #define INSFP_s 0x001 /* 32-bit single */ 429 #define INSFP_d 0x002 /* 64-bit double */ 430 #define INSFP_q 0x003 /* 128-bit quad */ 431 /* FPop1. The comments give the types for which this instruction is defined. */ 432 #define INSFP1_FMOV 0x000 /* s, d, q */ 433 #define INSFP1_FNEG 0x004 /* s, d, q */ 434 #define INSFP1_FABS 0x008 /* s, d, q */ 435 #define INSFP1_FSQRT 0x028 /* s, d, q */ 436 #define INSFP1_FADD 0x040 /* s, d, q */ 437 #define INSFP1_FSUB 0x044 /* s, d, q */ 438 #define INSFP1_FMUL 0x048 /* s, d, q */ 439 #define INSFP1_FDIV 0x04c /* s, d, q */ 440 #define INSFP1_FsMULd 0x068 /* s */ 441 #define INSFP1_FdMULq 0x06c /* d */ 442 #define INSFP1_FTOx 0x080 /* s, d, q */ 443 #define INSFP1_FxTOs 0x084 /* special: i only */ 444 #define INSFP1_FxTOd 0x088 /* special: i only */ 445 #define INSFP1_FxTOq 0x08c /* special: i only */ 446 #define INSFP1_FTOs 0x0c4 /* i, d, q */ 447 #define INSFP1_FTOd 0x0c8 /* i, s, q */ 448 #define INSFP1_FTOq 0x0cc /* i, s, d */ 449 #define INSFP1_FTOi 0x0d0 /* i, s, d */ 450 451 /* FPop2 */ 452 #define INSFP2_FMOV_CCMUL 0x40 453 #define INSFP2_FMOV_CCOFFS 0x00 454 /* Use the IFCC_* constants for cc. Operand types: s, d, q */ 455 #define INSFP2_FMOV_CC(cc) ((cc) * INSFP2_FMOV_CCMUL + INSFP2_FMOV_CCOFFS) 456 #define INSFP2_FMOV_RCMUL 0x20 457 #define INSFP2_FMOV_RCOFFS 0x04 458 /* Use the IRCOND_* constants for rc. Operand types: s, d, q */ 459 #define INSFP2_FMOV_RC(rc) ((rc) * INSFP2_FMOV_RCMUL + INSFP2_FMOV_RCOFFS) 460 #define INSFP2_FCMP 0x050 /* s, d, q */ 461 #define INSFP2_FCMPE 0x054 /* s, d, q */ 462 463 /* Decode 5-bit register field into 6-bit number (for doubles and quads). */ 464 #define INSFPdq_RN(rn) (((rn) & ~1) | (((rn) & 1) << 5)) 465 466 /* IMPLDEP1 for Sun UltraSparc */ 467 #define IIDP1_EDGE8 0x00 468 #define IIDP1_EDGE8N 0x01 /* US-III */ 469 #define IIDP1_EDGE8L 0x02 470 #define IIDP1_EDGE8LN 0x03 /* US-III */ 471 #define IIDP1_EDGE16 0x04 472 #define IIDP1_EDGE16N 0x05 /* US-III */ 473 #define IIDP1_EDGE16L 0x06 474 #define IIDP1_EDGE16LN 0x07 /* US-III */ 475 #define IIDP1_EDGE32 0x08 476 #define IIDP1_EDGE32N 0x09 /* US-III */ 477 #define IIDP1_EDGE32L 0x0a 478 #define IIDP1_EDGE32LN 0x0b /* US-III */ 479 #define IIDP1_ARRAY8 0x10 480 #define IIDP1_ARRAY16 0x12 481 #define IIDP1_ARRAY32 0x14 482 #define IIDP1_ALIGNADDRESS 0x18 483 #define IIDP1_BMASK 0x19 /* US-III */ 484 #define IIDP1_ALIGNADDRESS_L 0x1a 485 #define IIDP1_FCMPLE16 0x20 486 #define IIDP1_FCMPNE16 0x22 487 #define IIDP1_FCMPLE32 0x24 488 #define IIDP1_FCMPNE32 0x26 489 #define IIDP1_FCMPGT16 0x28 490 #define IIDP1_FCMPEQ16 0x2a 491 #define IIDP1_FCMPGT32 0x2c 492 #define IIDP1_FCMPEQ32 0x2e 493 #define IIDP1_FMUL8x16 0x31 494 #define IIDP1_FMUL8x16AU 0x33 495 #define IIDP1_FMUL8X16AL 0x35 496 #define IIDP1_FMUL8SUx16 0x36 497 #define IIDP1_FMUL8ULx16 0x37 498 #define IIDP1_FMULD8SUx16 0x38 499 #define IIDP1_FMULD8ULx16 0x39 500 #define IIDP1_FPACK32 0x3a 501 #define IIDP1_FPACK16 0x3b 502 #define IIDP1_FPACKFIX 0x3d 503 #define IIDP1_PDIST 0x3e 504 #define IIDP1_FALIGNDATA 0x48 505 #define IIDP1_FPMERGE 0x4b 506 #define IIDP1_BSHUFFLE 0x4c /* US-III */ 507 #define IIDP1_FEXPAND 0x4d 508 #define IIDP1_FPADD16 0x50 509 #define IIDP1_FPADD16S 0x51 510 #define IIDP1_FPADD32 0x52 511 #define IIDP1_FPADD32S 0x53 512 #define IIDP1_SUB16 0x54 513 #define IIDP1_SUB16S 0x55 514 #define IIDP1_SUB32 0x56 515 #define IIDP1_SUB32S 0x57 516 #define IIDP1_FZERO 0x60 517 #define IIDP1_FZEROS 0x61 518 #define IIDP1_FNOR 0x62 519 #define IIDP1_FNORS 0x63 520 #define IIDP1_FANDNOT2 0x64 521 #define IIDP1_FANDNOT2S 0x65 522 #define IIDP1_NOT2 0x66 523 #define IIDP1_NOT2S 0x67 524 #define IIDP1_FANDNOT1 0x68 525 #define IIDP1_FANDNOT1S 0x69 526 #define IIDP1_FNOT1 0x6a 527 #define IIDP1_FNOT1S 0x6b 528 #define IIDP1_FXOR 0x6c 529 #define IIDP1_FXORS 0x6d 530 #define IIDP1_FNAND 0x6e 531 #define IIDP1_FNANDS 0x6f 532 #define IIDP1_FAND 0x70 533 #define IIDP1_FANDS 0x71 534 #define IIDP1_FXNOR 0x72 535 #define IIDP1_FXNORS 0x73 536 #define IIDP1_FSRC1 0x74 537 #define IIDP1_FSRC1S 0x75 538 #define IIDP1_FORNOT2 0x76 539 #define IIDP1_FORNOT2S 0x77 540 #define IIDP1_FSRC2 0x78 541 #define IIDP1_FSRC2S 0x79 542 #define IIDP1_FORNOT1 0x7a 543 #define IIDP1_FORNOT1S 0x7b 544 #define IIDP1_FOR 0x7c 545 #define IIDP1_FORS 0x7d 546 #define IIDP1_FONE 0x7e 547 #define IIDP1_FONES 0x7f 548 #define IIDP1_SHUTDOWN 0x80 549 #define IIDP1_SIAM 0x81 /* US-III */ 550 551 /* 552 * Instruction modifiers 553 */ 554 /* cond values for integer ccr's */ 555 #define IICOND_N 0x00 556 #define IICOND_E 0x01 557 #define IICOND_LE 0x02 558 #define IICOND_L 0x03 559 #define IICOND_LEU 0x04 560 #define IICOND_CS 0x05 561 #define IICOND_NEG 0x06 562 #define IICOND_VS 0x07 563 #define IICOND_A 0x08 564 #define IICOND_NE 0x09 565 #define IICOND_G 0x0a 566 #define IICOND_GE 0x0b 567 #define IICOND_GU 0x0c 568 #define IICOND_CC 0x0d 569 #define IICOND_POS 0x0e 570 #define IICOND_VC 0x0f 571 572 /* cond values for fp ccr's */ 573 #define IFCOND_N 0x00 574 #define IFCOND_NE 0x01 575 #define IFCOND_LG 0x02 576 #define IFCOND_UL 0x03 577 #define IFCOND_L 0x04 578 #define IFCOND_UG 0x05 579 #define IFCOND_G 0x06 580 #define IFCOND_U 0x07 581 #define IFCOND_A 0x08 582 #define IFCOND_E 0x09 583 #define IFCOND_UE 0x0a 584 #define IFCOND_GE 0x0b 585 #define IFCOND_UGE 0x0c 586 #define IFCOND_LE 0x0d 587 #define IFCOND_ULE 0x0e 588 #define IFCOND_O 0x0f 589 590 /* rcond values for BPr, MOVr, FMOVr */ 591 #define IRCOND_Z 0x01 592 #define IRCOND_LEZ 0x02 593 #define IRCOND_LZ 0x03 594 #define IRCOND_NZ 0x05 595 #define IRCOND_GZ 0x06 596 #define IRCOND_GEZ 0x07 597 598 /* cc values for MOVcc and FMOVcc */ 599 #define IFCC_ICC 0x04 600 #define IFCC_XCC 0x06 601 /* if true, the lower 2 bits are the fcc number */ 602 #define IFCC_FCC(c) ((c) & 3) 603 #define IFCC_GET_FCC(c) ((c) & 3) 604 #define IFCC_ISFCC(c) (((c) & 4) == 0) 605 606 /* cc values for BPc and Tcc */ 607 #define IBCC_ICC 0x00 608 #define IBCC_XCC 0x02 609 610 /* 611 * Integer registers 612 */ 613 #define IREG_G0 0x00 614 #define IREG_O0 0x08 615 #define IREG_L0 0x10 616 #define IREQ_I0 0x18 617 618 #endif /* !_MACHINE_INSTR_H_ */
Cache object: d9e0e2f1111c2562b34c8eb56de08b2f
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]