Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/sparc64/pci/apb.c
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 5 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 6 * Copyright (c) 2000 BSDi 7 * Copyright (c) 2001, 2003 Thomas Moestl <tmm@FreeBSD.org> 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: FreeBSD: src/sys/dev/pci/pci_pci.c,v 1.3 2000/12/13 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Support for the Sun APB (Advanced PCI Bridge) PCI-PCI bridge. 41 * This bridge does not fully comply to the PCI bridge specification, and is 42 * therefore not supported by the generic driver. 43 * We can use some of the pcib methods anyway. 44 */ 45 46 #include "opt_ofw_pci.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/module.h> 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 #include <sys/sysctl.h> 55 56 #include <dev/ofw/ofw_bus.h> 57 #include <dev/ofw/openfirm.h> 58 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 #include <dev/pci/pcib_private.h> 65 66 #include "pcib_if.h" 67 68 #include <sparc64/pci/ofw_pci.h> 69 #include <sparc64/pci/ofw_pcib_subr.h> 70 71 /* 72 * Bridge-specific data. 73 */ 74 struct apb_softc { 75 struct ofw_pcib_gen_softc sc_bsc; 76 uint8_t sc_iomap; 77 uint8_t sc_memmap; 78 }; 79 80 static device_probe_t apb_probe; 81 static device_attach_t apb_attach; 82 static bus_alloc_resource_t apb_alloc_resource; 83 static bus_adjust_resource_t apb_adjust_resource; 84 85 static device_method_t apb_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, apb_probe), 88 DEVMETHOD(device_attach, apb_attach), 89 90 /* Bus interface */ 91 DEVMETHOD(bus_alloc_resource, apb_alloc_resource), 92 DEVMETHOD(bus_adjust_resource, apb_adjust_resource), 93 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 94 95 /* pcib interface */ 96 DEVMETHOD(pcib_route_interrupt, ofw_pcib_gen_route_interrupt), 97 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 98 99 /* ofw_bus interface */ 100 DEVMETHOD(ofw_bus_get_node, ofw_pcib_gen_get_node), 101 102 DEVMETHOD_END 103 }; 104 105 static devclass_t pcib_devclass; 106 107 DEFINE_CLASS_1(pcib, apb_driver, apb_methods, sizeof(struct apb_softc), 108 pcib_driver); 109 EARLY_DRIVER_MODULE(apb, pci, apb_driver, pcib_devclass, 0, 0, BUS_PASS_BUS); 110 MODULE_DEPEND(apb, pci, 1, 1, 1); 111 112 /* APB specific registers */ 113 #define APBR_IOMAP 0xde 114 #define APBR_MEMMAP 0xdf 115 116 /* Definitions for the mapping registers */ 117 #define APB_IO_SCALE 0x200000 118 #define APB_MEM_SCALE 0x20000000 119 120 /* 121 * Generic device interface 122 */ 123 static int 124 apb_probe(device_t dev) 125 { 126 127 if (pci_get_vendor(dev) == 0x108e && /* Sun */ 128 pci_get_device(dev) == 0x5000) { /* APB */ 129 device_set_desc(dev, "APB PCI-PCI bridge"); 130 return (0); 131 } 132 return (ENXIO); 133 } 134 135 static void 136 apb_map_print(uint8_t map, rman_res_t scale) 137 { 138 int i, first; 139 140 for (first = 1, i = 0; i < 8; i++) { 141 if ((map & (1 << i)) != 0) { 142 printf("%s0x%jx-0x%jx", first ? "" : ", ", 143 i * scale, (i + 1) * scale - 1); 144 first = 0; 145 } 146 } 147 } 148 149 static int 150 apb_checkrange(uint8_t map, rman_res_t scale, rman_res_t start, rman_res_t end) 151 { 152 int i, ei; 153 154 i = start / scale; 155 ei = end / scale; 156 if (i > 7 || ei > 7) 157 return (0); 158 for (; i <= ei; i++) 159 if ((map & (1 << i)) == 0) 160 return (0); 161 return (1); 162 } 163 164 static int 165 apb_attach(device_t dev) 166 { 167 struct apb_softc *sc; 168 struct sysctl_ctx_list *sctx; 169 struct sysctl_oid *soid; 170 171 sc = device_get_softc(dev); 172 173 /* 174 * Get current bridge configuration. 175 */ 176 sc->sc_bsc.ops_pcib_sc.domain = pci_get_domain(dev); 177 sc->sc_bsc.ops_pcib_sc.pribus = pci_get_bus(dev); 178 pci_write_config(dev, PCIR_PRIBUS_1, sc->sc_bsc.ops_pcib_sc.pribus, 1); 179 sc->sc_bsc.ops_pcib_sc.bus.sec = 180 pci_read_config(dev, PCIR_SECBUS_1, 1); 181 sc->sc_bsc.ops_pcib_sc.bus.sub = 182 pci_read_config(dev, PCIR_SUBBUS_1, 1); 183 sc->sc_bsc.ops_pcib_sc.bridgectl = 184 pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 185 sc->sc_iomap = pci_read_config(dev, APBR_IOMAP, 1); 186 sc->sc_memmap = pci_read_config(dev, APBR_MEMMAP, 1); 187 188 /* 189 * Setup SYSCTL reporting nodes. 190 */ 191 sctx = device_get_sysctl_ctx(dev); 192 soid = device_get_sysctl_tree(dev); 193 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 194 CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.domain, 0, 195 "Domain number"); 196 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 197 CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.pribus, 0, 198 "Primary bus number"); 199 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 200 CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.bus.sec, 0, 201 "Secondary bus number"); 202 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 203 CTLFLAG_RD, &sc->sc_bsc.ops_pcib_sc.bus.sub, 0, 204 "Subordinate bus number"); 205 206 ofw_pcib_gen_setup(dev); 207 208 if (bootverbose) { 209 device_printf(dev, " domain %d\n", 210 sc->sc_bsc.ops_pcib_sc.domain); 211 device_printf(dev, " secondary bus %d\n", 212 sc->sc_bsc.ops_pcib_sc.bus.sec); 213 device_printf(dev, " subordinate bus %d\n", 214 sc->sc_bsc.ops_pcib_sc.bus.sub); 215 device_printf(dev, " I/O decode "); 216 apb_map_print(sc->sc_iomap, APB_IO_SCALE); 217 printf("\n"); 218 device_printf(dev, " memory decode "); 219 apb_map_print(sc->sc_memmap, APB_MEM_SCALE); 220 printf("\n"); 221 } 222 223 device_add_child(dev, "pci", -1); 224 return (bus_generic_attach(dev)); 225 } 226 227 /* 228 * We have to trap resource allocation requests and ensure that the bridge 229 * is set up to, or capable of handling them. 230 */ 231 static struct resource * 232 apb_alloc_resource(device_t dev, device_t child, int type, int *rid, 233 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 234 { 235 struct apb_softc *sc; 236 237 sc = device_get_softc(dev); 238 239 /* 240 * If this is a "default" allocation against this rid, we can't work 241 * out where it's coming from (we should actually never see these) so 242 * we just have to punt. 243 */ 244 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 245 device_printf(dev, "can't decode default resource id %d for " 246 "%s, bypassing\n", *rid, device_get_nameunit(child)); 247 goto passup; 248 } 249 250 /* 251 * Fail the allocation for this range if it's not supported. 252 * XXX we should probably just fix up the bridge decode and 253 * soldier on. 254 */ 255 switch (type) { 256 case SYS_RES_IOPORT: 257 if (!apb_checkrange(sc->sc_iomap, APB_IO_SCALE, start, end)) { 258 device_printf(dev, "device %s requested unsupported " 259 "I/O range 0x%jx-0x%jx\n", 260 device_get_nameunit(child), start, end); 261 return (NULL); 262 } 263 if (bootverbose) 264 device_printf(sc->sc_bsc.ops_pcib_sc.dev, "device " 265 "%s requested decoded I/O range 0x%jx-0x%jx\n", 266 device_get_nameunit(child), start, end); 267 break; 268 case SYS_RES_MEMORY: 269 if (!apb_checkrange(sc->sc_memmap, APB_MEM_SCALE, start, 270 end)) { 271 device_printf(dev, "device %s requested unsupported " 272 "memory range 0x%jx-0x%jx\n", 273 device_get_nameunit(child), start, end); 274 return (NULL); 275 } 276 if (bootverbose) 277 device_printf(sc->sc_bsc.ops_pcib_sc.dev, "device " 278 "%s requested decoded memory range 0x%jx-0x%jx\n", 279 device_get_nameunit(child), start, end); 280 break; 281 } 282 283 passup: 284 /* 285 * Bridge is OK decoding this resource, so pass it up. 286 */ 287 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 288 count, flags)); 289 } 290 291 static int 292 apb_adjust_resource(device_t dev, device_t child, int type, 293 struct resource *r, rman_res_t start, rman_res_t end) 294 { 295 struct apb_softc *sc; 296 297 sc = device_get_softc(dev); 298 switch (type) { 299 case SYS_RES_IOPORT: 300 if (!apb_checkrange(sc->sc_iomap, APB_IO_SCALE, start, end)) 301 return (ENXIO); 302 break; 303 case SYS_RES_MEMORY: 304 if (!apb_checkrange(sc->sc_memmap, APB_MEM_SCALE, start, end)) 305 return (ENXIO); 306 break; 307 } 308 return (bus_generic_adjust_resource(dev, child, type, r, start, end)); 309 }
Cache object: 99e3f51f5bd95b8eb2d6db27642a26d2
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