1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
6 * Copyright (c) 2000, BSDi
7 * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org>
8 * Copyright (c) 2005 - 2009 Marius Strobl <marius@FreeBSD.org>
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice unmodified, this list of conditions, and the following
16 * disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 #include "opt_ofw_pci.h"
37
38 #include <sys/param.h>
39 #include <sys/bus.h>
40 #include <sys/kernel.h>
41 #include <sys/libkern.h>
42 #include <sys/module.h>
43 #include <sys/pciio.h>
44
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_pci.h>
47 #include <dev/ofw/openfirm.h>
48
49 #include <machine/bus.h>
50 #ifndef SUN4V
51 #include <machine/bus_common.h>
52 #include <machine/iommureg.h>
53 #endif
54 #include <machine/resource.h>
55
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pci_private.h>
59
60 #include <sparc64/pci/ofw_pci.h>
61
62 #include "pcib_if.h"
63 #include "pci_if.h"
64
65 /* Helper functions */
66 static void ofw_pcibus_setup_device(device_t bridge, uint32_t clock,
67 u_int busno, u_int slot, u_int func);
68
69 /* Methods */
70 static bus_child_deleted_t ofw_pcibus_child_deleted;
71 static bus_child_pnpinfo_str_t ofw_pcibus_pnpinfo_str;
72 static device_attach_t ofw_pcibus_attach;
73 static device_probe_t ofw_pcibus_probe;
74 static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
75 static pci_alloc_devinfo_t ofw_pcibus_alloc_devinfo;
76 static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
77
78 static device_method_t ofw_pcibus_methods[] = {
79 /* Device interface */
80 DEVMETHOD(device_probe, ofw_pcibus_probe),
81 DEVMETHOD(device_attach, ofw_pcibus_attach),
82
83 /* Bus interface */
84 DEVMETHOD(bus_child_deleted, ofw_pcibus_child_deleted),
85 DEVMETHOD(bus_child_pnpinfo_str, ofw_pcibus_pnpinfo_str),
86 DEVMETHOD(bus_rescan, bus_null_rescan),
87
88 /* PCI interface */
89 DEVMETHOD(pci_alloc_devinfo, ofw_pcibus_alloc_devinfo),
90 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt),
91
92 /* ofw_bus interface */
93 DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo),
94 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
95 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
96 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
97 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
98 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
99
100 DEVMETHOD_END
101 };
102
103 struct ofw_pcibus_devinfo {
104 struct pci_devinfo opd_dinfo;
105 struct ofw_bus_devinfo opd_obdinfo;
106 };
107
108 static devclass_t pci_devclass;
109
110 DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods,
111 sizeof(struct pci_softc), pci_driver);
112 EARLY_DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0,
113 BUS_PASS_BUS);
114 MODULE_VERSION(ofw_pcibus, 1);
115 MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1);
116
117 static int
118 ofw_pcibus_probe(device_t dev)
119 {
120
121 if (ofw_bus_get_node(dev) == -1)
122 return (ENXIO);
123 device_set_desc(dev, "OFW PCI bus");
124
125 return (0);
126 }
127
128 /*
129 * Perform miscellaneous setups the firmware usually does not do for us.
130 */
131 static void
132 ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
133 u_int slot, u_int func)
134 {
135 #define CS_READ(n, w) \
136 PCIB_READ_CONFIG(bridge, busno, slot, func, (n), (w))
137 #define CS_WRITE(n, v, w) \
138 PCIB_WRITE_CONFIG(bridge, busno, slot, func, (n), (v), (w))
139
140 #ifndef SUN4V
141 uint32_t reg;
142
143 /*
144 * Initialize the latency timer register for busmaster devices to
145 * work properly. This is another task which the firmware doesn't
146 * always perform. The Min_Gnt register can be used to compute its
147 * recommended value: it contains the desired latency in units of
148 * 1/4 us assuming a clock rate of 33MHz. To calculate the correct
149 * latency timer value, the clock frequency of the bus (defaulting
150 * to 33MHz) should be used and no wait states assumed.
151 * For bridges, we additionally set up the bridge control and the
152 * secondary latency registers.
153 */
154 if ((CS_READ(PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) ==
155 PCIM_HDRTYPE_BRIDGE) {
156 reg = CS_READ(PCIR_BRIDGECTL_1, 1);
157 reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE |
158 PCIB_BCR_PERR_ENABLE;
159 #ifdef OFW_PCI_DEBUG
160 device_printf(bridge,
161 "bridge %d/%d/%d: control 0x%x -> 0x%x\n",
162 busno, slot, func, CS_READ(PCIR_BRIDGECTL_1, 1), reg);
163 #endif /* OFW_PCI_DEBUG */
164 CS_WRITE(PCIR_BRIDGECTL_1, reg, 1);
165
166 reg = OFW_PCI_LATENCY;
167 #ifdef OFW_PCI_DEBUG
168 device_printf(bridge,
169 "bridge %d/%d/%d: latency timer %d -> %d\n",
170 busno, slot, func, CS_READ(PCIR_SECLAT_1, 1), reg);
171 #endif /* OFW_PCI_DEBUG */
172 CS_WRITE(PCIR_SECLAT_1, reg, 1);
173 } else {
174 reg = CS_READ(PCIR_MINGNT, 1);
175 if ((int)reg > 0) {
176 switch (clock) {
177 case 33000000:
178 reg *= 8;
179 break;
180 case 66000000:
181 reg *= 4;
182 break;
183 }
184 reg = min(reg, 255);
185 } else
186 reg = OFW_PCI_LATENCY;
187 }
188 #ifdef OFW_PCI_DEBUG
189 device_printf(bridge, "device %d/%d/%d: latency timer %d -> %d\n",
190 busno, slot, func, CS_READ(PCIR_LATTIMER, 1), reg);
191 #endif /* OFW_PCI_DEBUG */
192 CS_WRITE(PCIR_LATTIMER, reg, 1);
193
194 /*
195 * Compute a value to write into the cache line size register.
196 * The role of the streaming cache is unclear in write invalidate
197 * transfers, so it is made sure that it's line size is always
198 * reached. Generally, the cache line size is fixed at 64 bytes
199 * by Fireplane/Safari, JBus and UPA.
200 */
201 CS_WRITE(PCIR_CACHELNSZ, STRBUF_LINESZ / sizeof(uint32_t), 1);
202 #endif
203
204 /*
205 * Ensure that ALi M5229 report the actual content of PCIR_PROGIF
206 * and that IDE I/O is force enabled. The former is done in order
207 * to have unique behavior across revisions as some default to
208 * hiding bits 4-6 for compliance with PCI 2.3. The latter is done
209 * as at least revision 0xc8 requires the PCIM_CMD_PORTEN bypass
210 * to be always enabled as otherwise even enabling PCIM_CMD_PORTEN
211 * results in an instant data access trap on Fire-based machines.
212 * Thus these quirks have to be handled before pci(4) adds the maps.
213 * Note that for older revisions bit 0 of register 0x50 enables the
214 * internal IDE function instead of force enabling IDE I/O.
215 */
216 if ((CS_READ(PCIR_VENDOR, 2) == 0x10b9 &&
217 CS_READ(PCIR_DEVICE, 2) == 0x5229))
218 CS_WRITE(0x50, CS_READ(0x50, 1) | 0x3, 1);
219
220 /*
221 * The preset in the intline register is usually wrong. Reset
222 * it to 255, so that the PCI code will reroute the interrupt if
223 * needed.
224 */
225 CS_WRITE(PCIR_INTLINE, PCI_INVALID_IRQ, 1);
226
227 #undef CS_READ
228 #undef CS_WRITE
229 }
230
231 static int
232 ofw_pcibus_attach(device_t dev)
233 {
234 device_t pcib;
235 struct ofw_pci_register pcir;
236 struct ofw_pcibus_devinfo *dinfo;
237 phandle_t node, child;
238 uint32_t clock;
239 u_int busno, domain, func, slot;
240 int error;
241
242 error = pci_attach_common(dev);
243 if (error)
244 return (error);
245 pcib = device_get_parent(dev);
246 domain = pcib_get_domain(dev);
247 busno = pcib_get_bus(dev);
248 node = ofw_bus_get_node(dev);
249
250 /*
251 * Add the PCI side of the host-PCI bridge itself to the bus.
252 * Note that we exclude the host-PCIe bridges here as these
253 * have no configuration space implemented themselves.
254 */
255 if (strcmp(device_get_name(device_get_parent(pcib)), "nexus") == 0 &&
256 ofw_bus_get_type(pcib) != NULL &&
257 strcmp(ofw_bus_get_type(pcib), OFW_TYPE_PCIE) != 0 &&
258 (dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib, dev,
259 domain, busno, 0, 0)) != NULL) {
260 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, node) != 0)
261 pci_freecfg((struct pci_devinfo *)dinfo);
262 else
263 pci_add_child(dev, (struct pci_devinfo *)dinfo);
264 }
265
266 if (OF_getprop(ofw_bus_get_node(pcib), "clock-frequency", &clock,
267 sizeof(clock)) == -1)
268 clock = 33000000;
269 for (child = OF_child(node); child != 0; child = OF_peer(child)) {
270 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1)
271 continue;
272 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi);
273 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi);
274 /* Some OFW device trees contain dupes. */
275 if (pci_find_dbsf(domain, busno, slot, func) != NULL)
276 continue;
277 ofw_pcibus_setup_device(pcib, clock, busno, slot, func);
278 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib, dev,
279 domain, busno, slot, func);
280 if (dinfo == NULL)
281 continue;
282 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) !=
283 0) {
284 pci_freecfg((struct pci_devinfo *)dinfo);
285 continue;
286 }
287 pci_add_child(dev, (struct pci_devinfo *)dinfo);
288 OFW_PCI_SETUP_DEVICE(pcib, dinfo->opd_dinfo.cfg.dev);
289 }
290
291 return (bus_generic_attach(dev));
292 }
293
294 struct pci_devinfo *
295 ofw_pcibus_alloc_devinfo(device_t dev)
296 {
297 struct ofw_pcibus_devinfo *dinfo;
298
299 dinfo = malloc(sizeof(*dinfo), M_DEVBUF, M_WAITOK | M_ZERO);
300 return (&dinfo->opd_dinfo);
301 }
302
303 static int
304 ofw_pcibus_assign_interrupt(device_t dev, device_t child)
305 {
306 ofw_pci_intr_t intr;
307 int isz;
308
309 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr,
310 sizeof(intr));
311 if (isz != sizeof(intr)) {
312 /* No property; our best guess is the intpin. */
313 intr = pci_get_intpin(child);
314 #ifndef SUN4V
315 } else if (intr >= 255) {
316 /*
317 * A fully specified interrupt (including IGN), as present on
318 * SPARCengine Ultra AX and E450. Extract the INO and return
319 * it.
320 */
321 return (INTINO(intr));
322 #endif
323 }
324 /*
325 * If we got intr from a property, it may or may not be an intpin.
326 * For on-board devices, it frequently is not, and is completely out
327 * of the valid intpin range. For PCI slots, it hopefully is,
328 * otherwise we will have trouble interfacing with non-OFW buses
329 * such as cardbus.
330 * Since we cannot tell which it is without violating layering, we
331 * will always use the route_interrupt method, and treat exceptions
332 * on the level they become apparent.
333 */
334 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr));
335 }
336
337 static const struct ofw_bus_devinfo *
338 ofw_pcibus_get_devinfo(device_t bus, device_t dev)
339 {
340 struct ofw_pcibus_devinfo *dinfo;
341
342 dinfo = device_get_ivars(dev);
343 return (&dinfo->opd_obdinfo);
344 }
345
346 static void
347 ofw_pcibus_child_deleted(device_t dev, device_t child)
348 {
349 struct ofw_pcibus_devinfo *dinfo;
350
351 dinfo = device_get_ivars(dev);
352 ofw_bus_gen_destroy_devinfo(&dinfo->opd_obdinfo);
353 pci_child_deleted(dev, child);
354 }
355
356 static int
357 ofw_pcibus_pnpinfo_str(device_t dev, device_t child, char *buf,
358 size_t buflen)
359 {
360
361 pci_child_pnpinfo_str_method(dev, child, buf, buflen);
362 if (ofw_bus_get_node(child) != -1) {
363 strlcat(buf, " ", buflen); /* Separate info. */
364 ofw_bus_gen_child_pnpinfo_str(dev, child, buf, buflen);
365 }
366
367 return (0);
368 }
Cache object: 050951a16dd7c1201d66c42823971255
|