1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 1999, 2000 Matthew R. Green
5 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
6 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
27 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37
38 /*
39 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
40 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
41 */
42
43 #include "opt_ofw_pci.h"
44 #include "opt_psycho.h"
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/bus.h>
49 #include <sys/endian.h>
50 #include <sys/kdb.h>
51 #include <sys/kernel.h>
52 #include <sys/lock.h>
53 #include <sys/malloc.h>
54 #include <sys/module.h>
55 #include <sys/mutex.h>
56 #include <sys/pcpu.h>
57 #include <sys/reboot.h>
58 #include <sys/rman.h>
59 #include <sys/sysctl.h>
60
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/openfirm.h>
63
64 #include <machine/bus.h>
65 #include <machine/bus_common.h>
66 #include <machine/bus_private.h>
67 #include <machine/iommureg.h>
68 #include <machine/iommuvar.h>
69 #include <machine/resource.h>
70 #include <machine/ver.h>
71
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
74 #include <dev/pci/pcib_private.h>
75
76 #include <sparc64/pci/ofw_pci.h>
77 #include <sparc64/pci/psychoreg.h>
78 #include <sparc64/pci/psychovar.h>
79
80 #include "pcib_if.h"
81
82 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
83 const char *);
84 static const struct psycho_desc *psycho_get_desc(device_t);
85 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
86 driver_filter_t, driver_intr_t);
87 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
88 bus_addr_t *, u_long *);
89 static void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
90 bus_dmasync_op_t op);
91 static void psycho_intr_enable(void *);
92 static void psycho_intr_disable(void *);
93 static void psycho_intr_assign(void *);
94 static void psycho_intr_clear(void *);
95
96 /* Interrupt handlers */
97 static driver_filter_t psycho_ue;
98 static driver_filter_t psycho_ce;
99 static driver_filter_t psycho_pci_bus;
100 static driver_filter_t psycho_powerdebug;
101 static driver_intr_t psycho_powerdown;
102 static driver_intr_t psycho_overtemp;
103 #ifdef PSYCHO_MAP_WAKEUP
104 static driver_filter_t psycho_wakeup;
105 #endif
106
107 /* IOMMU support */
108 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
109
110 /*
111 * Methods
112 */
113 static device_probe_t psycho_probe;
114 static device_attach_t psycho_attach;
115 static bus_setup_intr_t psycho_setup_intr;
116 static bus_alloc_resource_t psycho_alloc_resource;
117 static pcib_maxslots_t psycho_maxslots;
118 static pcib_read_config_t psycho_read_config;
119 static pcib_write_config_t psycho_write_config;
120 static pcib_route_interrupt_t psycho_route_interrupt;
121 static ofw_pci_setup_device_t psycho_setup_device;
122
123 static device_method_t psycho_methods[] = {
124 /* Device interface */
125 DEVMETHOD(device_probe, psycho_probe),
126 DEVMETHOD(device_attach, psycho_attach),
127 DEVMETHOD(device_shutdown, bus_generic_shutdown),
128 DEVMETHOD(device_suspend, bus_generic_suspend),
129 DEVMETHOD(device_resume, bus_generic_resume),
130
131 /* Bus interface */
132 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
133 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
134 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
135 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
136 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
137 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
138 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
139 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
140 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
141
142 /* pcib interface */
143 DEVMETHOD(pcib_maxslots, psycho_maxslots),
144 DEVMETHOD(pcib_read_config, psycho_read_config),
145 DEVMETHOD(pcib_write_config, psycho_write_config),
146 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
147 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
148
149 /* ofw_bus interface */
150 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
151
152 /* ofw_pci interface */
153 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
154
155 DEVMETHOD_END
156 };
157
158 static devclass_t psycho_devclass;
159
160 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
161 sizeof(struct psycho_softc));
162 EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, NULL, NULL,
163 BUS_PASS_BUS);
164
165 static SYSCTL_NODE(_hw, OID_AUTO, psycho, CTLFLAG_RD, 0, "psycho parameters");
166
167 static u_int psycho_powerfail = 1;
168 SYSCTL_UINT(_hw_psycho, OID_AUTO, powerfail, CTLFLAG_RDTUN, &psycho_powerfail,
169 0, "powerfail action (0: none, 1: shutdown (default), 2: debugger)");
170
171 static SLIST_HEAD(, psycho_softc) psycho_softcs =
172 SLIST_HEAD_INITIALIZER(psycho_softcs);
173
174 static const struct intr_controller psycho_ic = {
175 psycho_intr_enable,
176 psycho_intr_disable,
177 psycho_intr_assign,
178 psycho_intr_clear
179 };
180
181 struct psycho_icarg {
182 struct psycho_softc *pica_sc;
183 bus_addr_t pica_map;
184 bus_addr_t pica_clr;
185 };
186
187 #define PSYCHO_READ8(sc, off) \
188 bus_read_8((sc)->sc_mem_res, (off))
189 #define PSYCHO_WRITE8(sc, off, v) \
190 bus_write_8((sc)->sc_mem_res, (off), (v))
191 #define PCICTL_READ8(sc, off) \
192 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
193 #define PCICTL_WRITE8(sc, off, v) \
194 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
195
196 /*
197 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
198 * single PCI bus and does not have a streaming buffer. It often has an APB
199 * (advanced PCI bridge) connected to it, which was designed specifically for
200 * the IIi. The APB lets the IIi handle two independent PCI buses, and
201 * appears as two "Simba"'s underneath the Sabre.
202 *
203 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
204 * basically the same as Sabre but without an APB underneath it.
205 *
206 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA
207 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
208 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
209 * will usually find a "Psycho+" since I don't think the original "Psycho"
210 * ever shipped, and if it did it would be in the U30.
211 *
212 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
213 * both part of the same IC, they only have a single register space. As such,
214 * they need to be configured together, even though the autoconfiguration will
215 * attach them separately.
216 *
217 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
218 * as pci1 and pci2, although they have been implemented with other PCI bus
219 * numbers on some machines.
220 *
221 * On UltraII machines, there can be any number of "Psycho+" ICs, each
222 * providing two PCI buses.
223 */
224
225 struct psycho_desc {
226 const char *pd_string;
227 int pd_mode;
228 const char *pd_name;
229 };
230
231 static const struct psycho_desc psycho_compats[] = {
232 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
233 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
234 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
235 { NULL, 0, NULL }
236 };
237
238 static const struct psycho_desc psycho_models[] = {
239 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
240 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
241 { NULL, 0, NULL }
242 };
243
244 static const struct psycho_desc *
245 psycho_find_desc(const struct psycho_desc *table, const char *string)
246 {
247 const struct psycho_desc *desc;
248
249 if (string == NULL)
250 return (NULL);
251 for (desc = table; desc->pd_string != NULL; desc++)
252 if (strcmp(desc->pd_string, string) == 0)
253 return (desc);
254 return (NULL);
255 }
256
257 static const struct psycho_desc *
258 psycho_get_desc(device_t dev)
259 {
260 const struct psycho_desc *rv;
261
262 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
263 if (rv == NULL)
264 rv = psycho_find_desc(psycho_compats,
265 ofw_bus_get_compat(dev));
266 return (rv);
267 }
268
269 static int
270 psycho_probe(device_t dev)
271 {
272 const char *dtype;
273
274 dtype = ofw_bus_get_type(dev);
275 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
276 psycho_get_desc(dev) != NULL) {
277 device_set_desc(dev, "U2P UPA-PCI bridge");
278 return (0);
279 }
280 return (ENXIO);
281 }
282
283 static int
284 psycho_attach(device_t dev)
285 {
286 struct psycho_icarg *pica;
287 struct psycho_softc *asc, *sc, *osc;
288 const struct psycho_desc *desc;
289 bus_addr_t intrclr, intrmap;
290 bus_dma_tag_t dmat;
291 uint64_t csr, dr;
292 phandle_t node;
293 uint32_t dvmabase, prop;
294 u_int rerun, ver;
295 int i, j;
296
297 node = ofw_bus_get_node(dev);
298 sc = device_get_softc(dev);
299 desc = psycho_get_desc(dev);
300
301 sc->sc_dev = dev;
302 sc->sc_mode = desc->pd_mode;
303
304 /*
305 * The Psycho gets three register banks:
306 * (0) per-PBM configuration and status registers
307 * (1) per-PBM PCI configuration space, containing only the
308 * PBM 256-byte PCI header
309 * (2) the shared Psycho configuration registers
310 */
311 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
312 i = 2;
313 sc->sc_pcictl =
314 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
315 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
316 switch (sc->sc_pcictl) {
317 case PSR_PCICTL0:
318 sc->sc_half = 0;
319 break;
320 case PSR_PCICTL1:
321 sc->sc_half = 1;
322 break;
323 default:
324 panic("%s: bogus PCI control register location",
325 __func__);
326 /* NOTREACHED */
327 }
328 } else {
329 i = 0;
330 sc->sc_pcictl = PSR_PCICTL0;
331 sc->sc_half = 0;
332 }
333 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
334 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
335 RF_ACTIVE);
336 if (sc->sc_mem_res == NULL)
337 panic("%s: could not allocate registers", __func__);
338
339 /*
340 * Match other Psychos that are already configured against
341 * the base physical address. This will be the same for a
342 * pair of devices that share register space.
343 */
344 osc = NULL;
345 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
346 if (rman_get_start(asc->sc_mem_res) ==
347 rman_get_start(sc->sc_mem_res)) {
348 /* Found partner. */
349 osc = asc;
350 break;
351 }
352 }
353 if (osc == NULL) {
354 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
355 M_NOWAIT | M_ZERO);
356 if (sc->sc_mtx == NULL)
357 panic("%s: could not malloc mutex", __func__);
358 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
359 } else {
360 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
361 panic("%s: no partner expected", __func__);
362 if (mtx_initialized(osc->sc_mtx) == 0)
363 panic("%s: mutex not initialized", __func__);
364 sc->sc_mtx = osc->sc_mtx;
365 }
366 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
367
368 csr = PSYCHO_READ8(sc, PSR_CS);
369 ver = PSYCHO_GCSR_VERS(csr);
370 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
371 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
372 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
373 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
374 prop = 33000000;
375
376 device_printf(dev,
377 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
378 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
379 'A' + sc->sc_half, prop / 1000 / 1000);
380
381 /* Set up the PCI control and PCI diagnostic registers. */
382
383 csr = PCICTL_READ8(sc, PCR_CS);
384 csr &= ~PCICTL_ARB_PARK;
385 if (OF_getproplen(node, "no-bus-parking") < 0)
386 csr |= PCICTL_ARB_PARK;
387
388 /* Workarounds for version specific bugs. */
389 dr = PCICTL_READ8(sc, PCR_DIAG);
390 switch (ver) {
391 case 0:
392 dr |= DIAG_RTRY_DIS;
393 dr &= ~DIAG_DWSYNC_DIS;
394 rerun = 0;
395 break;
396 case 1:
397 csr &= ~PCICTL_ARB_PARK;
398 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
399 rerun = 0;
400 break;
401 default:
402 dr |= DIAG_DWSYNC_DIS;
403 dr &= ~DIAG_RTRY_DIS;
404 rerun = 1;
405 break;
406 }
407
408 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
409 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
410 #ifdef PSYCHO_DEBUG
411 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
412 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
413 (unsigned long long)csr);
414 #endif
415 PCICTL_WRITE8(sc, PCR_CS, csr);
416
417 dr &= ~DIAG_ISYNC_DIS;
418 #ifdef PSYCHO_DEBUG
419 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
420 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
421 (unsigned long long)dr);
422 #endif
423 PCICTL_WRITE8(sc, PCR_DIAG, dr);
424
425 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
426 /* Use the PROM preset for now. */
427 csr = PCICTL_READ8(sc, PCR_TAS);
428 if (csr == 0)
429 panic("%s: Hummingbird/Sabre TAS not initialized.",
430 __func__);
431 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
432 } else
433 dvmabase = -1;
434
435 /*
436 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
437 * to arrive here, do the interrupt setup and start up the IOMMU.
438 */
439 if (osc == NULL) {
440 /*
441 * Hunt through all the interrupt mapping regs and register
442 * our interrupt controller for the corresponding interrupt
443 * vectors. We do this early in order to be able to catch
444 * stray interrupts.
445 */
446 for (i = 0; i <= PSYCHO_MAX_INO; i++) {
447 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr,
448 NULL) == 0)
449 continue;
450 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
451 if (pica == NULL)
452 panic("%s: could not allocate interrupt "
453 "controller argument", __func__);
454 pica->pica_sc = sc;
455 pica->pica_map = intrmap;
456 pica->pica_clr = intrclr;
457 #ifdef PSYCHO_DEBUG
458 /*
459 * Enable all interrupts and clear all interrupt
460 * states. This aids the debugging of interrupt
461 * routing problems.
462 */
463 device_printf(dev,
464 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
465 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
466 (u_long)intrmap, (u_long)PSYCHO_READ8(sc,
467 intrmap), (u_long)intrclr);
468 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i));
469 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE);
470 PSYCHO_WRITE8(sc, intrmap,
471 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i),
472 PCPU_GET(mid)));
473 #endif
474 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
475 i), &psycho_ic, pica);
476 if (j != 0)
477 device_printf(dev, "could not register "
478 "interrupt controller for INO %d (%d)\n",
479 i, j);
480 }
481
482 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
483 sparc64_counter_init(device_get_nameunit(dev),
484 rman_get_bustag(sc->sc_mem_res),
485 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
486
487 /*
488 * Set up IOMMU and PCI configuration if we're the first
489 * of a pair of Psychos to arrive here or a Hummingbird
490 * or Sabre.
491 *
492 * We should calculate a TSB size based on amount of RAM
493 * and number of bus controllers and number and type of
494 * child devices.
495 *
496 * For the moment, 32KB should be more than enough.
497 */
498 sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT |
499 M_ZERO);
500 if (sc->sc_is == NULL)
501 panic("%s: could not malloc IOMMU state", __func__);
502 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM;
503 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
504 sc->sc_dma_methods =
505 malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF,
506 M_NOWAIT);
507 if (sc->sc_dma_methods == NULL)
508 panic("%s: could not malloc DMA methods",
509 __func__);
510 memcpy(sc->sc_dma_methods, &iommu_dma_methods,
511 sizeof(*sc->sc_dma_methods));
512 sc->sc_dma_methods->dm_dmamap_sync =
513 sabre_dmamap_sync;
514 sc->sc_is->is_pmaxaddr =
515 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
516 } else {
517 sc->sc_dma_methods = &iommu_dma_methods;
518 sc->sc_is->is_pmaxaddr =
519 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
520 }
521 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
522 if (OF_getproplen(node, "no-streaming-cache") < 0)
523 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
524 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
525 psycho_iommu_init(sc, 3, dvmabase);
526 } else {
527 /* Just copy IOMMU state, config tag and address. */
528 sc->sc_dma_methods = &iommu_dma_methods;
529 sc->sc_is = osc->sc_is;
530 if (OF_getproplen(node, "no-streaming-cache") < 0)
531 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
532 iommu_reset(sc->sc_is);
533 }
534
535 /* Create our DMA tag. */
536 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
537 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
538 0xff, 0xffffffff, 0, NULL, NULL, &dmat) != 0)
539 panic("%s: could not create PCI DMA tag", __func__);
540 dmat->dt_cookie = sc->sc_is;
541 dmat->dt_mt = sc->sc_dma_methods;
542
543 if (ofw_pci_attach_common(dev, dmat, PSYCHO_IO_SIZE,
544 PSYCHO_MEM_SIZE) != 0)
545 panic("%s: ofw_pci_attach_common() failed", __func__);
546
547 /* Clear any pending PCI error bits. */
548 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
549 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_ops.sc_pci_secbus,
550 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
551 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
552 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
553
554 if (osc == NULL) {
555 /*
556 * Establish handlers for interesting interrupts...
557 *
558 * XXX We need to remember these and remove this to support
559 * hotplug on the UPA/FHC bus.
560 *
561 * XXX Not all controllers have these, but installing them
562 * is better than trying to sort through this mess.
563 */
564 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
565 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
566 switch (psycho_powerfail) {
567 case 0:
568 break;
569 case 2:
570 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP,
571 psycho_powerdebug, NULL);
572 break;
573 default:
574 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
575 psycho_powerdown);
576 break;
577 }
578 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
579 /*
580 * Hummingbirds/Sabres do not have the following two
581 * interrupts.
582 */
583
584 /*
585 * The spare hardware interrupt is used for the
586 * over-temperature interrupt.
587 */
588 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, NULL,
589 psycho_overtemp);
590 #ifdef PSYCHO_MAP_WAKEUP
591 /*
592 * psycho_wakeup() doesn't do anything useful right
593 * now.
594 */
595 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
596 psycho_wakeup, NULL);
597 #endif /* PSYCHO_MAP_WAKEUP */
598 }
599 }
600 /*
601 * Register a PCI bus error interrupt handler according to which
602 * half this is. Hummingbird/Sabre don't have a PCI bus B error
603 * interrupt but they are also only used for PCI bus A.
604 */
605 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
606 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
607
608 /*
609 * Set the latency timer register as this isn't always done by the
610 * firmware.
611 */
612 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
613 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
614
615 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
616 le16enc(&sc->sc_pci_hpbcfg[i],
617 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
618 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
619 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, PCS_DEVICE,
620 PCS_FUNC, i)));
621 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
622 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_ops.sc_pci_cfgt,
623 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
624 sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
625
626 /*
627 * On E250 the interrupt map entry for the EBus bridge is wrong,
628 * causing incorrect interrupts to be assigned to some devices on
629 * the EBus. Work around it by changing our copy of the interrupt
630 * map mask to perform a full comparison of the INO. That way
631 * the interrupt map entry for the EBus bridge won't match at all
632 * and the INOs specified in the "interrupts" properties of the
633 * EBus devices will be used directly instead.
634 */
635 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
636 sc->sc_ops.sc_pci_iinfo.opi_imapmsk != NULL)
637 *(ofw_pci_intr_t *)(&sc->sc_ops.sc_pci_iinfo.opi_imapmsk[
638 sc->sc_ops.sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
639
640 device_add_child(dev, "pci", -1);
641 return (bus_generic_attach(dev));
642 }
643
644 static void
645 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
646 driver_filter_t filt, driver_intr_t intr)
647 {
648 u_long vec;
649 int rid;
650
651 rid = index;
652 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
653 SYS_RES_IRQ, &rid, RF_ACTIVE);
654 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
655 /*
656 * These interrupts aren't mandatory and not available
657 * with all controllers (not even Psychos).
658 */
659 return;
660 }
661 if (sc->sc_irq_res[index] == NULL ||
662 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) !=
663 sc->sc_ign ||
664 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
665 intr_vectors[vec].iv_ic != &psycho_ic ||
666 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
667 INTR_TYPE_MISC | INTR_BRIDGE | INTR_MPSAFE, filt, intr, sc,
668 &sc->sc_ihand[index]) != 0)
669 panic("%s: failed to set up interrupt %d", __func__, index);
670 }
671
672 static int
673 psycho_find_intrmap(struct psycho_softc *sc, u_int ino,
674 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
675 {
676 bus_addr_t intrclr, intrmap;
677 uint64_t diag;
678 int found;
679
680 /*
681 * XXX we only compare INOs rather than INRs since the firmware may
682 * not provide the IGN and the IGN is constant for all devices on
683 * that PCI controller.
684 * This could cause problems for the FFB/external interrupt which
685 * has a full vector that can be set arbitrarily.
686 */
687
688 if (ino > PSYCHO_MAX_INO) {
689 device_printf(sc->sc_dev, "out of range INO %d requested\n",
690 ino);
691 return (0);
692 }
693
694 found = 0;
695 /* Hunt through OBIO first. */
696 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
697 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
698 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
699 diag >>= 2) {
700 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
701 (intrmap == PSR_TIMER0_INT_MAP ||
702 intrmap == PSR_TIMER1_INT_MAP ||
703 intrmap == PSR_PCIBERR_INT_MAP ||
704 intrmap == PSR_PWRMGT_INT_MAP))
705 continue;
706 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
707 diag &= 2;
708 found = 1;
709 break;
710 }
711 }
712
713 if (!found) {
714 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
715 /* Now do PCI interrupts. */
716 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
717 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
718 diag >>= 8) {
719 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
720 (intrmap == PSR_PCIA2_INT_MAP ||
721 intrmap == PSR_PCIA3_INT_MAP))
722 continue;
723 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
724 intrclr += 8 * (ino & 3);
725 diag = (diag >> ((ino & 3) * 2)) & 2;
726 found = 1;
727 break;
728 }
729 }
730 }
731 if (intrmapptr != NULL)
732 *intrmapptr = intrmap;
733 if (intrclrptr != NULL)
734 *intrclrptr = intrclr;
735 if (intrdiagptr != NULL)
736 *intrdiagptr = diag;
737 return (found);
738 }
739
740 /*
741 * Interrupt handlers
742 */
743 static int
744 psycho_ue(void *arg)
745 {
746 struct psycho_softc *sc = arg;
747 uint64_t afar, afsr;
748
749 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
750 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
751 /*
752 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
753 * the AFAR to be set to the physical address of the TTE entry that
754 * was invalid/write protected. Call into the IOMMU code to have
755 * them decoded to virtual I/O addresses.
756 */
757 if ((afsr & UEAFSR_P_DTE) != 0)
758 iommu_decode_fault(sc->sc_is, afar);
759 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
760 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr);
761 return (FILTER_HANDLED);
762 }
763
764 static int
765 psycho_ce(void *arg)
766 {
767 struct psycho_softc *sc = arg;
768 uint64_t afar, afsr;
769
770 mtx_lock_spin(sc->sc_mtx);
771 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
772 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
773 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
774 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
775 /* Clear the error bits that we caught. */
776 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
777 mtx_unlock_spin(sc->sc_mtx);
778 return (FILTER_HANDLED);
779 }
780
781 static int
782 psycho_pci_bus(void *arg)
783 {
784 struct psycho_softc *sc = arg;
785 uint64_t afar, afsr;
786
787 afar = PCICTL_READ8(sc, PCR_AFA);
788 afsr = PCICTL_READ8(sc, PCR_AFS);
789 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
790 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
791 (u_long)afsr);
792 return (FILTER_HANDLED);
793 }
794
795 static int
796 psycho_powerdebug(void *arg __unused)
797 {
798
799 kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
800 return (FILTER_HANDLED);
801 }
802
803 static void
804 psycho_powerdown(void *arg __unused)
805 {
806 static int shutdown;
807
808 /* As the interrupt is cleared we may be called multiple times. */
809 if (shutdown != 0)
810 return;
811 shutdown++;
812 printf("Power Failure Detected: Shutting down NOW.\n");
813 shutdown_nice(RB_POWEROFF);
814 }
815
816 static void
817 psycho_overtemp(void *arg __unused)
818 {
819 static int shutdown;
820
821 /* As the interrupt is cleared we may be called multiple times. */
822 if (shutdown != 0)
823 return;
824 shutdown++;
825 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
826 shutdown_nice(RB_POWEROFF);
827 }
828
829 #ifdef PSYCHO_MAP_WAKEUP
830 static int
831 psycho_wakeup(void *arg)
832 {
833 struct psycho_softc *sc = arg;
834
835 /* We don't really have a framework to deal with this properly. */
836 device_printf(sc->sc_dev, "power management wakeup\n");
837 return (FILTER_HANDLED);
838 }
839 #endif /* PSYCHO_MAP_WAKEUP */
840
841 static void
842 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
843 {
844 struct iommu_state *is = sc->sc_is;
845
846 /* Punch in our copies. */
847 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
848 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
849 is->is_iommu = PSR_IOMMU;
850 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
851 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
852 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
853 is->is_dva = PSR_IOMMU_SVADIAG;
854 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
855
856 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
857 }
858
859 static int
860 psycho_maxslots(device_t dev)
861 {
862
863 /* XXX: is this correct? */
864 return (PCI_SLOTMAX);
865 }
866
867 static uint32_t
868 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
869 int width)
870 {
871 struct psycho_softc *sc;
872
873 sc = device_get_softc(dev);
874 /*
875 * The Hummingbird and Sabre bridges are picky in that they
876 * only allow their config space to be accessed using the
877 * "native" width of the respective register being accessed
878 * and return semi-random other content of their config space
879 * otherwise. Given that the PCI specs don't say anything
880 * about such a (unusual) limitation and lots of stuff expects
881 * to be able to access the contents of the config space at
882 * any width we allow just that. We do this by using a copy
883 * of the header of the bridge (the rest is all zero anyway)
884 * read during attach (expect for PCIR_STATUS) in order to
885 * simplify things.
886 * The Psycho bridges contain a dupe of their header at 0x80
887 * which we nullify that way also.
888 */
889 if (bus == sc->sc_ops.sc_pci_secbus && slot == PCS_DEVICE &&
890 func == PCS_FUNC) {
891 if (reg % width != 0)
892 return (-1);
893
894 if (reg >= sizeof(sc->sc_pci_hpbcfg))
895 return (0);
896
897 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
898 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
899 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
900 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
901 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
902 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus,
903 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
904
905 switch (width) {
906 case 1:
907 return (sc->sc_pci_hpbcfg[reg]);
908 case 2:
909 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
910 case 4:
911 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
912 }
913 }
914
915 return (ofw_pci_read_config_common(dev, PCI_REGMAX,
916 PSYCHO_CONF_OFF(bus, slot, func, reg), bus, slot, func, reg,
917 width));
918 }
919
920 static void
921 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
922 u_int reg, uint32_t val, int width)
923 {
924
925 ofw_pci_write_config_common(dev, PCI_REGMAX, PSYCHO_CONF_OFF(bus,
926 slot, func, reg), bus, slot, func, reg, val, width);
927 }
928
929 static int
930 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
931 {
932 struct psycho_softc *sc;
933 bus_addr_t intrmap;
934 ofw_pci_intr_t mintr;
935
936 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
937 if (PCI_INTERRUPT_VALID(mintr))
938 return (mintr);
939 /*
940 * If this is outside of the range for an intpin, it's likely a full
941 * INO, and no mapping is required at all; this happens on the U30,
942 * where there's no interrupt map at the Psycho node. Fortunately,
943 * there seem to be no INOs in the intpin range on this boxen, so
944 * this easy heuristics will do.
945 */
946 if (pin > 4)
947 return (pin);
948 /*
949 * Guess the INO; we always assume that this is a non-OBIO device,
950 * and that pin is a "real" intpin number. Determine the mapping
951 * register to be used by the slot number.
952 * We only need to do this on E450s and U30s, though; here, the
953 * slot numbers for bus A are one-based, while those for bus B
954 * seemingly have an offset of 2 (hence the factor of 3 below).
955 */
956 sc = device_get_softc(bridge);
957 intrmap = PSR_PCIA0_INT_MAP +
958 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
959 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
960 device_printf(bridge,
961 "guessing interrupt %d for device %d.%d pin %d\n",
962 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
963 return (mintr);
964 }
965
966 static void
967 sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
968 {
969 struct iommu_state *is = dt->dt_cookie;
970
971 if ((map->dm_flags & DMF_LOADED) == 0)
972 return;
973
974 if ((op & BUS_DMASYNC_POSTREAD) != 0)
975 (void)bus_space_read_8(is->is_bustag, is->is_bushandle,
976 PSR_DMA_WRITE_SYNC);
977
978 if ((op & BUS_DMASYNC_PREWRITE) != 0)
979 membar(Sync);
980 }
981
982 static void
983 psycho_intr_enable(void *arg)
984 {
985 struct intr_vector *iv = arg;
986 struct psycho_icarg *pica = iv->iv_icarg;
987
988 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
989 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
990 }
991
992 static void
993 psycho_intr_disable(void *arg)
994 {
995 struct intr_vector *iv = arg;
996 struct psycho_icarg *pica = iv->iv_icarg;
997
998 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
999 }
1000
1001 static void
1002 psycho_intr_assign(void *arg)
1003 {
1004 struct intr_vector *iv = arg;
1005 struct psycho_icarg *pica = iv->iv_icarg;
1006
1007 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1008 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1009 }
1010
1011 static void
1012 psycho_intr_clear(void *arg)
1013 {
1014 struct intr_vector *iv = arg;
1015 struct psycho_icarg *pica = iv->iv_icarg;
1016
1017 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE);
1018 }
1019
1020 static int
1021 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1022 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1023 void **cookiep)
1024 {
1025 struct psycho_softc *sc;
1026 u_long vec;
1027
1028 sc = device_get_softc(dev);
1029 /*
1030 * Make sure the vector is fully specified and we registered
1031 * our interrupt controller for it.
1032 */
1033 vec = rman_get_start(ires);
1034 if (INTIGN(vec) != sc->sc_ign ||
1035 intr_vectors[vec].iv_ic != &psycho_ic) {
1036 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1037 return (EINVAL);
1038 }
1039 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1040 arg, cookiep));
1041 }
1042
1043 static struct resource *
1044 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1045 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
1046 {
1047 struct psycho_softc *sc;
1048
1049 if (type == SYS_RES_IRQ) {
1050 sc = device_get_softc(bus);
1051 start = end = INTMAP_VEC(sc->sc_ign, end);
1052 }
1053 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
1054 count, flags));
1055 }
1056
1057 static void
1058 psycho_setup_device(device_t bus, device_t child)
1059 {
1060 struct psycho_softc *sc;
1061 uint32_t rev;
1062
1063 sc = device_get_softc(bus);
1064 /*
1065 * Revision 0 EBus bridges have a bug which prevents them from
1066 * working when bus parking is enabled.
1067 */
1068 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 ||
1069 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) &&
1070 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev,
1071 sizeof(rev)) > 0 && rev == 0)
1072 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) &
1073 ~PCICTL_ARB_PARK);
1074 }
Cache object: ec5548bae38a95c61c66bb2e49261adc
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