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sys/sparc64/pci/psycho.c
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1 /*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/8.0/sys/sparc64/pci/psycho.c 190109 2009-03-19 20:52:46Z marius $"); 35 36 /* 37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+' 38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges. 39 */ 40 41 #include "opt_ofw_pci.h" 42 #include "opt_psycho.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/endian.h> 48 #include <sys/kdb.h> 49 #include <sys/kernel.h> 50 #include <sys/lock.h> 51 #include <sys/malloc.h> 52 #include <sys/module.h> 53 #include <sys/mutex.h> 54 #include <sys/pcpu.h> 55 #include <sys/reboot.h> 56 #include <sys/rman.h> 57 58 #include <dev/ofw/ofw_bus.h> 59 #include <dev/ofw/ofw_pci.h> 60 #include <dev/ofw/openfirm.h> 61 62 #include <machine/bus.h> 63 #include <machine/bus_common.h> 64 #include <machine/bus_private.h> 65 #include <machine/iommureg.h> 66 #include <machine/iommuvar.h> 67 #include <machine/resource.h> 68 #include <machine/ver.h> 69 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcivar.h> 72 73 #include <sparc64/pci/ofw_pci.h> 74 #include <sparc64/pci/psychoreg.h> 75 #include <sparc64/pci/psychovar.h> 76 77 #include "pcib_if.h" 78 79 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *, 80 const char *); 81 static const struct psycho_desc *psycho_get_desc(device_t); 82 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t, 83 driver_filter_t, driver_intr_t); 84 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *, 85 bus_addr_t *, u_long *); 86 static driver_filter_t psycho_dma_sync_stub; 87 static void psycho_intr_enable(void *); 88 static void psycho_intr_disable(void *); 89 static void psycho_intr_assign(void *); 90 static void psycho_intr_clear(void *); 91 static bus_space_tag_t psycho_alloc_bus_tag(struct psycho_softc *, int); 92 93 /* Interrupt handlers */ 94 static driver_filter_t psycho_ue; 95 static driver_filter_t psycho_ce; 96 static driver_filter_t psycho_pci_bus; 97 static driver_filter_t psycho_powerfail; 98 static driver_intr_t psycho_overtemp; 99 #ifdef PSYCHO_MAP_WAKEUP 100 static driver_filter_t psycho_wakeup; 101 #endif 102 103 /* IOMMU support */ 104 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t); 105 106 /* 107 * Methods 108 */ 109 static device_probe_t psycho_probe; 110 static device_attach_t psycho_attach; 111 static bus_read_ivar_t psycho_read_ivar; 112 static bus_setup_intr_t psycho_setup_intr; 113 static bus_teardown_intr_t psycho_teardown_intr; 114 static bus_alloc_resource_t psycho_alloc_resource; 115 static bus_activate_resource_t psycho_activate_resource; 116 static bus_deactivate_resource_t psycho_deactivate_resource; 117 static bus_release_resource_t psycho_release_resource; 118 static bus_get_dma_tag_t psycho_get_dma_tag; 119 static pcib_maxslots_t psycho_maxslots; 120 static pcib_read_config_t psycho_read_config; 121 static pcib_write_config_t psycho_write_config; 122 static pcib_route_interrupt_t psycho_route_interrupt; 123 static ofw_bus_get_node_t psycho_get_node; 124 125 static device_method_t psycho_methods[] = { 126 /* Device interface */ 127 DEVMETHOD(device_probe, psycho_probe), 128 DEVMETHOD(device_attach, psycho_attach), 129 DEVMETHOD(device_shutdown, bus_generic_shutdown), 130 DEVMETHOD(device_suspend, bus_generic_suspend), 131 DEVMETHOD(device_resume, bus_generic_resume), 132 133 /* Bus interface */ 134 DEVMETHOD(bus_print_child, bus_generic_print_child), 135 DEVMETHOD(bus_read_ivar, psycho_read_ivar), 136 DEVMETHOD(bus_setup_intr, psycho_setup_intr), 137 DEVMETHOD(bus_teardown_intr, psycho_teardown_intr), 138 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource), 139 DEVMETHOD(bus_activate_resource, psycho_activate_resource), 140 DEVMETHOD(bus_deactivate_resource, psycho_deactivate_resource), 141 DEVMETHOD(bus_release_resource, psycho_release_resource), 142 DEVMETHOD(bus_get_dma_tag, psycho_get_dma_tag), 143 144 /* pcib interface */ 145 DEVMETHOD(pcib_maxslots, psycho_maxslots), 146 DEVMETHOD(pcib_read_config, psycho_read_config), 147 DEVMETHOD(pcib_write_config, psycho_write_config), 148 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt), 149 150 /* ofw_bus interface */ 151 DEVMETHOD(ofw_bus_get_node, psycho_get_node), 152 153 KOBJMETHOD_END 154 }; 155 156 static devclass_t psycho_devclass; 157 158 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods, 159 sizeof(struct psycho_softc)); 160 DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, 0, 0); 161 162 static SLIST_HEAD(, psycho_softc) psycho_softcs = 163 SLIST_HEAD_INITIALIZER(psycho_softcs); 164 165 static const struct intr_controller psycho_ic = { 166 psycho_intr_enable, 167 psycho_intr_disable, 168 psycho_intr_assign, 169 psycho_intr_clear 170 }; 171 172 struct psycho_icarg { 173 struct psycho_softc *pica_sc; 174 bus_addr_t pica_map; 175 bus_addr_t pica_clr; 176 }; 177 178 struct psycho_dma_sync { 179 struct psycho_softc *pds_sc; 180 driver_filter_t *pds_handler; /* handler to call */ 181 void *pds_arg; /* argument for the handler */ 182 void *pds_cookie; /* parent bus int. cookie */ 183 device_t pds_ppb; /* farest PCI-PCI bridge */ 184 uint8_t pds_bus; /* bus of farest PCI device */ 185 uint8_t pds_slot; /* slot of farest PCI device */ 186 uint8_t pds_func; /* func. of farest PCI device */ 187 }; 188 189 #define PSYCHO_READ8(sc, off) \ 190 bus_read_8((sc)->sc_mem_res, (off)) 191 #define PSYCHO_WRITE8(sc, off, v) \ 192 bus_write_8((sc)->sc_mem_res, (off), (v)) 193 #define PCICTL_READ8(sc, off) \ 194 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off)) 195 #define PCICTL_WRITE8(sc, off, v) \ 196 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v)) 197 198 /* 199 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a 200 * single PCI bus and does not have a streaming buffer. It often has an APB 201 * (advanced PCI bridge) connected to it, which was designed specifically for 202 * the IIi. The APB let's the IIi handle two independednt PCI buses, and 203 * appears as two "Simba"'s underneath the Sabre. 204 * 205 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's 206 * basically the same as Sabre but without an APB underneath it. 207 * 208 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA bus 209 * and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while 210 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You 211 * will usually find a "Psycho+" since I don't think the original "Psycho" 212 * ever shipped, and if it did it would be in the U30. 213 * 214 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are 215 * both part of the same IC, they only have a single register space. As such, 216 * they need to be configured together, even though the autoconfiguration will 217 * attach them separately. 218 * 219 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often 220 * as pci1 and pci2, although they have been implemented with other PCI bus 221 * numbers on some machines. 222 * 223 * On UltraII machines, there can be any number of "Psycho+" ICs, each 224 * providing two PCI buses. 225 */ 226 227 #define OFW_PCI_TYPE "pci" 228 229 struct psycho_desc { 230 const char *pd_string; 231 int pd_mode; 232 const char *pd_name; 233 }; 234 235 static const struct psycho_desc const psycho_compats[] = { 236 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" }, 237 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" }, 238 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" }, 239 { NULL, 0, NULL } 240 }; 241 242 static const struct psycho_desc const psycho_models[] = { 243 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" }, 244 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" }, 245 { NULL, 0, NULL } 246 }; 247 248 static const struct psycho_desc * 249 psycho_find_desc(const struct psycho_desc *table, const char *string) 250 { 251 const struct psycho_desc *desc; 252 253 if (string == NULL) 254 return (NULL); 255 for (desc = table; desc->pd_string != NULL; desc++) 256 if (strcmp(desc->pd_string, string) == 0) 257 return (desc); 258 return (NULL); 259 } 260 261 static const struct psycho_desc * 262 psycho_get_desc(device_t dev) 263 { 264 const struct psycho_desc *rv; 265 266 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev)); 267 if (rv == NULL) 268 rv = psycho_find_desc(psycho_compats, ofw_bus_get_compat(dev)); 269 return (rv); 270 } 271 272 static int 273 psycho_probe(device_t dev) 274 { 275 const char *dtype; 276 277 dtype = ofw_bus_get_type(dev); 278 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 && 279 psycho_get_desc(dev) != NULL) { 280 device_set_desc(dev, "U2P UPA-PCI bridge"); 281 return (0); 282 } 283 return (ENXIO); 284 } 285 286 static int 287 psycho_attach(device_t dev) 288 { 289 char name[sizeof("pci108e,1000")]; 290 struct psycho_icarg *pica; 291 struct psycho_softc *asc, *sc, *osc; 292 struct ofw_pci_ranges *range; 293 const struct psycho_desc *desc; 294 bus_addr_t intrclr, intrmap; 295 uint64_t csr, dr; 296 phandle_t child, node; 297 uint32_t dvmabase, prop, prop_array[2]; 298 int32_t rev; 299 u_int rerun, ver; 300 int i, n; 301 302 node = ofw_bus_get_node(dev); 303 sc = device_get_softc(dev); 304 desc = psycho_get_desc(dev); 305 306 sc->sc_node = node; 307 sc->sc_dev = dev; 308 sc->sc_mode = desc->pd_mode; 309 310 /* 311 * The Psycho gets three register banks: 312 * (0) per-PBM configuration and status registers 313 * (1) per-PBM PCI configuration space, containing only the 314 * PBM 256-byte PCI header 315 * (2) the shared Psycho configuration registers 316 */ 317 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 318 i = 2; 319 sc->sc_pcictl = 320 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) - 321 bus_get_resource_start(dev, SYS_RES_MEMORY, 2); 322 switch (sc->sc_pcictl) { 323 case PSR_PCICTL0: 324 sc->sc_half = 0; 325 break; 326 case PSR_PCICTL1: 327 sc->sc_half = 1; 328 break; 329 default: 330 panic("%s: bogus PCI control register location", 331 __func__); 332 /* NOTREACHED */ 333 } 334 } else { 335 i = 0; 336 sc->sc_pcictl = PSR_PCICTL0; 337 sc->sc_half = 0; 338 } 339 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i, 340 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) | 341 RF_ACTIVE); 342 if (sc->sc_mem_res == NULL) 343 panic("%s: could not allocate registers", __func__); 344 345 /* 346 * Match other Psychos that are already configured against 347 * the base physical address. This will be the same for a 348 * pair of devices that share register space. 349 */ 350 osc = NULL; 351 SLIST_FOREACH(asc, &psycho_softcs, sc_link) { 352 if (rman_get_start(asc->sc_mem_res) == 353 rman_get_start(sc->sc_mem_res)) { 354 /* Found partner. */ 355 osc = asc; 356 break; 357 } 358 } 359 if (osc == NULL) { 360 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 361 M_NOWAIT | M_ZERO); 362 if (sc->sc_mtx == NULL) 363 panic("%s: could not malloc mutex", __func__); 364 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 365 } else { 366 if (sc->sc_mode != PSYCHO_MODE_PSYCHO) 367 panic("%s: no partner expected", __func__); 368 if (mtx_initialized(osc->sc_mtx) == 0) 369 panic("%s: mutex not initialized", __func__); 370 sc->sc_mtx = osc->sc_mtx; 371 } 372 373 csr = PSYCHO_READ8(sc, PSR_CS); 374 ver = PSYCHO_GCSR_VERS(csr); 375 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */ 376 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 377 sc->sc_ign = PSYCHO_GCSR_IGN(csr); 378 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 379 prop = 33000000; 380 381 device_printf(dev, 382 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n", 383 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign, 384 'A' + sc->sc_half, prop / 1000 / 1000); 385 386 /* Set up the PCI control and PCI diagnostic registers. */ 387 388 /* 389 * Revision 0 EBus bridges have a bug which prevents them from 390 * working when bus parking is enabled. 391 */ 392 rev = -1; 393 csr = PCICTL_READ8(sc, PCR_CS); 394 csr &= ~PCICTL_ARB_PARK; 395 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 396 if (OF_getprop(child, "name", name, sizeof(name)) == -1) 397 continue; 398 if ((strcmp(name, "ebus") == 0 || 399 strcmp(name, "pci108e,1000") == 0) && 400 OF_getprop(child, "revision-id", &rev, sizeof(rev)) > 0 && 401 rev == 0) 402 break; 403 } 404 if (rev != 0 && OF_getproplen(node, "no-bus-parking") < 0) 405 csr |= PCICTL_ARB_PARK; 406 407 /* Workarounds for version specific bugs. */ 408 dr = PCICTL_READ8(sc, PCR_DIAG); 409 switch (ver) { 410 case 0: 411 dr |= DIAG_RTRY_DIS; 412 dr &= ~DIAG_DWSYNC_DIS; 413 rerun = 0; 414 break; 415 case 1: 416 csr &= ~PCICTL_ARB_PARK; 417 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS; 418 rerun = 0; 419 break; 420 default: 421 dr |= DIAG_DWSYNC_DIS; 422 dr &= ~DIAG_RTRY_DIS; 423 rerun = 1; 424 break; 425 } 426 427 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4; 428 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN); 429 #ifdef PSYCHO_DEBUG 430 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n", 431 (unsigned long long)PCICTL_READ8(sc, PCR_CS), 432 (unsigned long long)csr); 433 #endif 434 PCICTL_WRITE8(sc, PCR_CS, csr); 435 436 dr &= ~DIAG_ISYNC_DIS; 437 #ifdef PSYCHO_DEBUG 438 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n", 439 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG), 440 (unsigned long long)dr); 441 #endif 442 PCICTL_WRITE8(sc, PCR_DIAG, dr); 443 444 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 445 /* Use the PROM preset for now. */ 446 csr = PCICTL_READ8(sc, PCR_TAS); 447 if (csr == 0) 448 panic("%s: Hummingbird/Sabre TAS not initialized.", 449 __func__); 450 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT; 451 } else 452 dvmabase = -1; 453 454 /* Initialize memory and I/O rmans. */ 455 sc->sc_pci_io_rman.rm_type = RMAN_ARRAY; 456 sc->sc_pci_io_rman.rm_descr = "Psycho PCI I/O Ports"; 457 if (rman_init(&sc->sc_pci_io_rman) != 0 || 458 rman_manage_region(&sc->sc_pci_io_rman, 0, PSYCHO_IO_SIZE) != 0) 459 panic("%s: failed to set up I/O rman", __func__); 460 sc->sc_pci_mem_rman.rm_type = RMAN_ARRAY; 461 sc->sc_pci_mem_rman.rm_descr = "Psycho PCI Memory"; 462 if (rman_init(&sc->sc_pci_mem_rman) != 0 || 463 rman_manage_region(&sc->sc_pci_mem_rman, 0, PSYCHO_MEM_SIZE) != 0) 464 panic("%s: failed to set up memory rman", __func__); 465 466 n = OF_getprop_alloc(node, "ranges", sizeof(*range), (void **)&range); 467 /* 468 * Make sure that the expected ranges are present. The 469 * OFW_PCI_CS_MEM64 one is not currently used though. 470 */ 471 if (n != PSYCHO_NRANGE) 472 panic("%s: unsupported number of ranges", __func__); 473 /* 474 * Find the addresses of the various bus spaces. 475 * There should not be multiple ones of one kind. 476 * The physical start addresses of the ranges are the configuration, 477 * memory and I/O handles. 478 */ 479 for (n = 0; n < PSYCHO_NRANGE; n++) { 480 i = OFW_PCI_RANGE_CS(&range[n]); 481 if (sc->sc_pci_bh[i] != 0) 482 panic("%s: duplicate range for space %d", __func__, i); 483 sc->sc_pci_bh[i] = OFW_PCI_RANGE_PHYS(&range[n]); 484 } 485 free(range, M_OFWPROP); 486 487 /* Register the softc, this is needed for paired Psychos. */ 488 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link); 489 490 /* 491 * If we're a Hummingbird/Sabre or the first of a pair of Psychos 492 * to arrive here, do the interrupt setup and start up the IOMMU. 493 */ 494 if (osc == NULL) { 495 /* 496 * Hunt through all the interrupt mapping regs and register 497 * our interrupt controller for the corresponding interrupt 498 * vectors. We do this early in order to be able to catch 499 * stray interrupts. 500 */ 501 for (n = 0; n <= PSYCHO_MAX_INO; n++) { 502 if (psycho_find_intrmap(sc, n, &intrmap, &intrclr, 503 NULL) == 0) 504 continue; 505 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT); 506 if (pica == NULL) 507 panic("%s: could not allocate interrupt " 508 "controller argument", __func__); 509 pica->pica_sc = sc; 510 pica->pica_map = intrmap; 511 pica->pica_clr = intrclr; 512 #ifdef PSYCHO_DEBUG 513 /* 514 * Enable all interrupts and clear all interrupt 515 * states. This aids the debugging of interrupt 516 * routing problems. 517 */ 518 device_printf(dev, 519 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n", 520 n, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO", 521 (u_long)intrmap, (u_long)PSYCHO_READ8(sc, intrmap), 522 (u_long)intrclr); 523 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, n)); 524 PSYCHO_WRITE8(sc, intrclr, 0); 525 PSYCHO_WRITE8(sc, intrmap, 526 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, n), 527 PCPU_GET(mid))); 528 #endif 529 i = intr_controller_register(INTMAP_VEC(sc->sc_ign, n), 530 &psycho_ic, pica); 531 if (i != 0) 532 device_printf(dev, "could not register " 533 "interrupt controller for INO %d (%d)\n", 534 n, i); 535 } 536 537 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) 538 sparc64_counter_init(device_get_nameunit(dev), 539 rman_get_bustag(sc->sc_mem_res), 540 rman_get_bushandle(sc->sc_mem_res), PSR_TC0); 541 542 /* 543 * Set up IOMMU and PCI configuration if we're the first 544 * of a pair of Psychos to arrive here or a Hummingbird 545 * or Sabre. 546 * 547 * We should calculate a TSB size based on amount of RAM 548 * and number of bus controllers and number and type of 549 * child devices. 550 * 551 * For the moment, 32KB should be more than enough. 552 */ 553 sc->sc_is = malloc(sizeof(struct iommu_state), M_DEVBUF, 554 M_NOWAIT | M_ZERO); 555 if (sc->sc_is == NULL) 556 panic("%s: malloc iommu_state failed", __func__); 557 if (sc->sc_mode == PSYCHO_MODE_SABRE) 558 sc->sc_is->is_pmaxaddr = 559 IOMMU_MAXADDR(SABRE_IOMMU_BITS); 560 else 561 sc->sc_is->is_pmaxaddr = 562 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS); 563 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0; 564 if (OF_getproplen(node, "no-streaming-cache") < 0) 565 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF; 566 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0; 567 psycho_iommu_init(sc, 3, dvmabase); 568 } else { 569 /* Just copy IOMMU state, config tag and address. */ 570 sc->sc_is = osc->sc_is; 571 if (OF_getproplen(node, "no-streaming-cache") < 0) 572 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF; 573 iommu_reset(sc->sc_is); 574 } 575 576 /* Allocate our tags. */ 577 sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE); 578 sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE); 579 sc->sc_pci_cfgt = psycho_alloc_bus_tag(sc, PCI_CONFIG_BUS_SPACE); 580 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 581 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr, 582 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) 583 panic("%s: bus_dma_tag_create failed", __func__); 584 /* Customize the tag. */ 585 sc->sc_pci_dmat->dt_cookie = sc->sc_is; 586 sc->sc_pci_dmat->dt_mt = &iommu_dma_methods; 587 588 n = OF_getprop(node, "bus-range", (void *)prop_array, 589 sizeof(prop_array)); 590 if (n == -1) 591 panic("%s: could not get bus-range", __func__); 592 if (n != sizeof(prop_array)) 593 panic("%s: broken bus-range (%d)", __func__, n); 594 if (bootverbose) 595 device_printf(dev, "bus range %u to %u; PCI bus %d\n", 596 prop_array[0], prop_array[1], prop_array[0]); 597 sc->sc_pci_secbus = prop_array[0]; 598 599 /* Clear any pending PCI error bits. */ 600 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 601 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus, 602 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2); 603 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS)); 604 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS)); 605 606 if (osc == NULL) { 607 /* 608 * Establish handlers for interesting interrupts... 609 * 610 * XXX We need to remember these and remove this to support 611 * hotplug on the UPA/FHC bus. 612 * 613 * XXX Not all controllers have these, but installing them 614 * is better than trying to sort through this mess. 615 */ 616 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL); 617 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL); 618 #ifdef DEBUGGER_ON_POWERFAIL 619 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail, 620 NULL); 621 #else 622 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL, 623 (driver_intr_t *)psycho_powerfail); 624 #endif 625 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) { 626 /* 627 * Hummingbirds/Sabres do not have the following two 628 * interrupts. 629 */ 630 631 /* 632 * The spare hardware interrupt is used for the 633 * over-temperature interrupt. 634 */ 635 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, 636 NULL, psycho_overtemp); 637 #ifdef PSYCHO_MAP_WAKEUP 638 /* 639 * psycho_wakeup() doesn't do anything useful right 640 * now. 641 */ 642 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP, 643 psycho_wakeup, NULL); 644 #endif /* PSYCHO_MAP_WAKEUP */ 645 } 646 } 647 /* 648 * Register a PCI bus error interrupt handler according to which 649 * half this is. Hummingbird/Sabre don't have a PCI bus B error 650 * interrupt but they are also only used for PCI bus A. 651 */ 652 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP : 653 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL); 654 655 /* 656 * Set the latency timer register as this isn't always done by the 657 * firmware. 658 */ 659 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, 660 PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 661 662 for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t)) 663 le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2( 664 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG], 665 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE, 666 PCS_FUNC, n))); 667 for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t)) 668 sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt, 669 sc->sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF( 670 sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, n)); 671 672 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t)); 673 /* 674 * On E250 the interrupt map entry for the EBus bridge is wrong, 675 * causing incorrect interrupts to be assigned to some devices on 676 * the EBus. Work around it by changing our copy of the interrupt 677 * map mask to perform a full comparison of the INO. That way 678 * the interrupt map entry for the EBus bridge won't match at all 679 * and the INOs specified in the "interrupts" properties of the 680 * EBus devices will be used directly instead. 681 */ 682 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 && 683 sc->sc_pci_iinfo.opi_imapmsk != NULL) 684 *(ofw_pci_intr_t *)(&sc->sc_pci_iinfo.opi_imapmsk[ 685 sc->sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK; 686 687 device_add_child(dev, "pci", -1); 688 return (bus_generic_attach(dev)); 689 } 690 691 static void 692 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap, 693 driver_filter_t filt, driver_intr_t intr) 694 { 695 u_long vec; 696 int rid; 697 698 rid = index; 699 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, SYS_RES_IRQ, 700 &rid, RF_ACTIVE); 701 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) { 702 /* 703 * These interrupts aren't mandatory and not available 704 * with all controllers (not even Psychos). 705 */ 706 return; 707 } 708 if (sc->sc_irq_res[index] == NULL || 709 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) != sc->sc_ign || 710 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec || 711 intr_vectors[vec].iv_ic != &psycho_ic || 712 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 713 INTR_TYPE_MISC | INTR_FAST, filt, intr, sc, 714 &sc->sc_ihand[index]) != 0) 715 panic("%s: failed to set up interrupt %d", __func__, index); 716 } 717 718 static int 719 psycho_find_intrmap(struct psycho_softc *sc, u_int ino, bus_addr_t *intrmapptr, 720 bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr) 721 { 722 bus_addr_t intrclr, intrmap; 723 uint64_t diag; 724 int found; 725 726 /* 727 * XXX we only compare INOs rather than INRs since the firmware may 728 * not provide the IGN and the IGN is constant for all devices on 729 * that PCI controller. 730 * This could cause problems for the FFB/external interrupt which 731 * has a full vector that can be set arbitrarily. 732 */ 733 734 if (ino > PSYCHO_MAX_INO) { 735 device_printf(sc->sc_dev, "out of range INO %d requested\n", 736 ino); 737 return (0); 738 } 739 740 found = 0; 741 /* Hunt through OBIO first. */ 742 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG); 743 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR; 744 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8, 745 diag >>= 2) { 746 if (sc->sc_mode == PSYCHO_MODE_SABRE && 747 (intrmap == PSR_TIMER0_INT_MAP || 748 intrmap == PSR_TIMER1_INT_MAP || 749 intrmap == PSR_PCIBERR_INT_MAP || 750 intrmap == PSR_PWRMGT_INT_MAP)) 751 continue; 752 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) { 753 diag &= 2; 754 found = 1; 755 break; 756 } 757 } 758 759 if (!found) { 760 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG); 761 /* Now do PCI interrupts. */ 762 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR; 763 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32, 764 diag >>= 8) { 765 if (sc->sc_mode == PSYCHO_MODE_PSYCHO && 766 (intrmap == PSR_PCIA2_INT_MAP || 767 intrmap == PSR_PCIA3_INT_MAP)) 768 continue; 769 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) { 770 intrclr += 8 * (ino & 3); 771 diag = (diag >> ((ino & 3) * 2)) & 2; 772 found = 1; 773 break; 774 } 775 } 776 } 777 if (intrmapptr != NULL) 778 *intrmapptr = intrmap; 779 if (intrclrptr != NULL) 780 *intrclrptr = intrclr; 781 if (intrdiagptr != NULL) 782 *intrdiagptr = diag; 783 return (found); 784 } 785 786 /* 787 * Interrupt handlers 788 */ 789 static int 790 psycho_ue(void *arg) 791 { 792 struct psycho_softc *sc = arg; 793 uint64_t afar, afsr; 794 795 afar = PSYCHO_READ8(sc, PSR_UE_AFA); 796 afsr = PSYCHO_READ8(sc, PSR_UE_AFS); 797 /* 798 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause 799 * the AFAR to be set to the physical address of the TTE entry that 800 * was invalid/write protected. Call into the IOMMU code to have 801 * them decoded to virtual I/O addresses. 802 */ 803 if ((afsr & UEAFSR_P_DTE) != 0) 804 iommu_decode_fault(sc->sc_is, afar); 805 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx", 806 device_get_name(sc->sc_dev), (u_long)afar, (u_long)afsr); 807 return (FILTER_HANDLED); 808 } 809 810 static int 811 psycho_ce(void *arg) 812 { 813 struct psycho_softc *sc = arg; 814 uint64_t afar, afsr; 815 816 mtx_lock_spin(sc->sc_mtx); 817 afar = PSYCHO_READ8(sc, PSR_CE_AFA); 818 afsr = PSYCHO_READ8(sc, PSR_CE_AFS); 819 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx " 820 "AFSR %#lx\n", (u_long)afar, (u_long)afsr); 821 /* Clear the error bits that we caught. */ 822 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr); 823 mtx_unlock_spin(sc->sc_mtx); 824 return (FILTER_HANDLED); 825 } 826 827 static int 828 psycho_pci_bus(void *arg) 829 { 830 struct psycho_softc *sc = arg; 831 uint64_t afar, afsr; 832 833 afar = PCICTL_READ8(sc, PCR_AFA); 834 afsr = PCICTL_READ8(sc, PCR_AFS); 835 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx", 836 device_get_name(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar, 837 (u_long)afsr); 838 return (FILTER_HANDLED); 839 } 840 841 static int 842 psycho_powerfail(void *arg) 843 { 844 #ifdef DEBUGGER_ON_POWERFAIL 845 struct psycho_softc *sc = arg; 846 847 kdb_enter(KDB_WHY_POWERFAIL, "powerfail"); 848 #else 849 static int shutdown; 850 851 /* As the interrupt is cleared we may be called multiple times. */ 852 if (shutdown != 0) 853 return (FILTER_HANDLED); 854 shutdown++; 855 printf("Power Failure Detected: Shutting down NOW.\n"); 856 shutdown_nice(0); 857 #endif 858 return (FILTER_HANDLED); 859 } 860 861 static void 862 psycho_overtemp(void *arg) 863 { 864 static int shutdown; 865 866 /* As the interrupt is cleared we may be called multiple times. */ 867 if (shutdown != 0) 868 return; 869 shutdown++; 870 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n"); 871 shutdown_nice(RB_POWEROFF); 872 } 873 874 #ifdef PSYCHO_MAP_WAKEUP 875 static int 876 psycho_wakeup(void *arg) 877 { 878 struct psycho_softc *sc = arg; 879 880 /* Gee, we don't really have a framework to deal with this properly. */ 881 device_printf(sc->sc_dev, "power management wakeup\n"); 882 return (FILTER_HANDLED); 883 } 884 #endif /* PSYCHO_MAP_WAKEUP */ 885 886 static void 887 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase) 888 { 889 struct iommu_state *is = sc->sc_is; 890 891 /* Punch in our copies. */ 892 is->is_bustag = rman_get_bustag(sc->sc_mem_res); 893 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res); 894 is->is_iommu = PSR_IOMMU; 895 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG; 896 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG; 897 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG; 898 is->is_dva = PSR_IOMMU_SVADIAG; 899 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG; 900 901 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0); 902 } 903 904 static int 905 psycho_maxslots(device_t dev) 906 { 907 908 /* XXX: is this correct? */ 909 return (PCI_SLOTMAX); 910 } 911 912 static uint32_t 913 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 914 int width) 915 { 916 struct psycho_softc *sc; 917 bus_space_handle_t bh; 918 u_long offset = 0; 919 uint8_t byte; 920 uint16_t shrt; 921 uint32_t r, wrd; 922 int i; 923 924 sc = device_get_softc(dev); 925 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 926 927 /* 928 * The Hummingbird and Sabre bridges are picky in that they 929 * only allow their config space to be accessed using the 930 * "native" width of the respective register being accessed 931 * and return semi-random other content of their config space 932 * otherwise. Given that the PCI specs don't say anything 933 * about such a (unusual) limitation and lots of stuff expects 934 * to be able to access the contents of the config space at 935 * any width we allow just that. We do this by using a copy 936 * of the header of the bridge (the rest is all zero anyway) 937 * read during attach (expect for PCIR_STATUS) in order to 938 * simplify things. 939 * The Psycho bridges contain a dupe of their header at 0x80 940 * which we nullify that way also. 941 */ 942 if (bus == sc->sc_pci_secbus && slot == PCS_DEVICE && 943 func == PCS_FUNC) { 944 if (offset % width != 0) 945 return (-1); 946 947 if (reg >= sizeof(sc->sc_pci_hpbcfg)) 948 return (0); 949 950 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) || 951 reg == PCIR_STATUS || reg == PCIR_STATUS + 1) 952 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS], 953 bus_space_read_2(sc->sc_pci_cfgt, bh, 954 PSYCHO_CONF_OFF(sc->sc_pci_secbus, 955 PCS_DEVICE, PCS_FUNC, PCIR_STATUS))); 956 957 switch (width) { 958 case 1: 959 return (sc->sc_pci_hpbcfg[reg]); 960 case 2: 961 return (le16dec(&sc->sc_pci_hpbcfg[reg])); 962 case 4: 963 return (le32dec(&sc->sc_pci_hpbcfg[reg])); 964 } 965 } 966 967 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 968 switch (width) { 969 case 1: 970 i = bus_space_peek_1(sc->sc_pci_cfgt, bh, offset, &byte); 971 r = byte; 972 break; 973 case 2: 974 i = bus_space_peek_2(sc->sc_pci_cfgt, bh, offset, &shrt); 975 r = shrt; 976 break; 977 case 4: 978 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd); 979 r = wrd; 980 break; 981 default: 982 panic("%s: bad width", __func__); 983 /* NOTREACHED */ 984 } 985 986 if (i) { 987 #ifdef PSYCHO_DEBUG 988 printf("%s: read data error reading: %d.%d.%d: 0x%x\n", 989 __func__, bus, slot, func, reg); 990 #endif 991 r = -1; 992 } 993 return (r); 994 } 995 996 static void 997 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 998 uint32_t val, int width) 999 { 1000 struct psycho_softc *sc; 1001 bus_space_handle_t bh; 1002 u_long offset = 0; 1003 1004 sc = device_get_softc(dev); 1005 offset = PSYCHO_CONF_OFF(bus, slot, func, reg); 1006 bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG]; 1007 switch (width) { 1008 case 1: 1009 bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val); 1010 break; 1011 case 2: 1012 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val); 1013 break; 1014 case 4: 1015 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val); 1016 break; 1017 default: 1018 panic("%s: bad width", __func__); 1019 /* NOTREACHED */ 1020 } 1021 } 1022 1023 static int 1024 psycho_route_interrupt(device_t bridge, device_t dev, int pin) 1025 { 1026 struct psycho_softc *sc; 1027 struct ofw_pci_register reg; 1028 bus_addr_t intrmap; 1029 ofw_pci_intr_t pintr, mintr; 1030 uint8_t maskbuf[sizeof(reg) + sizeof(pintr)]; 1031 1032 sc = device_get_softc(bridge); 1033 pintr = pin; 1034 if (ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, ®, 1035 sizeof(reg), &pintr, sizeof(pintr), &mintr, sizeof(mintr), maskbuf)) 1036 return (mintr); 1037 /* 1038 * If this is outside of the range for an intpin, it's likely a full 1039 * INO, and no mapping is required at all; this happens on the U30, 1040 * where there's no interrupt map at the Psycho node. Fortunately, 1041 * there seem to be no INOs in the intpin range on this boxen, so 1042 * this easy heuristics will do. 1043 */ 1044 if (pin > 4) 1045 return (pin); 1046 /* 1047 * Guess the INO; we always assume that this is a non-OBIO 1048 * device, and that pin is a "real" intpin number. Determine 1049 * the mapping register to be used by the slot number. 1050 * We only need to do this on E450s, it seems; here, the slot numbers 1051 * for bus A are one-based, while those for bus B seemingly have an 1052 * offset of 2 (hence the factor of 3 below). 1053 */ 1054 intrmap = PSR_PCIA0_INT_MAP + 1055 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half); 1056 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1; 1057 device_printf(bridge, "guessing interrupt %d for device %d.%d pin %d\n", 1058 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin); 1059 return (mintr); 1060 } 1061 1062 static int 1063 psycho_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1064 { 1065 struct psycho_softc *sc; 1066 1067 sc = device_get_softc(dev); 1068 switch (which) { 1069 case PCIB_IVAR_DOMAIN: 1070 *result = device_get_unit(dev); 1071 return (0); 1072 case PCIB_IVAR_BUS: 1073 *result = sc->sc_pci_secbus; 1074 return (0); 1075 } 1076 return (ENOENT); 1077 } 1078 1079 static int 1080 psycho_dma_sync_stub(void *arg) 1081 { 1082 struct psycho_dma_sync *pds = arg; 1083 1084 (void)PCIB_READ_CONFIG(pds->pds_ppb, pds->pds_bus, pds->pds_slot, 1085 pds->pds_func, PCIR_VENDOR, 2); 1086 (void)PSYCHO_READ8(pds->pds_sc, PSR_DMA_WRITE_SYNC); 1087 return (pds->pds_handler(pds->pds_arg)); 1088 } 1089 1090 static void 1091 psycho_intr_enable(void *arg) 1092 { 1093 struct intr_vector *iv = arg; 1094 struct psycho_icarg *pica = iv->iv_icarg; 1095 1096 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, 1097 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1098 } 1099 1100 static void 1101 psycho_intr_disable(void *arg) 1102 { 1103 struct intr_vector *iv = arg; 1104 struct psycho_icarg *pica = iv->iv_icarg; 1105 1106 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec); 1107 } 1108 1109 static void 1110 psycho_intr_assign(void *arg) 1111 { 1112 struct intr_vector *iv = arg; 1113 struct psycho_icarg *pica = iv->iv_icarg; 1114 1115 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID( 1116 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid)); 1117 } 1118 1119 static void 1120 psycho_intr_clear(void *arg) 1121 { 1122 struct intr_vector *iv = arg; 1123 struct psycho_icarg *pica = iv->iv_icarg; 1124 1125 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, 0); 1126 } 1127 1128 static int 1129 psycho_setup_intr(device_t dev, device_t child, struct resource *ires, 1130 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1131 void **cookiep) 1132 { 1133 struct { 1134 int apb:1; 1135 int ppb:1; 1136 } found; 1137 devclass_t pci_devclass; 1138 device_t cdev, pdev, pcidev; 1139 struct psycho_softc *sc; 1140 struct psycho_dma_sync *pds; 1141 u_long vec; 1142 int error; 1143 1144 sc = device_get_softc(dev); 1145 /* 1146 * Make sure the vector is fully specified and we registered 1147 * our interrupt controller for it. 1148 */ 1149 vec = rman_get_start(ires); 1150 if (INTIGN(vec) != sc->sc_ign || 1151 intr_vectors[vec].iv_ic != &psycho_ic) { 1152 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1153 return (EINVAL); 1154 } 1155 1156 /* 1157 * The Sabre-APB-combination does not automatically flush DMA 1158 * write data for devices behind additional PCI-PCI bridges 1159 * underneath the APB PCI-PCI bridge. The procedure for a 1160 * manual flush is to do a PIO read on the far side of the 1161 * farthest PCI-PCI bridge followed by a read of the PCI DMA 1162 * write sync register of the Sabre. 1163 */ 1164 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1165 pds = malloc(sizeof(*pds), M_DEVBUF, M_NOWAIT | M_ZERO); 1166 if (pds == NULL) 1167 return (ENOMEM); 1168 pcidev = NULL; 1169 found.apb = found.ppb = 0; 1170 pci_devclass = devclass_find("pci"); 1171 for (cdev = child; cdev != dev; cdev = pdev) { 1172 pdev = device_get_parent(cdev); 1173 if (pcidev == NULL) { 1174 if (device_get_devclass(pdev) != pci_devclass) 1175 continue; 1176 pcidev = cdev; 1177 continue; 1178 } 1179 /* 1180 * NB: APB would also match as PCI-PCI bridges. 1181 */ 1182 if (pci_get_vendor(cdev) == 0x108e && 1183 pci_get_device(cdev) == 0x5000) { 1184 found.apb = 1; 1185 break; 1186 } 1187 if (pci_get_class(cdev) == PCIC_BRIDGE && 1188 pci_get_subclass(cdev) == PCIS_BRIDGE_PCI) 1189 found.ppb = 1; 1190 } 1191 if (found.apb && found.ppb && pcidev != NULL) { 1192 pds->pds_sc = sc; 1193 pds->pds_arg = arg; 1194 pds->pds_ppb = 1195 device_get_parent(device_get_parent(pcidev)); 1196 pds->pds_bus = pci_get_bus(pcidev); 1197 pds->pds_slot = pci_get_slot(pcidev); 1198 pds->pds_func = pci_get_function(pcidev); 1199 if (bootverbose) 1200 device_printf(dev, "installed DMA sync " 1201 "wrapper for device %d.%d on bus %d\n", 1202 pds->pds_slot, pds->pds_func, 1203 pds->pds_bus); 1204 if (intr == NULL) { 1205 pds->pds_handler = filt; 1206 error = bus_generic_setup_intr(dev, child, 1207 ires, flags, psycho_dma_sync_stub, intr, 1208 pds, cookiep); 1209 } else { 1210 pds->pds_handler = (driver_filter_t *)intr; 1211 error = bus_generic_setup_intr(dev, child, 1212 ires, flags, filt, 1213 (driver_intr_t *)psycho_dma_sync_stub, 1214 pds, cookiep); 1215 } 1216 } else 1217 error = bus_generic_setup_intr(dev, child, ires, 1218 flags, filt, intr, arg, cookiep); 1219 if (error != 0) { 1220 free(pds, M_DEVBUF); 1221 return (error); 1222 } 1223 pds->pds_cookie = *cookiep; 1224 *cookiep = pds; 1225 return (error); 1226 } 1227 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1228 arg, cookiep)); 1229 } 1230 1231 static int 1232 psycho_teardown_intr(device_t dev, device_t child, struct resource *vec, 1233 void *cookie) 1234 { 1235 struct psycho_softc *sc; 1236 struct psycho_dma_sync *pds; 1237 int error; 1238 1239 sc = device_get_softc(dev); 1240 if (sc->sc_mode == PSYCHO_MODE_SABRE) { 1241 pds = cookie; 1242 error = bus_generic_teardown_intr(dev, child, vec, 1243 pds->pds_cookie); 1244 if (error == 0) 1245 free(pds, M_DEVBUF); 1246 return (error); 1247 } 1248 return (bus_generic_teardown_intr(dev, child, vec, cookie)); 1249 } 1250 1251 static struct resource * 1252 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, 1253 u_long start, u_long end, u_long count, u_int flags) 1254 { 1255 struct psycho_softc *sc; 1256 struct resource *rv; 1257 struct rman *rm; 1258 bus_space_tag_t bt; 1259 bus_space_handle_t bh; 1260 int needactivate = flags & RF_ACTIVE; 1261 1262 flags &= ~RF_ACTIVE; 1263 1264 sc = device_get_softc(bus); 1265 if (type == SYS_RES_IRQ) { 1266 /* 1267 * XXX: Don't accept blank ranges for now, only single 1268 * interrupts. The other case should not happen with 1269 * the MI PCI code... 1270 * XXX: This may return a resource that is out of the 1271 * range that was specified. Is this correct...? 1272 */ 1273 if (start != end) 1274 panic("%s: XXX: interrupt range", __func__); 1275 start = end = INTMAP_VEC(sc->sc_ign, end); 1276 return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type, 1277 rid, start, end, count, flags)); 1278 } 1279 switch (type) { 1280 case SYS_RES_MEMORY: 1281 rm = &sc->sc_pci_mem_rman; 1282 bt = sc->sc_pci_memt; 1283 bh = sc->sc_pci_bh[OFW_PCI_CS_MEM32]; 1284 break; 1285 case SYS_RES_IOPORT: 1286 rm = &sc->sc_pci_io_rman; 1287 bt = sc->sc_pci_iot; 1288 bh = sc->sc_pci_bh[OFW_PCI_CS_IO]; 1289 break; 1290 default: 1291 return (NULL); 1292 /* NOTREACHED */ 1293 } 1294 1295 rv = rman_reserve_resource(rm, start, end, count, flags, child); 1296 if (rv == NULL) 1297 return (NULL); 1298 rman_set_rid(rv, *rid); 1299 bh += rman_get_start(rv); 1300 rman_set_bustag(rv, bt); 1301 rman_set_bushandle(rv, bh); 1302 1303 if (needactivate) { 1304 if (bus_activate_resource(child, type, *rid, rv)) { 1305 rman_release_resource(rv); 1306 return (NULL); 1307 } 1308 } 1309 return (rv); 1310 } 1311 1312 static int 1313 psycho_activate_resource(device_t bus, device_t child, int type, int rid, 1314 struct resource *r) 1315 { 1316 void *p; 1317 int error; 1318 1319 if (type == SYS_RES_IRQ) 1320 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child, 1321 type, rid, r)); 1322 if (type == SYS_RES_MEMORY) { 1323 /* 1324 * Need to memory-map the device space, as some drivers 1325 * depend on the virtual address being set and usable. 1326 */ 1327 error = sparc64_bus_mem_map(rman_get_bustag(r), 1328 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 1329 if (error != 0) 1330 return (error); 1331 rman_set_virtual(r, p); 1332 } 1333 return (rman_activate_resource(r)); 1334 } 1335 1336 static int 1337 psycho_deactivate_resource(device_t bus, device_t child, int type, int rid, 1338 struct resource *r) 1339 { 1340 1341 if (type == SYS_RES_IRQ) 1342 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child, 1343 type, rid, r)); 1344 if (type == SYS_RES_MEMORY) { 1345 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 1346 rman_set_virtual(r, NULL); 1347 } 1348 return (rman_deactivate_resource(r)); 1349 } 1350 1351 static int 1352 psycho_release_resource(device_t bus, device_t child, int type, int rid, 1353 struct resource *r) 1354 { 1355 int error; 1356 1357 if (type == SYS_RES_IRQ) 1358 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child, 1359 type, rid, r)); 1360 if (rman_get_flags(r) & RF_ACTIVE) { 1361 error = bus_deactivate_resource(child, type, rid, r); 1362 if (error) 1363 return (error); 1364 } 1365 return (rman_release_resource(r)); 1366 } 1367 1368 static bus_dma_tag_t 1369 psycho_get_dma_tag(device_t bus, device_t child) 1370 { 1371 struct psycho_softc *sc; 1372 1373 sc = device_get_softc(bus); 1374 return (sc->sc_pci_dmat); 1375 } 1376 1377 static phandle_t 1378 psycho_get_node(device_t bus, device_t dev) 1379 { 1380 struct psycho_softc *sc; 1381 1382 sc = device_get_softc(bus); 1383 /* We only have one child, the PCI bus, which needs our own node. */ 1384 return (sc->sc_node); 1385 } 1386 1387 static bus_space_tag_t 1388 psycho_alloc_bus_tag(struct psycho_softc *sc, int type) 1389 { 1390 bus_space_tag_t bt; 1391 1392 bt = malloc(sizeof(struct bus_space_tag), M_DEVBUF, M_NOWAIT | M_ZERO); 1393 if (bt == NULL) 1394 panic("%s: out of memory", __func__); 1395 1396 bt->bst_cookie = sc; 1397 bt->bst_parent = rman_get_bustag(sc->sc_mem_res); 1398 bt->bst_type = type; 1399 return (bt); 1400 }
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