The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/sparc64/pci/psychoreg.h

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    1 /*-
    2  * Copyright (c) 1998, 1999 Eduardo E. Horvath
    3  * Copyright (c) 1999 Matthew R. Green
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. The name of the author may not be used to endorse or promote products
   15  *    derived from this software without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   22  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   23  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   24  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   25  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  *      from: NetBSD: psychoreg.h,v 1.8 2001/09/10 16:17:06 eeh Exp
   30  *
   31  * $FreeBSD$
   32  */
   33 
   34 #ifndef _SPARC64_PCI_PSYCHOREG_H_
   35 #define _SPARC64_PCI_PSYCHOREG_H_
   36 
   37 /*
   38  * Sun4u PCI definitions.  Here's where we deal w/the machine
   39  * dependencies of Psycho and the PCI controller on the UltraIIi.
   40  *
   41  * All PCI registers are bit-swapped, however they are not byte-swapped.
   42  * This means that they must be accessed using little-endian access modes,
   43  * either map the pages little-endian or use little-endian ASIs.
   44  *
   45  * PSYCHO implements two PCI buses, A and B.
   46  */
   47 
   48 #define PSYCHO_NINTR            6
   49 #define PSYCHO_NRANGE           4
   50 
   51 /*
   52  * Psycho register offsets
   53  *
   54  * NB: FFB0 and FFB1 intr map regs also appear at 0x6000 and 0x8000
   55  * respectively.
   56  */
   57 #define PSR_UPA_PORTID          0x0000  /* UPA port ID register */
   58 #define PSR_UPA_CONFIG          0x0008  /* UPA config register */
   59 #define PSR_CS                  0x0010  /* PSYCHO control/status register */
   60 #define PSR_ECCC                0x0020  /* ECC control register */
   61 #define PSR_UE_AFS              0x0030  /* Uncorrectable Error AFSR */
   62 #define PSR_UE_AFA              0x0038  /* Uncorrectable Error AFAR */
   63 #define PSR_CE_AFS              0x0040  /* Correctable Error AFSR */
   64 #define PSR_CE_AFA              0x0048  /* Correctable Error AFAR */
   65 #define PSR_PM_CTL              0x0100  /* Performance monitor control reg */
   66 #define PSR_PM_COUNT            0x0108  /* Performance monitor counter reg */
   67 #define PSR_IOMMU               0x0200  /* IOMMU registers */
   68 #define PSR_PCIA0_INT_MAP       0x0c00  /* PCI bus a slot 0 irq map reg */
   69 #define PSR_PCIA1_INT_MAP       0x0c08  /* PCI bus a slot 1 irq map reg */
   70 #define PSR_PCIA2_INT_MAP       0x0c10  /* PCI bus a slot 2 irq map reg (IIi) */
   71 #define PSR_PCIA3_INT_MAP       0x0c18  /* PCI bus a slot 3 irq map reg (IIi) */
   72 #define PSR_PCIB0_INT_MAP       0x0c20  /* PCI bus b slot 0 irq map reg */
   73 #define PSR_PCIB1_INT_MAP       0x0c28  /* PCI bus b slot 1 irq map reg */
   74 #define PSR_PCIB2_INT_MAP       0x0c30  /* PCI bus b slot 2 irq map reg */
   75 #define PSR_PCIB3_INT_MAP       0x0c38  /* PCI bus b slot 3 irq map reg */
   76 #define PSR_SCSI_INT_MAP        0x1000  /* SCSI interrupt map reg */
   77 #define PSR_ETHER_INT_MAP       0x1008  /* ethernet interrupt map reg */
   78 #define PSR_BPP_INT_MAP         0x1010  /* parallel interrupt map reg */
   79 #define PSR_AUDIOR_INT_MAP      0x1018  /* audio record interrupt map reg */
   80 #define PSR_AUDIOP_INT_MAP      0x1020  /* audio playback interrupt map reg */
   81 #define PSR_POWER_INT_MAP       0x1028  /* power fail interrupt map reg */
   82 #define PSR_SKBDMS_INT_MAP      0x1030  /* serial/kbd/mouse interrupt map reg */
   83 #define PSR_FD_INT_MAP          0x1038  /* floppy interrupt map reg */
   84 #define PSR_SPARE_INT_MAP       0x1040  /* spare interrupt map reg */
   85 #define PSR_KBD_INT_MAP         0x1048  /* kbd [unused] interrupt map reg */
   86 #define PSR_MOUSE_INT_MAP       0x1050  /* mouse [unused] interrupt map reg */
   87 #define PSR_SERIAL_INT_MAP      0x1058  /* second serial interrupt map reg */
   88 #define PSR_TIMER0_INT_MAP      0x1060  /* timer 0 interrupt map reg */
   89 #define PSR_TIMER1_INT_MAP      0x1068  /* timer 1 interrupt map reg */
   90 #define PSR_UE_INT_MAP          0x1070  /* UE interrupt map reg */
   91 #define PSR_CE_INT_MAP          0x1078  /* CE interrupt map reg */
   92 #define PSR_PCIAERR_INT_MAP     0x1080  /* PCI bus a error interrupt map reg */
   93 #define PSR_PCIBERR_INT_MAP     0x1088  /* PCI bus b error interrupt map reg */
   94 #define PSR_PWRMGT_INT_MAP      0x1090  /* power mgmt wake interrupt map reg */
   95 #define PSR_FFB0_INT_MAP        0x1098  /* FFB0 graphics interrupt map reg */
   96 #define PSR_FFB1_INT_MAP        0x10a0  /* FFB1 graphics interrupt map reg */
   97 /* Note: clear interrupt 0 registers are not really used */
   98 #define PSR_PCIA0_INT_CLR       0x1400  /* PCI a slot 0 clear int regs 0..3 */
   99 #define PSR_PCIA1_INT_CLR       0x1420  /* PCI a slot 1 clear int regs 0..3 */
  100 #define PSR_PCIA2_INT_CLR       0x1440  /* PCI a slot 2 clear int regs 0..3 */
  101 #define PSR_PCIA3_INT_CLR       0x1460  /* PCI a slot 3 clear int regs 0..3 */
  102 #define PSR_PCIB0_INT_CLR       0x1480  /* PCI b slot 0 clear int regs 0..3 */
  103 #define PSR_PCIB1_INT_CLR       0x14a0  /* PCI b slot 1 clear int regs 0..3 */
  104 #define PSR_PCIB2_INT_CLR       0x14c0  /* PCI b slot 2 clear int regs 0..3 */
  105 #define PSR_PCIB3_INT_CLR       0x14d0  /* PCI b slot 3 clear int regs 0..3 */
  106 #define PSR_SCSI_INT_CLR        0x1800  /* SCSI clear int reg */
  107 #define PSR_ETHER_INT_CLR       0x1808  /* ethernet clear int reg */
  108 #define PSR_BPP_INT_CLR         0x1810  /* parallel clear int reg */
  109 #define PSR_AUDIOR_INT_CLR      0x1818  /* audio record clear int reg */
  110 #define PSR_AUDIOP_INT_CLR      0x1820  /* audio playback clear int reg */
  111 #define PSR_POWER_INT_CLR       0x1828  /* power fail clear int reg */
  112 #define PSR_SKBDMS_INT_CLR      0x1830  /* serial/kbd/mouse clear int reg */
  113 #define PSR_FD_INT_CLR          0x1838  /* floppy clear int reg */
  114 #define PSR_SPARE_INT_CLR       0x1840  /* spare clear int reg */
  115 #define PSR_KBD_INT_CLR         0x1848  /* kbd [unused] clear int reg */
  116 #define PSR_MOUSE_INT_CLR       0x1850  /* mouse [unused] clear int reg */
  117 #define PSR_SERIAL_INT_CLR      0x1858  /* second serial clear int reg */
  118 #define PSR_TIMER0_INT_CLR      0x1860  /* timer 0 clear int reg */
  119 #define PSR_TIMER1_INT_CLR      0x1868  /* timer 1 clear int reg */
  120 #define PSR_UE_INT_CLR          0x1870  /* UE clear int reg */
  121 #define PSR_CE_INT_CLR          0x1878  /* CE clear int reg */
  122 #define PSR_PCIAERR_INT_CLR     0x1880  /* PCI bus a error clear int reg */
  123 #define PSR_PCIBERR_INT_CLR     0x1888  /* PCI bus b error clear int reg */
  124 #define PSR_PWRMGT_INT_CLR      0x1890  /* power mgmt wake clr interrupt reg */
  125 #define PSR_INTR_RETRY_TIM      0x1a00  /* interrupt retry timer */
  126 #define PSR_TC0                 0x1c00  /* timer/counter 0 */
  127 #define PSR_TC1                 0x1c10  /* timer/counter 1 */
  128 #define PSR_DMA_WRITE_SYNC      0x1c20  /* PCI DMA write sync register (IIi) */
  129 #define PSR_PCICTL0             0x2000  /* PCICTL registers for 1st Psycho */
  130 #define PSR_PCICTL1             0x4000  /* PCICTL registers for 2nd Psycho */
  131 #define PSR_DMA_SCB_DIAG0       0xa000  /* DMA scoreboard diag reg 0 */
  132 #define PSR_DMA_SCB_DIAG1       0xa008  /* DMA scoreboard diag reg 1 */
  133 #define PSR_IOMMU_SVADIAG       0xa400  /* IOMMU virtual addr diag reg */
  134 #define PSR_IOMMU_TLB_CMP_DIAG  0xa408  /* IOMMU TLB tag compare diag reg */
  135 #define PSR_IOMMU_QUEUE_DIAG    0xa500  /* IOMMU LRU queue diag regs 0..15 */
  136 #define PSR_IOMMU_TLB_TAG_DIAG  0xa580  /* TLB tag diag regs 0..15 */
  137 #define PSR_IOMMU_TLB_DATA_DIAG 0xa600  /* TLB data RAM diag regs 0..15 */
  138 #define PSR_PCI_INT_DIAG        0xa800  /* PCI int state diag reg */
  139 #define PSR_OBIO_INT_DIAG       0xa808  /* OBIO and misc int state diag reg */
  140 #define PSR_STRBUF_DIAG         0xb000  /* Streaming buffer diag regs */
  141 /*
  142  * Here is the rest of the map, which we're not specifying:
  143  *
  144  * 1fe.0100.0000 - 1fe.01ff.ffff        PCI configuration space
  145  * 1fe.0100.0000 - 1fe.0100.00ff        PCI B configuration header
  146  * 1fe.0101.0000 - 1fe.0101.00ff        PCI A configuration header
  147  * 1fe.0200.0000 - 1fe.0200.ffff        PCI A I/O space
  148  * 1fe.0201.0000 - 1fe.0201.ffff        PCI B I/O space
  149  * 1ff.0000.0000 - 1ff.7fff.ffff        PCI A memory space
  150  * 1ff.8000.0000 - 1ff.ffff.ffff        PCI B memory space
  151  *
  152  * NB: config and I/O space can use 1-4 byte accesses, not 8 byte
  153  * accesses.  Memory space can use any sized accesses.
  154  *
  155  * Note that the SUNW,sabre/SUNW,simba combinations found on the
  156  * Ultra5 and Ultra10 machines uses slightly differrent addresses
  157  * than the above.  This is mostly due to the fact that the APB is
  158  * a multi-function PCI device with two PCI bridges, and the U2P is
  159  * two separate PCI bridges.  It uses the same PCI configuration
  160  * space, though the configuration header for each PCI bus is
  161  * located differently due to the SUNW,simba PCI busses being
  162  * function 0 and function 1 of the APB, whereas the Psycho's are
  163  * each their own PCI device.  The I/O and memory spaces are each
  164  * split into 8 equally sized areas (8x2MB blocks for I/O space,
  165  * and 8x512MB blocks for memory space).  These are allocated in to
  166  * either PCI A or PCI B, or neither in the APB's `I/O Address Map
  167  * Register A/B' (0xde) and `Memory Address Map Register A/B' (0xdf)
  168  * registers of each Simba.  We must ensure that both of the
  169  * following are correct (the prom should do this for us):
  170  *
  171  *    (PCI A Memory Address Map) & (PCI B Memory Address Map) == 0
  172  *
  173  *    (PCI A I/O Address Map) & (PCI B I/O Address Map) == 0
  174  *
  175  * 1fe.0100.0000 - 1fe.01ff.ffff        PCI configuration space
  176  * 1fe.0100.0800 - 1fe.0100.08ff        PCI B configuration header
  177  * 1fe.0100.0900 - 1fe.0100.09ff        PCI A configuration header
  178  * 1fe.0200.0000 - 1fe.02ff.ffff        PCI I/O space (divided)
  179  * 1ff.0000.0000 - 1ff.ffff.ffff        PCI memory space (divided)
  180  */
  181 
  182 /*
  183  * PSR_CS defines:
  184  *
  185  * 63     59     55     50     45     4        3       2     1      0
  186  * +------+------+------+------+--//---+--------+-------+-----+------+
  187  * | IMPL | VERS | MID  | IGN  |  xxx  | APCKEN | APERR | IAP | MODE |
  188  * +------+------+------+------+--//---+--------+-------+-----+------+
  189  *
  190  */
  191 #define PSYCHO_GCSR_IMPL(csr)   ((u_int)(((csr) >> 60) & 0xf))
  192 #define PSYCHO_GCSR_VERS(csr)   ((u_int)(((csr) >> 56) & 0xf))
  193 #define PSYCHO_GCSR_MID(csr)    ((u_int)(((csr) >> 51) & 0x1f))
  194 #define PSYCHO_GCSR_IGN(csr)    ((u_int)(((csr) >> 46) & 0x1f))
  195 #define PSYCHO_CSR_APCKEN       8       /* UPA addr parity check enable */
  196 #define PSYCHO_CSR_APERR        4       /* UPA addr parity error */
  197 #define PSYCHO_CSR_IAP          2       /* invert UPA address parity */
  198 #define PSYCHO_CSR_MODE         1       /* UPA/PCI handshake */
  199 
  200 /* Offsets into the PSR_PCICTL* register block */
  201 #define PCR_CS                  0x0000  /* PCI control/status register */
  202 #define PCR_AFS                 0x0010  /* PCI AFSR register */
  203 #define PCR_AFA                 0x0018  /* PCI AFAR register */
  204 #define PCR_DIAG                0x0020  /* PCI diagnostic register */
  205 #define PCR_TAS                 0x0028  /* PCI target address space reg (IIi) */
  206 #define PCR_STRBUF              0x0800  /* IOMMU streaming buffer registers. */
  207 
  208 /* Device space defines */
  209 #define PSYCHO_CONF_SIZE        0x1000000
  210 #define PSYCHO_CONF_BUS_SHIFT   16
  211 #define PSYCHO_CONF_DEV_SHIFT   11
  212 #define PSYCHO_CONF_FUNC_SHIFT  8
  213 #define PSYCHO_CONF_REG_SHIFT   0
  214 #define PSYCHO_IO_SIZE          0x1000000
  215 #define PSYCHO_MEM_SIZE         0x100000000
  216 
  217 #define PSYCHO_CONF_OFF(bus, slot, func, reg)                           \
  218         (((bus) << PSYCHO_CONF_BUS_SHIFT) |                             \
  219         ((slot) << PSYCHO_CONF_DEV_SHIFT) |                             \
  220         ((func) << PSYCHO_CONF_FUNC_SHIFT) |                            \
  221         ((reg) << PSYCHO_CONF_REG_SHIFT))
  222 
  223 /* what the bits mean! */
  224 
  225 /*
  226  * PCI [a|b] control/status register
  227  * Note that the Hummingbird/Sabre only has one set of PCI control/status
  228  * registers.
  229  */
  230 #define PCICTL_MRLM     0x0000001000000000      /* Memory Read Line/Multiple */
  231 #define PCICTL_SERR     0x0000000400000000      /* SERR asserted; W1C */
  232 #define PCICTL_ARB_PARK 0x0000000000200000      /* PCI arbitration parking */
  233 #define PCICTL_CPU_PRIO 0x0000000000100000      /* PCI arbitration parking */
  234 #define PCICTL_ARB_PRIO 0x00000000000f0000      /* PCI arbitration parking */
  235 #define PCICTL_ERRINTEN 0x0000000000000100      /* PCI error interrupt enable */
  236 #define PCICTL_RTRYWAIT 0x0000000000000080      /* PCI error interrupt enable */
  237 #define PCICTL_4ENABLE  0x000000000000000f      /* enable 4 PCI slots */
  238 #define PCICTL_6ENABLE  0x000000000000003f      /* enable 6 PCI slots */
  239 
  240 /* Uncorrectable error asynchronous fault status registers */
  241 #define UEAFSR_BLK      (1UL << 23)     /* Error caused by block transaction */
  242 #define UEAFSR_P_DTE    (1UL << 56)     /* Pri. DVMA translation error */
  243 #define UEAFSR_S_DTE    (1UL << 57)     /* Sec. DVMA translation error */
  244 #define UEAFSR_S_DWR    (1UL << 58)     /* Sec. error during DVMA write */
  245 #define UEAFSR_S_DRD    (1UL << 59)     /* Sec. error during DVMA read */
  246 #define UEAFSR_S_PIO    (1UL << 60)     /* Sec. error during PIO access */
  247 #define UEAFSR_P_DWR    (1UL << 61)     /* Pri. error during DVMA write */
  248 #define UEAFSR_P_DRD    (1UL << 62)     /* Pri. error during DVMA read */
  249 #define UEAFSR_P_PIO    (1UL << 63)     /* Pri. error during PIO access */
  250 
  251 /* Correctable error asynchronous fault status registers */
  252 #define CEAFSR_BLK      (1UL << 23)     /* Error caused by block transaction */
  253 #define CEAFSR_S_DWR    (1UL << 58)     /* Sec. error caused by DVMA write */
  254 #define CEAFSR_S_DRD    (1UL << 59)     /* Sec. error caused by DVMA read */
  255 #define CEAFSR_S_PIO    (1UL << 60)     /* Sec. error caused by PIO access */
  256 #define CEAFSR_P_DWR    (1UL << 61)     /* Pri. error caused by DVMA write */
  257 #define CEAFSR_P_DRD    (1UL << 62)     /* Pri. error caused by DVMA read */
  258 #define CEAFSR_P_PIO    (1UL << 63)     /* Pri. error caused by PIO access */
  259 
  260 #define CEAFSR_ERRMASK                                                  \
  261         (CEAFSR_P_PIO | CEAFSR_P_DRD | CEAFSR_P_DWR |                   \
  262          CEAFSR_S_PIO | CEAFSR_S_DRD | CEAFSR_S_DWR)
  263 
  264 /* Definitions for the target address space register */
  265 #define PCITAS_ADDR_SHIFT       29
  266 
  267 /* Definitions for the Psycho configuration space */
  268 #define PCS_DEVICE      0               /* Device number of Psycho CS entry */
  269 #define PCS_FUNC        0               /* Function number of Psycho CS entry */
  270 
  271 /* Non-Standard registers in the configration space */
  272 #define PCSR_SECBUS     0x40            /* Secondary bus number register */
  273 #define PCSR_SUBBUS     0x41            /* Subordinate bus number register */
  274 
  275 #endif /* !_SPARC64_PCI_PSYCHOREG_H_ */

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