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sys/sparc64/pci/schizo.c
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1 /*- 2 * Copyright (c) 1999, 2000 Matthew R. Green 3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 4 * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD: releng/11.2/sys/sparc64/pci/schizo.c 294883 2016-01-27 02:23:54Z jhibbits $"); 36 37 /* 38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 39 * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 40 */ 41 42 #include "opt_ofw_pci.h" 43 #include "opt_schizo.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/bus.h> 48 #include <sys/kernel.h> 49 #include <sys/lock.h> 50 #include <sys/malloc.h> 51 #include <sys/module.h> 52 #include <sys/mutex.h> 53 #include <sys/pcpu.h> 54 #include <sys/rman.h> 55 #include <sys/sysctl.h> 56 #include <sys/time.h> 57 #include <sys/timetc.h> 58 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/openfirm.h> 61 62 #include <machine/bus.h> 63 #include <machine/bus_common.h> 64 #include <machine/bus_private.h> 65 #include <machine/iommureg.h> 66 #include <machine/iommuvar.h> 67 #include <machine/resource.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <sparc64/pci/ofw_pci.h> 73 #include <sparc64/pci/schizoreg.h> 74 #include <sparc64/pci/schizovar.h> 75 76 #include "pcib_if.h" 77 78 static const struct schizo_desc *schizo_get_desc(device_t); 79 static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 80 driver_filter_t); 81 static void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 82 bus_dmasync_op_t op); 83 static void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 84 bus_dmasync_op_t op); 85 static void schizo_intr_enable(void *); 86 static void schizo_intr_disable(void *); 87 static void schizo_intr_assign(void *); 88 static void schizo_intr_clear(void *); 89 static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 90 static int schizo_get_intrmap(struct schizo_softc *, u_int, 91 bus_addr_t *, bus_addr_t *); 92 static timecounter_get_t schizo_get_timecount; 93 94 /* Interrupt handlers */ 95 static driver_filter_t schizo_pci_bus; 96 static driver_filter_t schizo_ue; 97 static driver_filter_t schizo_ce; 98 static driver_filter_t schizo_host_bus; 99 static driver_filter_t schizo_cdma; 100 101 /* IOMMU support */ 102 static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 103 104 /* 105 * Methods 106 */ 107 static device_probe_t schizo_probe; 108 static device_attach_t schizo_attach; 109 static bus_setup_intr_t schizo_setup_intr; 110 static bus_alloc_resource_t schizo_alloc_resource; 111 static pcib_maxslots_t schizo_maxslots; 112 static pcib_read_config_t schizo_read_config; 113 static pcib_write_config_t schizo_write_config; 114 static pcib_route_interrupt_t schizo_route_interrupt; 115 static ofw_pci_setup_device_t schizo_setup_device; 116 117 static device_method_t schizo_methods[] = { 118 /* Device interface */ 119 DEVMETHOD(device_probe, schizo_probe), 120 DEVMETHOD(device_attach, schizo_attach), 121 DEVMETHOD(device_shutdown, bus_generic_shutdown), 122 DEVMETHOD(device_suspend, bus_generic_suspend), 123 DEVMETHOD(device_resume, bus_generic_resume), 124 125 /* Bus interface */ 126 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar), 127 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 128 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 129 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 130 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource), 131 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 132 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource), 133 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 134 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag), 135 136 /* pcib interface */ 137 DEVMETHOD(pcib_maxslots, schizo_maxslots), 138 DEVMETHOD(pcib_read_config, schizo_read_config), 139 DEVMETHOD(pcib_write_config, schizo_write_config), 140 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 141 142 /* ofw_bus interface */ 143 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node), 144 145 /* ofw_pci interface */ 146 DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 147 148 DEVMETHOD_END 149 }; 150 151 static devclass_t schizo_devclass; 152 153 DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 154 sizeof(struct schizo_softc)); 155 EARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 156 BUS_PASS_BUS); 157 158 static SLIST_HEAD(, schizo_softc) schizo_softcs = 159 SLIST_HEAD_INITIALIZER(schizo_softcs); 160 161 static const struct intr_controller schizo_ic = { 162 schizo_intr_enable, 163 schizo_intr_disable, 164 schizo_intr_assign, 165 schizo_intr_clear 166 }; 167 168 struct schizo_icarg { 169 struct schizo_softc *sica_sc; 170 bus_addr_t sica_map; 171 bus_addr_t sica_clr; 172 }; 173 174 #define SCHIZO_CDMA_TIMEOUT 1 /* 1 second per try */ 175 #define SCHIZO_CDMA_TRIES 15 176 #define SCHIZO_PERF_CNT_QLTY 100 177 178 #define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 179 bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 180 #define SCHIZO_SPC_READ_8(spc, sc, offs) \ 181 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 182 #define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 183 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 184 185 #ifndef SCHIZO_DEBUG 186 #define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 187 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 188 #else 189 #define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 190 device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 191 (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 192 (unsigned long long)(v)); \ 193 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 194 } while (0) 195 #endif 196 197 #define SCHIZO_PCI_READ_8(sc, offs) \ 198 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 199 #define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 200 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 201 #define SCHIZO_CTRL_READ_8(sc, offs) \ 202 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 203 #define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 204 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 205 #define SCHIZO_PCICFG_READ_8(sc, offs) \ 206 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 207 #define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 208 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 209 #define SCHIZO_ICON_READ_8(sc, offs) \ 210 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 211 #define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 212 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 213 214 #define SCHIZO_PCI_SET(sc, offs, v) \ 215 SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 216 #define SCHIZO_CTRL_SET(sc, offs, v) \ 217 SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 218 219 struct schizo_desc { 220 const char *sd_string; 221 int sd_mode; 222 const char *sd_name; 223 }; 224 225 static const struct schizo_desc schizo_compats[] = { 226 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 227 #if 0 228 { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 229 #endif 230 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 231 { NULL, 0, NULL } 232 }; 233 234 static const struct schizo_desc * 235 schizo_get_desc(device_t dev) 236 { 237 const struct schizo_desc *desc; 238 const char *compat; 239 240 compat = ofw_bus_get_compat(dev); 241 if (compat == NULL) 242 return (NULL); 243 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 244 if (strcmp(desc->sd_string, compat) == 0) 245 return (desc); 246 return (NULL); 247 } 248 249 static int 250 schizo_probe(device_t dev) 251 { 252 const char *dtype; 253 254 dtype = ofw_bus_get_type(dev); 255 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 256 schizo_get_desc(dev) != NULL) { 257 device_set_desc(dev, "Sun Host-PCI bridge"); 258 return (0); 259 } 260 return (ENXIO); 261 } 262 263 static int 264 schizo_attach(device_t dev) 265 { 266 const struct schizo_desc *desc; 267 struct schizo_softc *asc, *sc, *osc; 268 struct timecounter *tc; 269 bus_dma_tag_t dmat; 270 uint64_t ino_bitmap, reg; 271 phandle_t node; 272 uint32_t prop, prop_array[2]; 273 int i, j, mode, rid, tsbsize; 274 275 sc = device_get_softc(dev); 276 node = ofw_bus_get_node(dev); 277 desc = schizo_get_desc(dev); 278 mode = desc->sd_mode; 279 280 sc->sc_dev = dev; 281 sc->sc_mode = mode; 282 sc->sc_flags = 0; 283 284 /* 285 * The Schizo has three register banks: 286 * (0) per-PBM PCI configuration and status registers, but for bus B 287 * shared with the UPA64s interrupt mapping register banks 288 * (1) shared Schizo controller configuration and status registers 289 * (2) per-PBM PCI configuration space 290 * 291 * The Tomatillo has four register banks: 292 * (0) per-PBM PCI configuration and status registers 293 * (1) per-PBM Tomatillo controller configuration registers, but on 294 * machines having the `jbusppm' device shared with its Estar 295 * register bank for bus A 296 * (2) per-PBM PCI configuration space 297 * (3) per-PBM interrupt concentrator registers 298 */ 299 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 300 20) & 1; 301 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 302 i++) { 303 rid = i; 304 sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 305 SYS_RES_MEMORY, &rid, 306 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 307 i == STX_PCI) || i == STX_CTRL)) || 308 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 309 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 310 if (sc->sc_mem_res[i] == NULL) 311 panic("%s: could not allocate register bank %d", 312 __func__, i); 313 } 314 315 /* 316 * Match other Schizos that are already configured against 317 * the controller base physical address. This will be the 318 * same for a pair of devices that share register space. 319 */ 320 osc = NULL; 321 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 322 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 323 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 324 /* Found partner. */ 325 osc = asc; 326 break; 327 } 328 } 329 if (osc == NULL) { 330 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 331 M_NOWAIT | M_ZERO); 332 if (sc->sc_mtx == NULL) 333 panic("%s: could not malloc mutex", __func__); 334 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 335 } else { 336 if (sc->sc_mode != SCHIZO_MODE_SCZ) 337 panic("%s: no partner expected", __func__); 338 if (mtx_initialized(osc->sc_mtx) == 0) 339 panic("%s: mutex not initialized", __func__); 340 sc->sc_mtx = osc->sc_mtx; 341 } 342 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 343 344 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 345 panic("%s: could not determine IGN", __func__); 346 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 347 -1) 348 panic("%s: could not determine version", __func__); 349 if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 350 &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 351 panic("%s: could not determine module-revision", __func__); 352 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 353 prop = 33000000; 354 355 if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 356 XMS_PCI_CTRL_X_MODE) != 0) { 357 if (sc->sc_mrev < 1) 358 panic("PCI-X mode unsupported"); 359 sc->sc_flags |= SCHIZO_FLAGS_XMODE; 360 } 361 362 device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 363 if (mode == SCHIZO_MODE_XMS) 364 printf("module-revision %d, ", sc->sc_mrev); 365 printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 366 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 367 "-X" : "", prop / 1000 / 1000); 368 369 /* Set up the PCI interrupt retry timer. */ 370 SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 371 372 /* Set up the PCI control register. */ 373 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 374 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 375 STX_PCI_CTRL_ARB_MASK); 376 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 377 STX_PCI_CTRL_ERR_IEN; 378 if (OF_getproplen(node, "no-bus-parking") < 0) 379 reg |= STX_PCI_CTRL_ARB_PARK; 380 if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 381 reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 382 else 383 reg |= STX_PCI_CTRL_ARB_MASK; 384 if (mode == SCHIZO_MODE_TOM) { 385 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 386 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 387 reg |= TOM_PCI_CTRL_DTO_IEN; 388 else 389 reg |= STX_PCI_CTRL_PTO; 390 } else if (mode == SCHIZO_MODE_XMS) { 391 SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 392 SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 393 reg |= XMS_PCI_CTRL_X_ERRINT_EN; 394 } 395 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 396 397 /* Set up the PCI diagnostic register. */ 398 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 399 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 400 STX_PCI_DIAG_INTRSYNC_DIS); 401 SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 402 403 /* 404 * Enable DMA write parity error interrupts of version >= 7 (i.e. 405 * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 406 * no effect though). 407 */ 408 if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 409 mode == SCHIZO_MODE_XMS) { 410 reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 411 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 412 SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 413 } 414 415 /* 416 * On Tomatillo clear the I/O prefetch lengths (workaround for a 417 * Jalapeno bug). 418 */ 419 if (mode == SCHIZO_MODE_TOM) 420 SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 421 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 422 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 423 424 /* 425 * Hunt through all the interrupt mapping regs and register 426 * the interrupt controller for our interrupt vectors. We do 427 * this early in order to be able to catch stray interrupts. 428 * This is complicated by the fact that a pair of Schizo PBMs 429 * shares one IGN. 430 */ 431 i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 432 sizeof(prop_array)); 433 if (i != -1) 434 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 435 else { 436 /* 437 * If the ino-bitmap property is missing, just provide the 438 * default set of interrupts for this controller and let 439 * schizo_setup_intr() take care of child interrupts. 440 */ 441 if (sc->sc_half == 0) 442 ino_bitmap = (1ULL << STX_UE_INO) | 443 (1ULL << STX_CE_INO) | 444 (1ULL << STX_PCIERR_A_INO) | 445 (1ULL << STX_BUS_INO); 446 else 447 ino_bitmap = 1ULL << STX_PCIERR_B_INO; 448 } 449 for (i = 0; i <= STX_MAX_INO; i++) { 450 if ((ino_bitmap & (1ULL << i)) == 0) 451 continue; 452 if (i == STX_FB0_INO || i == STX_FB1_INO) 453 /* Leave for upa(4). */ 454 continue; 455 j = schizo_intr_register(sc, i); 456 if (j != 0) 457 device_printf(dev, "could not register interrupt " 458 "controller for INO %d (%d)\n", i, j); 459 } 460 461 /* 462 * Setup Safari/JBus performance counter 0 in bus cycle counting 463 * mode as timecounter. Unfortunately, this is broken with at 464 * least the version 4 Tomatillos found in Fire V120 and Blade 465 * 1500, which apparently actually count some different event at 466 * ~0.5 and 3MHz respectively instead (also when running in full 467 * power mode). Besides, one counter seems to be shared by a 468 * "pair" of Tomatillos, too. 469 */ 470 if (sc->sc_half == 0) { 471 SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 472 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 473 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 474 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 475 if (tc == NULL) 476 panic("%s: could not malloc timecounter", __func__); 477 tc->tc_get_timecount = schizo_get_timecount; 478 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 479 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 480 sizeof(prop)) == -1) 481 panic("%s: could not determine clock frequency", 482 __func__); 483 tc->tc_frequency = prop; 484 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 485 if (mode == SCHIZO_MODE_SCZ) 486 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 487 else 488 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 489 tc->tc_priv = sc; 490 tc_init(tc); 491 } 492 493 /* 494 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 495 * one per PBM. Schizo and XMITS additionally have a streaming 496 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 497 * affected by several errata though. However, except for context 498 * flushes, taking advantage of it should be okay even with those. 499 */ 500 memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 501 sizeof(sc->sc_dma_methods)); 502 sc->sc_is.sis_sc = sc; 503 sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 504 sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 505 sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 506 if (OF_getproplen(node, "no-streaming-cache") < 0) 507 sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 508 509 #define TSBCASE(x) \ 510 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 511 tsbsize = (x); \ 512 break; \ 513 514 i = OF_getprop(node, "virtual-dma", (void *)prop_array, 515 sizeof(prop_array)); 516 if (i == -1 || i != sizeof(prop_array)) 517 schizo_iommu_init(sc, 7, -1); 518 else { 519 switch (prop_array[1]) { 520 TSBCASE(1); 521 TSBCASE(2); 522 TSBCASE(3); 523 TSBCASE(4); 524 TSBCASE(5); 525 TSBCASE(6); 526 TSBCASE(7); 527 TSBCASE(8); 528 default: 529 panic("%s: unsupported DVMA size 0x%x", 530 __func__, prop_array[1]); 531 /* NOTREACHED */ 532 } 533 schizo_iommu_init(sc, tsbsize, prop_array[0]); 534 } 535 536 #undef TSBCASE 537 538 /* Create our DMA tag. */ 539 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 540 sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 541 sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 542 &dmat) != 0) 543 panic("%s: could not create PCI DMA tag", __func__); 544 dmat->dt_cookie = &sc->sc_is; 545 dmat->dt_mt = &sc->sc_dma_methods; 546 547 if (ofw_pci_attach_common(dev, dmat, STX_IO_SIZE, STX_MEM_SIZE) != 0) 548 panic("%s: ofw_pci_attach_common() failed", __func__); 549 550 /* Clear any pending PCI error bits. */ 551 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, 552 STX_CS_FUNC, PCIR_STATUS, PCIB_READ_CONFIG(dev, 553 sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 554 2), 2); 555 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 556 SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 557 558 /* 559 * Establish handlers for interesting interrupts... 560 * Someone at Sun clearly was smoking crack; with Schizos PCI 561 * bus error interrupts for one PBM can be routed to the other 562 * PBM though we obviously need to use the softc of the former 563 * as the argument for the interrupt handler and the softc of 564 * the latter as the argument for the interrupt controller. 565 */ 566 if (sc->sc_half == 0) { 567 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 568 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 569 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 570 sica_sc == osc)) 571 /* 572 * We are the driver for PBM A and either also 573 * registered the interrupt controller for us or 574 * the driver for PBM B has probed first and 575 * registered it for us. 576 */ 577 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 578 schizo_pci_bus); 579 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 580 osc != NULL) 581 /* 582 * We are the driver for PBM A but registered 583 * the interrupt controller for PBM B, i.e. the 584 * driver for PBM B attached first but couldn't 585 * set up a handler for PBM B. 586 */ 587 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 588 schizo_pci_bus); 589 } else { 590 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 591 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 592 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 593 sica_sc == osc)) 594 /* 595 * We are the driver for PBM B and either also 596 * registered the interrupt controller for us or 597 * the driver for PBM A has probed first and 598 * registered it for us. 599 */ 600 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 601 schizo_pci_bus); 602 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 603 osc != NULL) 604 /* 605 * We are the driver for PBM B but registered 606 * the interrupt controller for PBM A, i.e. the 607 * driver for PBM A attached first but couldn't 608 * set up a handler for PBM A. 609 */ 610 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 611 schizo_pci_bus); 612 } 613 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 614 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 615 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 616 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 617 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 618 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 619 620 /* 621 * According to the Schizo Errata I-13, consistent DMA flushing/ 622 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 623 * so we can't use it and need to live with the consequences. With 624 * Schizo version >= 5, CDMA flushing/syncing is usable but requires 625 * the workaround described in Schizo Errata I-23. With Tomatillo 626 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 627 * version <= 4 (i.e. revision <= 2.3) bridges additionally require 628 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 629 */ 630 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 631 sc->sc_mode == SCHIZO_MODE_TOM || 632 sc->sc_mode == SCHIZO_MODE_XMS) { 633 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 634 sc->sc_dma_methods.dm_dmamap_sync = 635 schizo_dmamap_sync; 636 sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 637 /* 638 * Some firmware versions include the CDMA interrupt 639 * at RID 4 but most don't. With the latter we add 640 * it ourselves at the spare RID 5. 641 */ 642 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 643 4)); 644 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 645 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 646 (void)schizo_get_intrmap(sc, i, 647 &sc->sc_cdma_map, &sc->sc_cdma_clr); 648 schizo_set_intr(sc, 4, i, schizo_cdma); 649 } else { 650 i = STX_CDMA_A_INO + sc->sc_half; 651 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 652 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 653 sc->sc_cdma_vec, 1) != 0) 654 panic("%s: failed to add CDMA " 655 "interrupt", __func__); 656 j = schizo_intr_register(sc, i); 657 if (j != 0) 658 panic("%s: could not register " 659 "interrupt controller for CDMA " 660 "(%d)", __func__, j); 661 (void)schizo_get_intrmap(sc, i, 662 &sc->sc_cdma_map, &sc->sc_cdma_clr); 663 schizo_set_intr(sc, 5, i, schizo_cdma); 664 } 665 } else { 666 if (sc->sc_mode == SCHIZO_MODE_XMS) 667 mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 668 NULL, MTX_SPIN); 669 sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 670 sc->sc_half); 671 sc->sc_dma_methods.dm_dmamap_sync = 672 ichip_dmamap_sync; 673 } 674 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 675 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 676 } 677 678 /* 679 * Set the latency timer register as this isn't always done by the 680 * firmware. 681 */ 682 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, 683 STX_CS_FUNC, PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 684 685 #define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 686 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 687 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 688 (name), CTLFLAG_RD, (arg), 0, (desc)) 689 690 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 691 "DMA correctable errors"); 692 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 693 "PCI bus non-fatal errors"); 694 695 #undef SCHIZO_SYSCTL_ADD_UINT 696 697 device_add_child(dev, "pci", -1); 698 return (bus_generic_attach(dev)); 699 } 700 701 static void 702 schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 703 driver_filter_t handler) 704 { 705 u_long vec; 706 int rid; 707 708 rid = index; 709 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 710 SYS_RES_IRQ, &rid, RF_ACTIVE); 711 if (sc->sc_irq_res[index] == NULL || 712 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 713 INTIGN(vec) != sc->sc_ign || 714 intr_vectors[vec].iv_ic != &schizo_ic || 715 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 716 INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 717 &sc->sc_ihand[index]) != 0) 718 panic("%s: failed to set up interrupt %d", __func__, index); 719 } 720 721 static int 722 schizo_intr_register(struct schizo_softc *sc, u_int ino) 723 { 724 struct schizo_icarg *sica; 725 bus_addr_t intrclr, intrmap; 726 int error; 727 728 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 729 return (ENXIO); 730 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 731 if (sica == NULL) 732 return (ENOMEM); 733 sica->sica_sc = sc; 734 sica->sica_map = intrmap; 735 sica->sica_clr = intrclr; 736 #ifdef SCHIZO_DEBUG 737 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 738 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 739 (u_long)intrclr); 740 #endif 741 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 742 &schizo_ic, sica)); 743 if (error != 0) 744 free(sica, M_DEVBUF); 745 return (error); 746 } 747 748 static int 749 schizo_get_intrmap(struct schizo_softc *sc, u_int ino, 750 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 751 { 752 bus_addr_t intrclr, intrmap; 753 uint64_t mr; 754 755 /* 756 * XXX we only look for INOs rather than INRs since the firmware 757 * may not provide the IGN and the IGN is constant for all devices 758 * on that PCI controller. 759 */ 760 761 if (ino > STX_MAX_INO) { 762 device_printf(sc->sc_dev, "out of range INO %d requested\n", 763 ino); 764 return (0); 765 } 766 767 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 768 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 769 mr = SCHIZO_PCI_READ_8(sc, intrmap); 770 if (INTINO(mr) != ino) { 771 device_printf(sc->sc_dev, 772 "interrupt map entry does not match INO (%d != %d)\n", 773 (int)INTINO(mr), ino); 774 return (0); 775 } 776 777 if (intrmapptr != NULL) 778 *intrmapptr = intrmap; 779 if (intrclrptr != NULL) 780 *intrclrptr = intrclr; 781 return (1); 782 } 783 784 /* 785 * Interrupt handlers 786 */ 787 static int 788 schizo_pci_bus(void *arg) 789 { 790 struct schizo_softc *sc = arg; 791 uint64_t afar, afsr, csr, iommu, xstat; 792 uint32_t status; 793 u_int fatal; 794 795 fatal = 0; 796 797 mtx_lock_spin(sc->sc_mtx); 798 799 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 800 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 801 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 802 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 803 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 804 xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 805 else 806 xstat = 0; 807 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus, 808 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 809 810 /* 811 * IOMMU errors are only fatal on Tomatillo and there also only if 812 * target abort was not signaled. 813 */ 814 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 815 (iommu & TOM_PCI_IOMMU_ERR) != 0 && 816 ((status & PCIM_STATUS_STABORT) == 0 || 817 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 818 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 819 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 820 fatal = 1; 821 else if ((status & PCIM_STATUS_STABORT) != 0) 822 fatal = 1; 823 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 824 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 825 PCIM_STATUS_MDPERR)) != 0 || 826 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 827 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 828 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 829 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 830 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 831 STX_PCI_AFSR_P_UNUS)) != 0) 832 fatal = 1; 833 if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 834 XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 835 XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 836 XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 837 fatal = 1; 838 if (fatal == 0) 839 sc->sc_stats_pci_non_fatal++; 840 841 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 842 "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 843 'A' + sc->sc_half, (unsigned long long)afar, 844 (unsigned long long)afsr, (unsigned long long)csr, 845 (unsigned long long)iommu, (unsigned long long)xstat, status); 846 847 /* Clear the error bits that we caught. */ 848 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, 849 STX_CS_FUNC, PCIR_STATUS, status, 2); 850 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 851 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 852 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 853 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 854 SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 855 856 mtx_unlock_spin(sc->sc_mtx); 857 858 if (fatal != 0) 859 panic("%s: fatal PCI bus error", 860 device_get_nameunit(sc->sc_dev)); 861 return (FILTER_HANDLED); 862 } 863 864 static int 865 schizo_ue(void *arg) 866 { 867 struct schizo_softc *sc = arg; 868 uint64_t afar, afsr; 869 int i; 870 871 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 872 for (i = 0; i < 1000; i++) 873 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 874 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 875 break; 876 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 877 device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 878 (unsigned long long)afsr); 879 return (FILTER_HANDLED); 880 } 881 882 static int 883 schizo_ce(void *arg) 884 { 885 struct schizo_softc *sc = arg; 886 uint64_t afar, afsr; 887 int i; 888 889 mtx_lock_spin(sc->sc_mtx); 890 891 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 892 for (i = 0; i < 1000; i++) 893 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 894 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 895 break; 896 sc->sc_stats_dma_ce++; 897 device_printf(sc->sc_dev, 898 "correctable DMA error AFAR %#llx AFSR %#llx\n", 899 (unsigned long long)afar, (unsigned long long)afsr); 900 901 /* Clear the error bits that we caught. */ 902 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 903 904 mtx_unlock_spin(sc->sc_mtx); 905 906 return (FILTER_HANDLED); 907 } 908 909 static int 910 schizo_host_bus(void *arg) 911 { 912 struct schizo_softc *sc = arg; 913 uint64_t errlog; 914 915 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 916 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 917 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 918 (unsigned long long)errlog); 919 return (FILTER_HANDLED); 920 } 921 922 static int 923 schizo_cdma(void *arg) 924 { 925 struct schizo_softc *sc = arg; 926 927 atomic_cmpset_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_PENDING, 928 SCHIZO_CDMA_STATE_RECEIVED); 929 return (FILTER_HANDLED); 930 } 931 932 static void 933 schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 934 { 935 936 /* Punch in our copies. */ 937 sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 938 sc->sc_is.sis_is.is_bushandle = 939 rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 940 sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 941 sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 942 sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 943 sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 944 sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 945 sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 946 947 iommu_init(device_get_nameunit(sc->sc_dev), 948 (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 949 } 950 951 static int 952 schizo_maxslots(device_t dev) 953 { 954 struct schizo_softc *sc; 955 956 sc = device_get_softc(dev); 957 if (sc->sc_mode == SCHIZO_MODE_SCZ) 958 return (sc->sc_half == 0 ? 4 : 6); 959 960 /* XXX: is this correct? */ 961 return (PCI_SLOTMAX); 962 } 963 964 static uint32_t 965 schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 966 int width) 967 { 968 struct schizo_softc *sc; 969 970 sc = device_get_softc(dev); 971 /* 972 * The Schizo bridges contain a dupe of their header at 0x80. 973 */ 974 if (sc->sc_mode == SCHIZO_MODE_SCZ && 975 bus == sc->sc_ops.sc_pci_secbus && slot == STX_CS_DEVICE && 976 func == STX_CS_FUNC && reg + width > 0x80) 977 return (0); 978 979 return (ofw_pci_read_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus, 980 slot, func, reg), bus, slot, func, reg, width)); 981 } 982 983 static void 984 schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 985 u_int reg, uint32_t val, int width) 986 { 987 988 ofw_pci_write_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus, slot, 989 func, reg), bus, slot, func, reg, val, width); 990 } 991 992 static int 993 schizo_route_interrupt(device_t bridge, device_t dev, int pin) 994 { 995 ofw_pci_intr_t mintr; 996 997 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin); 998 if (!PCI_INTERRUPT_VALID(mintr)) 999 device_printf(bridge, 1000 "could not route pin %d for device %d.%d\n", 1001 pin, pci_get_slot(dev), pci_get_function(dev)); 1002 return (mintr); 1003 } 1004 1005 static void 1006 schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1007 { 1008 struct timeval cur, end; 1009 struct schizo_iommu_state *sis = dt->dt_cookie; 1010 struct schizo_softc *sc = sis->sis_sc; 1011 int i, res; 1012 #ifdef INVARIANTS 1013 register_t pil; 1014 #endif 1015 1016 if ((map->dm_flags & DMF_STREAMED) != 0) { 1017 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1018 return; 1019 } 1020 1021 if ((map->dm_flags & DMF_LOADED) == 0) 1022 return; 1023 1024 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1025 /* 1026 * Note that in order to allow this function to be called from 1027 * filters we would need to use a spin mutex for serialization 1028 * but given that these disable interrupts we have to emulate 1029 * one. 1030 */ 1031 critical_enter(); 1032 KASSERT((rdpr(pstate) & PSTATE_IE) != 0, 1033 ("%s: interrupts disabled", __func__)); 1034 KASSERT((pil = rdpr(pil)) <= PIL_BRIDGE, 1035 ("%s: PIL too low (%ld)", __func__, pil)); 1036 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1037 SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1038 ; 1039 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_map, 1040 INTMAP_ENABLE(sc->sc_cdma_vec, PCPU_GET(mid))); 1041 for (i = 0; i < SCHIZO_CDMA_TRIES; i++) { 1042 if (i > 0) 1043 printf("%s: try %d\n", __func__, i); 1044 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1045 INTCLR_RECEIVED); 1046 microuptime(&cur); 1047 end.tv_sec = SCHIZO_CDMA_TIMEOUT; 1048 end.tv_usec = 0; 1049 timevaladd(&end, &cur); 1050 for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1051 SCHIZO_CDMA_STATE_RECEIVED, 1052 SCHIZO_CDMA_STATE_IDLE)) == 0 && 1053 timevalcmp(&cur, &end, <=);) 1054 microuptime(&cur); 1055 if (res != 0) 1056 break; 1057 } 1058 if (res == 0) 1059 panic("%s: DMA does not sync", __func__); 1060 critical_exit(); 1061 } 1062 1063 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1064 membar(Sync); 1065 } 1066 1067 static void 1068 ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1069 { 1070 struct timeval cur, end; 1071 struct schizo_iommu_state *sis = dt->dt_cookie; 1072 struct schizo_softc *sc = sis->sis_sc; 1073 uint64_t reg; 1074 1075 if ((map->dm_flags & DMF_STREAMED) != 0) { 1076 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1077 return; 1078 } 1079 1080 if ((map->dm_flags & DMF_LOADED) == 0) 1081 return; 1082 1083 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1084 if (sc->sc_mode == SCHIZO_MODE_XMS) 1085 mtx_lock_spin(&sc->sc_sync_mtx); 1086 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1087 sc->sc_sync_val); 1088 microuptime(&cur); 1089 end.tv_sec = 1; 1090 end.tv_usec = 0; 1091 timevaladd(&end, &cur); 1092 for (; ((reg = SCHIZO_PCI_READ_8(sc, 1093 TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1094 timevalcmp(&cur, &end, <=);) 1095 microuptime(&cur); 1096 if ((reg & sc->sc_sync_val) != 0) 1097 panic("%s: DMA does not sync", __func__); 1098 if (sc->sc_mode == SCHIZO_MODE_XMS) 1099 mtx_unlock_spin(&sc->sc_sync_mtx); 1100 else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1101 ofw_pci_dmamap_sync_stst_order_common(); 1102 return; 1103 } 1104 } 1105 1106 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1107 membar(Sync); 1108 } 1109 1110 static void 1111 schizo_intr_enable(void *arg) 1112 { 1113 struct intr_vector *iv = arg; 1114 struct schizo_icarg *sica = iv->iv_icarg; 1115 1116 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1117 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1118 } 1119 1120 static void 1121 schizo_intr_disable(void *arg) 1122 { 1123 struct intr_vector *iv = arg; 1124 struct schizo_icarg *sica = iv->iv_icarg; 1125 1126 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1127 } 1128 1129 static void 1130 schizo_intr_assign(void *arg) 1131 { 1132 struct intr_vector *iv = arg; 1133 struct schizo_icarg *sica = iv->iv_icarg; 1134 1135 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1136 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1137 } 1138 1139 static void 1140 schizo_intr_clear(void *arg) 1141 { 1142 struct intr_vector *iv = arg; 1143 struct schizo_icarg *sica = iv->iv_icarg; 1144 1145 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1146 } 1147 1148 static int 1149 schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1150 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1151 void **cookiep) 1152 { 1153 struct schizo_softc *sc; 1154 u_long vec; 1155 int error; 1156 1157 sc = device_get_softc(dev); 1158 /* 1159 * Make sure the vector is fully specified. 1160 */ 1161 vec = rman_get_start(ires); 1162 if (INTIGN(vec) != sc->sc_ign) { 1163 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1164 return (EINVAL); 1165 } 1166 1167 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1168 /* 1169 * Ensure we use the right softc in case the interrupt 1170 * is routed to our companion PBM for some odd reason. 1171 */ 1172 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1173 sica_sc; 1174 } else if (intr_vectors[vec].iv_ic == NULL) { 1175 /* 1176 * Work around broken firmware which misses entries in 1177 * the ino-bitmap. 1178 */ 1179 error = schizo_intr_register(sc, INTINO(vec)); 1180 if (error != 0) { 1181 device_printf(dev, "could not register interrupt " 1182 "controller for vector 0x%lx (%d)\n", vec, error); 1183 return (error); 1184 } 1185 if (bootverbose) 1186 device_printf(dev, "belatedly registered as " 1187 "interrupt controller for vector 0x%lx\n", vec); 1188 } else { 1189 device_printf(dev, 1190 "invalid interrupt controller for vector 0x%lx\n", vec); 1191 return (EINVAL); 1192 } 1193 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1194 arg, cookiep)); 1195 } 1196 1197 static struct resource * 1198 schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1199 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1200 { 1201 struct schizo_softc *sc; 1202 1203 if (type == SYS_RES_IRQ) { 1204 sc = device_get_softc(bus); 1205 start = end = INTMAP_VEC(sc->sc_ign, end); 1206 } 1207 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end, 1208 count, flags)); 1209 } 1210 1211 static void 1212 schizo_setup_device(device_t bus, device_t child) 1213 { 1214 struct schizo_softc *sc; 1215 uint64_t reg; 1216 int capreg; 1217 1218 sc = device_get_softc(bus); 1219 /* 1220 * Disable bus parking in order to work around a bus hang caused by 1221 * Casinni/Skyhawk combinations. 1222 */ 1223 if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1224 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1225 STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1226 1227 if (sc->sc_mode == SCHIZO_MODE_XMS) { 1228 /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1229 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1230 (pci_read_config(child, PCIR_HDRTYPE, 1) & 1231 PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1232 pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1233 pci_write_config(child, capreg + PCIXR_COMMAND, 1234 pci_read_config(child, capreg + PCIXR_COMMAND, 1235 2) & 0x7c, 2); 1236 /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1237 if (sc->sc_mrev >= 4) { 1238 reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1239 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1240 if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1241 XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1242 SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1243 } 1244 } 1245 } 1246 1247 static u_int 1248 schizo_get_timecount(struct timecounter *tc) 1249 { 1250 struct schizo_softc *sc; 1251 1252 sc = tc->tc_priv; 1253 return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1254 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >> 1255 STX_CTRL_PERF_CNT_CNT0_SHIFT); 1256 }
Cache object: 04bf6e0ede2afe8b4e5de9618071d46e
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