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sys/sparc64/pci/schizo.c
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1999, 2000 Matthew R. Green 5 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org> 6 * Copyright (c) 2005 - 2011 by Marius Strobl <marius@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 25 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 27 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp 33 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 /* 40 * Driver for `Schizo' Fireplane/Safari to PCI 2.1, `Tomatillo' JBus to 41 * PCI 2.2 and `XMITS' Fireplane/Safari to PCI-X bridges 42 */ 43 44 #include "opt_ofw_pci.h" 45 #include "opt_schizo.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/bus.h> 50 #include <sys/kernel.h> 51 #include <sys/lock.h> 52 #include <sys/malloc.h> 53 #include <sys/module.h> 54 #include <sys/mutex.h> 55 #include <sys/pcpu.h> 56 #include <sys/rman.h> 57 #include <sys/sysctl.h> 58 #include <sys/time.h> 59 #include <sys/timetc.h> 60 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/openfirm.h> 63 64 #include <machine/bus.h> 65 #include <machine/bus_common.h> 66 #include <machine/bus_private.h> 67 #include <machine/iommureg.h> 68 #include <machine/iommuvar.h> 69 #include <machine/resource.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcib_private.h> 74 75 #include <sparc64/pci/ofw_pci.h> 76 #include <sparc64/pci/schizoreg.h> 77 #include <sparc64/pci/schizovar.h> 78 79 #include "pcib_if.h" 80 81 static const struct schizo_desc *schizo_get_desc(device_t); 82 static void schizo_set_intr(struct schizo_softc *, u_int, u_int, 83 driver_filter_t); 84 static void schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 85 bus_dmasync_op_t op); 86 static void ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, 87 bus_dmasync_op_t op); 88 static void schizo_intr_enable(void *); 89 static void schizo_intr_disable(void *); 90 static void schizo_intr_assign(void *); 91 static void schizo_intr_clear(void *); 92 static int schizo_intr_register(struct schizo_softc *sc, u_int ino); 93 static int schizo_get_intrmap(struct schizo_softc *, u_int, 94 bus_addr_t *, bus_addr_t *); 95 static timecounter_get_t schizo_get_timecount; 96 97 /* Interrupt handlers */ 98 static driver_filter_t schizo_pci_bus; 99 static driver_filter_t schizo_ue; 100 static driver_filter_t schizo_ce; 101 static driver_filter_t schizo_host_bus; 102 static driver_filter_t schizo_cdma; 103 104 /* IOMMU support */ 105 static void schizo_iommu_init(struct schizo_softc *, int, uint32_t); 106 107 /* 108 * Methods 109 */ 110 static device_probe_t schizo_probe; 111 static device_attach_t schizo_attach; 112 static bus_setup_intr_t schizo_setup_intr; 113 static bus_alloc_resource_t schizo_alloc_resource; 114 static pcib_maxslots_t schizo_maxslots; 115 static pcib_read_config_t schizo_read_config; 116 static pcib_write_config_t schizo_write_config; 117 static pcib_route_interrupt_t schizo_route_interrupt; 118 static ofw_pci_setup_device_t schizo_setup_device; 119 120 static device_method_t schizo_methods[] = { 121 /* Device interface */ 122 DEVMETHOD(device_probe, schizo_probe), 123 DEVMETHOD(device_attach, schizo_attach), 124 DEVMETHOD(device_shutdown, bus_generic_shutdown), 125 DEVMETHOD(device_suspend, bus_generic_suspend), 126 DEVMETHOD(device_resume, bus_generic_resume), 127 128 /* Bus interface */ 129 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar), 130 DEVMETHOD(bus_setup_intr, schizo_setup_intr), 131 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 132 DEVMETHOD(bus_alloc_resource, schizo_alloc_resource), 133 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource), 134 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 135 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource), 136 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 137 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag), 138 139 /* pcib interface */ 140 DEVMETHOD(pcib_maxslots, schizo_maxslots), 141 DEVMETHOD(pcib_read_config, schizo_read_config), 142 DEVMETHOD(pcib_write_config, schizo_write_config), 143 DEVMETHOD(pcib_route_interrupt, schizo_route_interrupt), 144 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 145 146 /* ofw_bus interface */ 147 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node), 148 149 /* ofw_pci interface */ 150 DEVMETHOD(ofw_pci_setup_device, schizo_setup_device), 151 152 DEVMETHOD_END 153 }; 154 155 static devclass_t schizo_devclass; 156 157 DEFINE_CLASS_0(pcib, schizo_driver, schizo_methods, 158 sizeof(struct schizo_softc)); 159 EARLY_DRIVER_MODULE(schizo, nexus, schizo_driver, schizo_devclass, 0, 0, 160 BUS_PASS_BUS); 161 162 static SLIST_HEAD(, schizo_softc) schizo_softcs = 163 SLIST_HEAD_INITIALIZER(schizo_softcs); 164 165 static const struct intr_controller schizo_ic = { 166 schizo_intr_enable, 167 schizo_intr_disable, 168 schizo_intr_assign, 169 schizo_intr_clear 170 }; 171 172 struct schizo_icarg { 173 struct schizo_softc *sica_sc; 174 bus_addr_t sica_map; 175 bus_addr_t sica_clr; 176 }; 177 178 #define SCHIZO_CDMA_TIMEOUT 1 /* 1 second per try */ 179 #define SCHIZO_CDMA_TRIES 15 180 #define SCHIZO_PERF_CNT_QLTY 100 181 182 #define SCHIZO_SPC_BARRIER(spc, sc, offs, len, flags) \ 183 bus_barrier((sc)->sc_mem_res[(spc)], (offs), (len), (flags)) 184 #define SCHIZO_SPC_READ_8(spc, sc, offs) \ 185 bus_read_8((sc)->sc_mem_res[(spc)], (offs)) 186 #define SCHIZO_SPC_WRITE_8(spc, sc, offs, v) \ 187 bus_write_8((sc)->sc_mem_res[(spc)], (offs), (v)) 188 189 #ifndef SCHIZO_DEBUG 190 #define SCHIZO_SPC_SET(spc, sc, offs, reg, v) \ 191 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)) 192 #else 193 #define SCHIZO_SPC_SET(spc, sc, offs, reg, v) do { \ 194 device_printf((sc)->sc_dev, reg " 0x%016llx -> 0x%016llx\n", \ 195 (unsigned long long)SCHIZO_SPC_READ_8((spc), (sc), (offs)), \ 196 (unsigned long long)(v)); \ 197 SCHIZO_SPC_WRITE_8((spc), (sc), (offs), (v)); \ 198 } while (0) 199 #endif 200 201 #define SCHIZO_PCI_READ_8(sc, offs) \ 202 SCHIZO_SPC_READ_8(STX_PCI, (sc), (offs)) 203 #define SCHIZO_PCI_WRITE_8(sc, offs, v) \ 204 SCHIZO_SPC_WRITE_8(STX_PCI, (sc), (offs), (v)) 205 #define SCHIZO_CTRL_READ_8(sc, offs) \ 206 SCHIZO_SPC_READ_8(STX_CTRL, (sc), (offs)) 207 #define SCHIZO_CTRL_WRITE_8(sc, offs, v) \ 208 SCHIZO_SPC_WRITE_8(STX_CTRL, (sc), (offs), (v)) 209 #define SCHIZO_PCICFG_READ_8(sc, offs) \ 210 SCHIZO_SPC_READ_8(STX_PCICFG, (sc), (offs)) 211 #define SCHIZO_PCICFG_WRITE_8(sc, offs, v) \ 212 SCHIZO_SPC_WRITE_8(STX_PCICFG, (sc), (offs), (v)) 213 #define SCHIZO_ICON_READ_8(sc, offs) \ 214 SCHIZO_SPC_READ_8(STX_ICON, (sc), (offs)) 215 #define SCHIZO_ICON_WRITE_8(sc, offs, v) \ 216 SCHIZO_SPC_WRITE_8(STX_ICON, (sc), (offs), (v)) 217 218 #define SCHIZO_PCI_SET(sc, offs, v) \ 219 SCHIZO_SPC_SET(STX_PCI, (sc), (offs), # offs, (v)) 220 #define SCHIZO_CTRL_SET(sc, offs, v) \ 221 SCHIZO_SPC_SET(STX_CTRL, (sc), (offs), # offs, (v)) 222 223 struct schizo_desc { 224 const char *sd_string; 225 int sd_mode; 226 const char *sd_name; 227 }; 228 229 static const struct schizo_desc schizo_compats[] = { 230 { "pci108e,8001", SCHIZO_MODE_SCZ, "Schizo" }, 231 #if 0 232 { "pci108e,8002", SCHIZO_MODE_XMS, "XMITS" }, 233 #endif 234 { "pci108e,a801", SCHIZO_MODE_TOM, "Tomatillo" }, 235 { NULL, 0, NULL } 236 }; 237 238 static const struct schizo_desc * 239 schizo_get_desc(device_t dev) 240 { 241 const struct schizo_desc *desc; 242 const char *compat; 243 244 compat = ofw_bus_get_compat(dev); 245 if (compat == NULL) 246 return (NULL); 247 for (desc = schizo_compats; desc->sd_string != NULL; desc++) 248 if (strcmp(desc->sd_string, compat) == 0) 249 return (desc); 250 return (NULL); 251 } 252 253 static int 254 schizo_probe(device_t dev) 255 { 256 const char *dtype; 257 258 dtype = ofw_bus_get_type(dev); 259 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 && 260 schizo_get_desc(dev) != NULL) { 261 device_set_desc(dev, "Sun Host-PCI bridge"); 262 return (0); 263 } 264 return (ENXIO); 265 } 266 267 static int 268 schizo_attach(device_t dev) 269 { 270 const struct schizo_desc *desc; 271 struct schizo_softc *asc, *sc, *osc; 272 struct timecounter *tc; 273 bus_dma_tag_t dmat; 274 uint64_t ino_bitmap, reg; 275 phandle_t node; 276 uint32_t prop, prop_array[2]; 277 int i, j, mode, rid, tsbsize; 278 279 sc = device_get_softc(dev); 280 node = ofw_bus_get_node(dev); 281 desc = schizo_get_desc(dev); 282 mode = desc->sd_mode; 283 284 sc->sc_dev = dev; 285 sc->sc_mode = mode; 286 sc->sc_flags = 0; 287 288 /* 289 * The Schizo has three register banks: 290 * (0) per-PBM PCI configuration and status registers, but for bus B 291 * shared with the UPA64s interrupt mapping register banks 292 * (1) shared Schizo controller configuration and status registers 293 * (2) per-PBM PCI configuration space 294 * 295 * The Tomatillo has four register banks: 296 * (0) per-PBM PCI configuration and status registers 297 * (1) per-PBM Tomatillo controller configuration registers, but on 298 * machines having the `jbusppm' device shared with its Estar 299 * register bank for bus A 300 * (2) per-PBM PCI configuration space 301 * (3) per-PBM interrupt concentrator registers 302 */ 303 sc->sc_half = (bus_get_resource_start(dev, SYS_RES_MEMORY, STX_PCI) >> 304 20) & 1; 305 for (i = 0; i < (mode == SCHIZO_MODE_SCZ ? SCZ_NREG : TOM_NREG); 306 i++) { 307 rid = i; 308 sc->sc_mem_res[i] = bus_alloc_resource_any(dev, 309 SYS_RES_MEMORY, &rid, 310 (((mode == SCHIZO_MODE_SCZ && ((sc->sc_half == 1 && 311 i == STX_PCI) || i == STX_CTRL)) || 312 (mode == SCHIZO_MODE_TOM && sc->sc_half == 0 && 313 i == STX_CTRL)) ? RF_SHAREABLE : 0) | RF_ACTIVE); 314 if (sc->sc_mem_res[i] == NULL) 315 panic("%s: could not allocate register bank %d", 316 __func__, i); 317 } 318 319 /* 320 * Match other Schizos that are already configured against 321 * the controller base physical address. This will be the 322 * same for a pair of devices that share register space. 323 */ 324 osc = NULL; 325 SLIST_FOREACH(asc, &schizo_softcs, sc_link) { 326 if (rman_get_start(asc->sc_mem_res[STX_CTRL]) == 327 rman_get_start(sc->sc_mem_res[STX_CTRL])) { 328 /* Found partner. */ 329 osc = asc; 330 break; 331 } 332 } 333 if (osc == NULL) { 334 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF, 335 M_NOWAIT | M_ZERO); 336 if (sc->sc_mtx == NULL) 337 panic("%s: could not malloc mutex", __func__); 338 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN); 339 } else { 340 if (sc->sc_mode != SCHIZO_MODE_SCZ) 341 panic("%s: no partner expected", __func__); 342 if (mtx_initialized(osc->sc_mtx) == 0) 343 panic("%s: mutex not initialized", __func__); 344 sc->sc_mtx = osc->sc_mtx; 345 } 346 SLIST_INSERT_HEAD(&schizo_softcs, sc, sc_link); 347 348 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) 349 panic("%s: could not determine IGN", __func__); 350 if (OF_getprop(node, "version#", &sc->sc_ver, sizeof(sc->sc_ver)) == 351 -1) 352 panic("%s: could not determine version", __func__); 353 if (mode == SCHIZO_MODE_XMS && OF_getprop(node, "module-revision#", 354 &sc->sc_mrev, sizeof(sc->sc_mrev)) == -1) 355 panic("%s: could not determine module-revision", __func__); 356 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1) 357 prop = 33000000; 358 359 if (mode == SCHIZO_MODE_XMS && (SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL) & 360 XMS_PCI_CTRL_X_MODE) != 0) { 361 if (sc->sc_mrev < 1) 362 panic("PCI-X mode unsupported"); 363 sc->sc_flags |= SCHIZO_FLAGS_XMODE; 364 } 365 366 device_printf(dev, "%s, version %d, ", desc->sd_name, sc->sc_ver); 367 if (mode == SCHIZO_MODE_XMS) 368 printf("module-revision %d, ", sc->sc_mrev); 369 printf("IGN %#x, bus %c, PCI%s mode, %dMHz\n", sc->sc_ign, 370 'A' + sc->sc_half, (sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 371 "-X" : "", prop / 1000 / 1000); 372 373 /* Set up the PCI interrupt retry timer. */ 374 SCHIZO_PCI_SET(sc, STX_PCI_INTR_RETRY_TIM, 5); 375 376 /* Set up the PCI control register. */ 377 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 378 reg &= ~(TOM_PCI_CTRL_DTO_IEN | STX_PCI_CTRL_ARB_PARK | 379 STX_PCI_CTRL_ARB_MASK); 380 reg |= STX_PCI_CTRL_MMU_IEN | STX_PCI_CTRL_SBH_IEN | 381 STX_PCI_CTRL_ERR_IEN; 382 if (OF_getproplen(node, "no-bus-parking") < 0) 383 reg |= STX_PCI_CTRL_ARB_PARK; 384 if (mode == SCHIZO_MODE_XMS && sc->sc_mrev == 1) 385 reg |= XMS_PCI_CTRL_XMITS10_ARB_MASK; 386 else 387 reg |= STX_PCI_CTRL_ARB_MASK; 388 if (mode == SCHIZO_MODE_TOM) { 389 reg |= TOM_PCI_CTRL_PRM | TOM_PCI_CTRL_PRO | TOM_PCI_CTRL_PRL; 390 if (sc->sc_ver <= 1) /* revision <= 2.0 */ 391 reg |= TOM_PCI_CTRL_DTO_IEN; 392 else 393 reg |= STX_PCI_CTRL_PTO; 394 } else if (mode == SCHIZO_MODE_XMS) { 395 SCHIZO_PCI_SET(sc, XMS_PCI_PARITY_DETECT, 0x3fff); 396 SCHIZO_PCI_SET(sc, XMS_PCI_UPPER_RETRY_COUNTER, 0x3e8); 397 reg |= XMS_PCI_CTRL_X_ERRINT_EN; 398 } 399 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, reg); 400 401 /* Set up the PCI diagnostic register. */ 402 reg = SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG); 403 reg &= ~(SCZ_PCI_DIAG_RTRYARB_DIS | STX_PCI_DIAG_RETRY_DIS | 404 STX_PCI_DIAG_INTRSYNC_DIS); 405 SCHIZO_PCI_SET(sc, STX_PCI_DIAG, reg); 406 407 /* 408 * Enable DMA write parity error interrupts of version >= 7 (i.e. 409 * revision >= 2.5) Schizo and XMITS (enabling it on XMITS < 3.0 has 410 * no effect though). 411 */ 412 if ((mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) || 413 mode == SCHIZO_MODE_XMS) { 414 reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD); 415 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN; 416 SCHIZO_PCI_SET(sc, SX_PCI_CFG_ICD, reg); 417 } 418 419 /* 420 * On Tomatillo clear the I/O prefetch lengths (workaround for a 421 * Jalapeno bug). 422 */ 423 if (mode == SCHIZO_MODE_TOM) 424 SCHIZO_PCI_SET(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW | 425 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM | 426 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL); 427 428 /* 429 * Hunt through all the interrupt mapping regs and register 430 * the interrupt controller for our interrupt vectors. We do 431 * this early in order to be able to catch stray interrupts. 432 * This is complicated by the fact that a pair of Schizo PBMs 433 * shares one IGN. 434 */ 435 i = OF_getprop(node, "ino-bitmap", (void *)prop_array, 436 sizeof(prop_array)); 437 if (i != -1) 438 ino_bitmap = ((uint64_t)prop_array[1] << 32) | prop_array[0]; 439 else { 440 /* 441 * If the ino-bitmap property is missing, just provide the 442 * default set of interrupts for this controller and let 443 * schizo_setup_intr() take care of child interrupts. 444 */ 445 if (sc->sc_half == 0) 446 ino_bitmap = (1ULL << STX_UE_INO) | 447 (1ULL << STX_CE_INO) | 448 (1ULL << STX_PCIERR_A_INO) | 449 (1ULL << STX_BUS_INO); 450 else 451 ino_bitmap = 1ULL << STX_PCIERR_B_INO; 452 } 453 for (i = 0; i <= STX_MAX_INO; i++) { 454 if ((ino_bitmap & (1ULL << i)) == 0) 455 continue; 456 if (i == STX_FB0_INO || i == STX_FB1_INO) 457 /* Leave for upa(4). */ 458 continue; 459 j = schizo_intr_register(sc, i); 460 if (j != 0) 461 device_printf(dev, "could not register interrupt " 462 "controller for INO %d (%d)\n", i, j); 463 } 464 465 /* 466 * Setup Safari/JBus performance counter 0 in bus cycle counting 467 * mode as timecounter. Unfortunately, this is broken with at 468 * least the version 4 Tomatillos found in Fire V120 and Blade 469 * 1500, which apparently actually count some different event at 470 * ~0.5 and 3MHz respectively instead (also when running in full 471 * power mode). Besides, one counter seems to be shared by a 472 * "pair" of Tomatillos, too. 473 */ 474 if (sc->sc_half == 0) { 475 SCHIZO_CTRL_SET(sc, STX_CTRL_PERF, 476 (STX_CTRL_PERF_DIS << STX_CTRL_PERF_CNT1_SHIFT) | 477 (STX_CTRL_PERF_BUSCYC << STX_CTRL_PERF_CNT0_SHIFT)); 478 tc = malloc(sizeof(*tc), M_DEVBUF, M_NOWAIT | M_ZERO); 479 if (tc == NULL) 480 panic("%s: could not malloc timecounter", __func__); 481 tc->tc_get_timecount = schizo_get_timecount; 482 tc->tc_counter_mask = STX_CTRL_PERF_CNT_MASK; 483 if (OF_getprop(OF_peer(0), "clock-frequency", &prop, 484 sizeof(prop)) == -1) 485 panic("%s: could not determine clock frequency", 486 __func__); 487 tc->tc_frequency = prop; 488 tc->tc_name = strdup(device_get_nameunit(dev), M_DEVBUF); 489 if (mode == SCHIZO_MODE_SCZ) 490 tc->tc_quality = SCHIZO_PERF_CNT_QLTY; 491 else 492 tc->tc_quality = -SCHIZO_PERF_CNT_QLTY; 493 tc->tc_priv = sc; 494 tc_init(tc); 495 } 496 497 /* 498 * Set up the IOMMU. Schizo, Tomatillo and XMITS all have 499 * one per PBM. Schizo and XMITS additionally have a streaming 500 * buffer, in Schizo version < 5 (i.e. revision < 2.3) it's 501 * affected by several errata though. However, except for context 502 * flushes, taking advantage of it should be okay even with those. 503 */ 504 memcpy(&sc->sc_dma_methods, &iommu_dma_methods, 505 sizeof(sc->sc_dma_methods)); 506 sc->sc_is.sis_sc = sc; 507 sc->sc_is.sis_is.is_flags = IOMMU_PRESERVE_PROM; 508 sc->sc_is.sis_is.is_pmaxaddr = IOMMU_MAXADDR(STX_IOMMU_BITS); 509 sc->sc_is.sis_is.is_sb[0] = sc->sc_is.sis_is.is_sb[1] = 0; 510 if (OF_getproplen(node, "no-streaming-cache") < 0) 511 sc->sc_is.sis_is.is_sb[0] = STX_PCI_STRBUF; 512 513 #define TSBCASE(x) \ 514 case (IOTSB_BASESZ << (x)) << (IO_PAGE_SHIFT - IOTTE_SHIFT): \ 515 tsbsize = (x); \ 516 break; \ 517 518 i = OF_getprop(node, "virtual-dma", (void *)prop_array, 519 sizeof(prop_array)); 520 if (i == -1 || i != sizeof(prop_array)) 521 schizo_iommu_init(sc, 7, -1); 522 else { 523 switch (prop_array[1]) { 524 TSBCASE(1); 525 TSBCASE(2); 526 TSBCASE(3); 527 TSBCASE(4); 528 TSBCASE(5); 529 TSBCASE(6); 530 TSBCASE(7); 531 TSBCASE(8); 532 default: 533 panic("%s: unsupported DVMA size 0x%x", 534 __func__, prop_array[1]); 535 /* NOTREACHED */ 536 } 537 schizo_iommu_init(sc, tsbsize, prop_array[0]); 538 } 539 540 #undef TSBCASE 541 542 /* Create our DMA tag. */ 543 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 544 sc->sc_is.sis_is.is_pmaxaddr, ~0, NULL, NULL, 545 sc->sc_is.sis_is.is_pmaxaddr, 0xff, 0xffffffff, 0, NULL, NULL, 546 &dmat) != 0) 547 panic("%s: could not create PCI DMA tag", __func__); 548 dmat->dt_cookie = &sc->sc_is; 549 dmat->dt_mt = &sc->sc_dma_methods; 550 551 if (ofw_pci_attach_common(dev, dmat, STX_IO_SIZE, STX_MEM_SIZE) != 0) 552 panic("%s: ofw_pci_attach_common() failed", __func__); 553 554 /* Clear any pending PCI error bits. */ 555 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, 556 STX_CS_FUNC, PCIR_STATUS, PCIB_READ_CONFIG(dev, 557 sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 558 2), 2); 559 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL)); 560 SCHIZO_PCI_SET(sc, STX_PCI_AFSR, SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR)); 561 562 /* 563 * Establish handlers for interesting interrupts... 564 * Someone at Sun clearly was smoking crack; with Schizos PCI 565 * bus error interrupts for one PBM can be routed to the other 566 * PBM though we obviously need to use the softc of the former 567 * as the argument for the interrupt handler and the softc of 568 * the latter as the argument for the interrupt controller. 569 */ 570 if (sc->sc_half == 0) { 571 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 || 572 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 573 INTMAP_VEC(sc->sc_ign, STX_PCIERR_A_INO)].iv_icarg)-> 574 sica_sc == osc)) 575 /* 576 * We are the driver for PBM A and either also 577 * registered the interrupt controller for us or 578 * the driver for PBM B has probed first and 579 * registered it for us. 580 */ 581 schizo_set_intr(sc, 0, STX_PCIERR_A_INO, 582 schizo_pci_bus); 583 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 && 584 osc != NULL) 585 /* 586 * We are the driver for PBM A but registered 587 * the interrupt controller for PBM B, i.e. the 588 * driver for PBM B attached first but couldn't 589 * set up a handler for PBM B. 590 */ 591 schizo_set_intr(osc, 0, STX_PCIERR_B_INO, 592 schizo_pci_bus); 593 } else { 594 if ((ino_bitmap & (1ULL << STX_PCIERR_B_INO)) != 0 || 595 (osc != NULL && ((struct schizo_icarg *)intr_vectors[ 596 INTMAP_VEC(sc->sc_ign, STX_PCIERR_B_INO)].iv_icarg)-> 597 sica_sc == osc)) 598 /* 599 * We are the driver for PBM B and either also 600 * registered the interrupt controller for us or 601 * the driver for PBM A has probed first and 602 * registered it for us. 603 */ 604 schizo_set_intr(sc, 0, STX_PCIERR_B_INO, 605 schizo_pci_bus); 606 if ((ino_bitmap & (1ULL << STX_PCIERR_A_INO)) != 0 && 607 osc != NULL) 608 /* 609 * We are the driver for PBM B but registered 610 * the interrupt controller for PBM A, i.e. the 611 * driver for PBM A attached first but couldn't 612 * set up a handler for PBM A. 613 */ 614 schizo_set_intr(osc, 0, STX_PCIERR_A_INO, 615 schizo_pci_bus); 616 } 617 if ((ino_bitmap & (1ULL << STX_UE_INO)) != 0) 618 schizo_set_intr(sc, 1, STX_UE_INO, schizo_ue); 619 if ((ino_bitmap & (1ULL << STX_CE_INO)) != 0) 620 schizo_set_intr(sc, 2, STX_CE_INO, schizo_ce); 621 if ((ino_bitmap & (1ULL << STX_BUS_INO)) != 0) 622 schizo_set_intr(sc, 3, STX_BUS_INO, schizo_host_bus); 623 624 /* 625 * According to the Schizo Errata I-13, consistent DMA flushing/ 626 * syncing is FUBAR in version < 5 (i.e. revision < 2.3) bridges, 627 * so we can't use it and need to live with the consequences. With 628 * Schizo version >= 5, CDMA flushing/syncing is usable but requires 629 * the workaround described in Schizo Errata I-23. With Tomatillo 630 * and XMITS, CDMA flushing/syncing works as expected, Tomatillo 631 * version <= 4 (i.e. revision <= 2.3) bridges additionally require 632 * a block store after a write to TOMXMS_PCI_DMA_SYNC_PEND though. 633 */ 634 if ((sc->sc_mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 5) || 635 sc->sc_mode == SCHIZO_MODE_TOM || 636 sc->sc_mode == SCHIZO_MODE_XMS) { 637 if (sc->sc_mode == SCHIZO_MODE_SCZ) { 638 sc->sc_dma_methods.dm_dmamap_sync = 639 schizo_dmamap_sync; 640 sc->sc_cdma_state = SCHIZO_CDMA_STATE_IDLE; 641 /* 642 * Some firmware versions include the CDMA interrupt 643 * at RID 4 but most don't. With the latter we add 644 * it ourselves at the spare RID 5. 645 */ 646 i = INTINO(bus_get_resource_start(dev, SYS_RES_IRQ, 647 4)); 648 if (i == STX_CDMA_A_INO || i == STX_CDMA_B_INO) { 649 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 650 (void)schizo_get_intrmap(sc, i, 651 &sc->sc_cdma_map, &sc->sc_cdma_clr); 652 schizo_set_intr(sc, 4, i, schizo_cdma); 653 } else { 654 i = STX_CDMA_A_INO + sc->sc_half; 655 sc->sc_cdma_vec = INTMAP_VEC(sc->sc_ign, i); 656 if (bus_set_resource(dev, SYS_RES_IRQ, 5, 657 sc->sc_cdma_vec, 1) != 0) 658 panic("%s: failed to add CDMA " 659 "interrupt", __func__); 660 j = schizo_intr_register(sc, i); 661 if (j != 0) 662 panic("%s: could not register " 663 "interrupt controller for CDMA " 664 "(%d)", __func__, j); 665 (void)schizo_get_intrmap(sc, i, 666 &sc->sc_cdma_map, &sc->sc_cdma_clr); 667 schizo_set_intr(sc, 5, i, schizo_cdma); 668 } 669 } else { 670 if (sc->sc_mode == SCHIZO_MODE_XMS) 671 mtx_init(&sc->sc_sync_mtx, "pcib_sync_mtx", 672 NULL, MTX_SPIN); 673 sc->sc_sync_val = 1ULL << (STX_PCIERR_A_INO + 674 sc->sc_half); 675 sc->sc_dma_methods.dm_dmamap_sync = 676 ichip_dmamap_sync; 677 } 678 if (sc->sc_mode == SCHIZO_MODE_TOM && sc->sc_ver <= 4) 679 sc->sc_flags |= SCHIZO_FLAGS_BSWAR; 680 } 681 682 /* 683 * Set the latency timer register as this isn't always done by the 684 * firmware. 685 */ 686 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, 687 STX_CS_FUNC, PCIR_LATTIMER, OFW_PCI_LATENCY, 1); 688 689 #define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \ 690 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \ 691 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \ 692 (name), CTLFLAG_RD, (arg), 0, (desc)) 693 694 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce, 695 "DMA correctable errors"); 696 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal, 697 "PCI bus non-fatal errors"); 698 699 #undef SCHIZO_SYSCTL_ADD_UINT 700 701 device_add_child(dev, "pci", -1); 702 return (bus_generic_attach(dev)); 703 } 704 705 static void 706 schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino, 707 driver_filter_t handler) 708 { 709 u_long vec; 710 int rid; 711 712 rid = index; 713 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev, 714 SYS_RES_IRQ, &rid, RF_ACTIVE); 715 if (sc->sc_irq_res[index] == NULL || 716 INTINO(vec = rman_get_start(sc->sc_irq_res[index])) != ino || 717 INTIGN(vec) != sc->sc_ign || 718 intr_vectors[vec].iv_ic != &schizo_ic || 719 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index], 720 INTR_TYPE_MISC | INTR_BRIDGE, handler, NULL, sc, 721 &sc->sc_ihand[index]) != 0) 722 panic("%s: failed to set up interrupt %d", __func__, index); 723 } 724 725 static int 726 schizo_intr_register(struct schizo_softc *sc, u_int ino) 727 { 728 struct schizo_icarg *sica; 729 bus_addr_t intrclr, intrmap; 730 int error; 731 732 if (schizo_get_intrmap(sc, ino, &intrmap, &intrclr) == 0) 733 return (ENXIO); 734 sica = malloc(sizeof(*sica), M_DEVBUF, M_NOWAIT); 735 if (sica == NULL) 736 return (ENOMEM); 737 sica->sica_sc = sc; 738 sica->sica_map = intrmap; 739 sica->sica_clr = intrclr; 740 #ifdef SCHIZO_DEBUG 741 device_printf(sc->sc_dev, "intr map (INO %d) %#lx: %#lx, clr: %#lx\n", 742 ino, (u_long)intrmap, (u_long)SCHIZO_PCI_READ_8(sc, intrmap), 743 (u_long)intrclr); 744 #endif 745 error = (intr_controller_register(INTMAP_VEC(sc->sc_ign, ino), 746 &schizo_ic, sica)); 747 if (error != 0) 748 free(sica, M_DEVBUF); 749 return (error); 750 } 751 752 static int 753 schizo_get_intrmap(struct schizo_softc *sc, u_int ino, 754 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr) 755 { 756 bus_addr_t intrclr, intrmap; 757 uint64_t mr; 758 759 /* 760 * XXX we only look for INOs rather than INRs since the firmware 761 * may not provide the IGN and the IGN is constant for all devices 762 * on that PCI controller. 763 */ 764 765 if (ino > STX_MAX_INO) { 766 device_printf(sc->sc_dev, "out of range INO %d requested\n", 767 ino); 768 return (0); 769 } 770 771 intrmap = STX_PCI_IMAP_BASE + (ino << 3); 772 intrclr = STX_PCI_ICLR_BASE + (ino << 3); 773 mr = SCHIZO_PCI_READ_8(sc, intrmap); 774 if (INTINO(mr) != ino) { 775 device_printf(sc->sc_dev, 776 "interrupt map entry does not match INO (%d != %d)\n", 777 (int)INTINO(mr), ino); 778 return (0); 779 } 780 781 if (intrmapptr != NULL) 782 *intrmapptr = intrmap; 783 if (intrclrptr != NULL) 784 *intrclrptr = intrclr; 785 return (1); 786 } 787 788 /* 789 * Interrupt handlers 790 */ 791 static int 792 schizo_pci_bus(void *arg) 793 { 794 struct schizo_softc *sc = arg; 795 uint64_t afar, afsr, csr, iommu, xstat; 796 uint32_t status; 797 u_int fatal; 798 799 fatal = 0; 800 801 mtx_lock_spin(sc->sc_mtx); 802 803 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR); 804 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR); 805 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL); 806 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU); 807 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 808 xstat = SCHIZO_PCI_READ_8(sc, XMS_PCI_X_ERR_STAT); 809 else 810 xstat = 0; 811 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus, 812 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2); 813 814 /* 815 * IOMMU errors are only fatal on Tomatillo and there also only if 816 * target abort was not signaled. 817 */ 818 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 && 819 (iommu & TOM_PCI_IOMMU_ERR) != 0 && 820 ((status & PCIM_STATUS_STABORT) == 0 || 821 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR && 822 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 && 823 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0))) 824 fatal = 1; 825 else if ((status & PCIM_STATUS_STABORT) != 0) 826 fatal = 1; 827 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR | 828 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT | 829 PCIM_STATUS_MDPERR)) != 0 || 830 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR | 831 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR | 832 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 || 833 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA | 834 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO | 835 STX_PCI_AFSR_P_UNUS)) != 0) 836 fatal = 1; 837 if (xstat & (XMS_PCI_X_ERR_STAT_P_SC_DSCRD | 838 XMS_PCI_X_ERR_STAT_P_SC_TTO | XMS_PCI_X_ERR_STAT_P_SDSTAT | 839 XMS_PCI_X_ERR_STAT_P_SMMU | XMS_PCI_X_ERR_STAT_P_CDSTAT | 840 XMS_PCI_X_ERR_STAT_P_CMMU | XMS_PCI_X_ERR_STAT_PERR_RCV)) 841 fatal = 1; 842 if (fatal == 0) 843 sc->sc_stats_pci_non_fatal++; 844 845 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx " 846 "PCI CSR %#llx IOMMU %#llx PCI-X %#llx STATUS %#x\n", 847 'A' + sc->sc_half, (unsigned long long)afar, 848 (unsigned long long)afsr, (unsigned long long)csr, 849 (unsigned long long)iommu, (unsigned long long)xstat, status); 850 851 /* Clear the error bits that we caught. */ 852 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_ops.sc_pci_secbus, STX_CS_DEVICE, 853 STX_CS_FUNC, PCIR_STATUS, status, 2); 854 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr); 855 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr); 856 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu); 857 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0) 858 SCHIZO_PCI_WRITE_8(sc, XMS_PCI_X_ERR_STAT, xstat); 859 860 mtx_unlock_spin(sc->sc_mtx); 861 862 if (fatal != 0) 863 panic("%s: fatal PCI bus error", 864 device_get_nameunit(sc->sc_dev)); 865 return (FILTER_HANDLED); 866 } 867 868 static int 869 schizo_ue(void *arg) 870 { 871 struct schizo_softc *sc = arg; 872 uint64_t afar, afsr; 873 int i; 874 875 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR); 876 for (i = 0; i < 1000; i++) 877 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 878 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 879 break; 880 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx", 881 device_get_nameunit(sc->sc_dev), (unsigned long long)afar, 882 (unsigned long long)afsr); 883 return (FILTER_HANDLED); 884 } 885 886 static int 887 schizo_ce(void *arg) 888 { 889 struct schizo_softc *sc = arg; 890 uint64_t afar, afsr; 891 int i; 892 893 mtx_lock_spin(sc->sc_mtx); 894 895 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR); 896 for (i = 0; i < 1000; i++) 897 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) & 898 STX_CTRL_CE_AFSR_ERRPNDG) == 0) 899 break; 900 sc->sc_stats_dma_ce++; 901 device_printf(sc->sc_dev, 902 "correctable DMA error AFAR %#llx AFSR %#llx\n", 903 (unsigned long long)afar, (unsigned long long)afsr); 904 905 /* Clear the error bits that we caught. */ 906 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr); 907 908 mtx_unlock_spin(sc->sc_mtx); 909 910 return (FILTER_HANDLED); 911 } 912 913 static int 914 schizo_host_bus(void *arg) 915 { 916 struct schizo_softc *sc = arg; 917 uint64_t errlog; 918 919 errlog = SCHIZO_CTRL_READ_8(sc, STX_CTRL_BUS_ERRLOG); 920 panic("%s: %s error %#llx", device_get_nameunit(sc->sc_dev), 921 sc->sc_mode == SCHIZO_MODE_TOM ? "JBus" : "Safari", 922 (unsigned long long)errlog); 923 return (FILTER_HANDLED); 924 } 925 926 static int 927 schizo_cdma(void *arg) 928 { 929 struct schizo_softc *sc = arg; 930 931 atomic_cmpset_32(&sc->sc_cdma_state, SCHIZO_CDMA_STATE_PENDING, 932 SCHIZO_CDMA_STATE_RECEIVED); 933 return (FILTER_HANDLED); 934 } 935 936 static void 937 schizo_iommu_init(struct schizo_softc *sc, int tsbsize, uint32_t dvmabase) 938 { 939 940 /* Punch in our copies. */ 941 sc->sc_is.sis_is.is_bustag = rman_get_bustag(sc->sc_mem_res[STX_PCI]); 942 sc->sc_is.sis_is.is_bushandle = 943 rman_get_bushandle(sc->sc_mem_res[STX_PCI]); 944 sc->sc_is.sis_is.is_iommu = STX_PCI_IOMMU; 945 sc->sc_is.sis_is.is_dtag = STX_PCI_IOMMU_TLB_TAG_DIAG; 946 sc->sc_is.sis_is.is_ddram = STX_PCI_IOMMU_TLB_DATA_DIAG; 947 sc->sc_is.sis_is.is_dqueue = STX_PCI_IOMMU_QUEUE_DIAG; 948 sc->sc_is.sis_is.is_dva = STX_PCI_IOMMU_SVADIAG; 949 sc->sc_is.sis_is.is_dtcmp = STX_PCI_IOMMU_TLB_CMP_DIAG; 950 951 iommu_init(device_get_nameunit(sc->sc_dev), 952 (struct iommu_state *)&sc->sc_is, tsbsize, dvmabase, 0); 953 } 954 955 static int 956 schizo_maxslots(device_t dev) 957 { 958 struct schizo_softc *sc; 959 960 sc = device_get_softc(dev); 961 if (sc->sc_mode == SCHIZO_MODE_SCZ) 962 return (sc->sc_half == 0 ? 4 : 6); 963 964 /* XXX: is this correct? */ 965 return (PCI_SLOTMAX); 966 } 967 968 static uint32_t 969 schizo_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 970 int width) 971 { 972 struct schizo_softc *sc; 973 974 sc = device_get_softc(dev); 975 /* 976 * The Schizo bridges contain a dupe of their header at 0x80. 977 */ 978 if (sc->sc_mode == SCHIZO_MODE_SCZ && 979 bus == sc->sc_ops.sc_pci_secbus && slot == STX_CS_DEVICE && 980 func == STX_CS_FUNC && reg + width > 0x80) 981 return (0); 982 983 return (ofw_pci_read_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus, 984 slot, func, reg), bus, slot, func, reg, width)); 985 } 986 987 static void 988 schizo_write_config(device_t dev, u_int bus, u_int slot, u_int func, 989 u_int reg, uint32_t val, int width) 990 { 991 992 ofw_pci_write_config_common(dev, PCI_REGMAX, STX_CONF_OFF(bus, slot, 993 func, reg), bus, slot, func, reg, val, width); 994 } 995 996 static int 997 schizo_route_interrupt(device_t bridge, device_t dev, int pin) 998 { 999 ofw_pci_intr_t mintr; 1000 1001 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin); 1002 if (!PCI_INTERRUPT_VALID(mintr)) 1003 device_printf(bridge, 1004 "could not route pin %d for device %d.%d\n", 1005 pin, pci_get_slot(dev), pci_get_function(dev)); 1006 return (mintr); 1007 } 1008 1009 static void 1010 schizo_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1011 { 1012 struct timeval cur, end; 1013 struct schizo_iommu_state *sis = dt->dt_cookie; 1014 struct schizo_softc *sc = sis->sis_sc; 1015 int i, res; 1016 #ifdef INVARIANTS 1017 register_t pil; 1018 #endif 1019 1020 if ((map->dm_flags & DMF_STREAMED) != 0) { 1021 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1022 return; 1023 } 1024 1025 if ((map->dm_flags & DMF_LOADED) == 0) 1026 return; 1027 1028 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1029 /* 1030 * Note that in order to allow this function to be called from 1031 * filters we would need to use a spin mutex for serialization 1032 * but given that these disable interrupts we have to emulate 1033 * one. 1034 */ 1035 critical_enter(); 1036 KASSERT((rdpr(pstate) & PSTATE_IE) != 0, 1037 ("%s: interrupts disabled", __func__)); 1038 KASSERT((pil = rdpr(pil)) <= PIL_BRIDGE, 1039 ("%s: PIL too low (%ld)", __func__, pil)); 1040 for (; atomic_cmpset_acq_32(&sc->sc_cdma_state, 1041 SCHIZO_CDMA_STATE_IDLE, SCHIZO_CDMA_STATE_PENDING) == 0;) 1042 ; 1043 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_map, 1044 INTMAP_ENABLE(sc->sc_cdma_vec, PCPU_GET(mid))); 1045 for (i = 0; i < SCHIZO_CDMA_TRIES; i++) { 1046 if (i > 0) 1047 printf("%s: try %d\n", __func__, i); 1048 SCHIZO_PCI_WRITE_8(sc, sc->sc_cdma_clr, 1049 INTCLR_RECEIVED); 1050 microuptime(&cur); 1051 end.tv_sec = SCHIZO_CDMA_TIMEOUT; 1052 end.tv_usec = 0; 1053 timevaladd(&end, &cur); 1054 for (; (res = atomic_cmpset_rel_32(&sc->sc_cdma_state, 1055 SCHIZO_CDMA_STATE_RECEIVED, 1056 SCHIZO_CDMA_STATE_IDLE)) == 0 && 1057 timevalcmp(&cur, &end, <=);) 1058 microuptime(&cur); 1059 if (res != 0) 1060 break; 1061 } 1062 if (res == 0) 1063 panic("%s: DMA does not sync", __func__); 1064 critical_exit(); 1065 } 1066 1067 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1068 membar(Sync); 1069 } 1070 1071 static void 1072 ichip_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op) 1073 { 1074 struct timeval cur, end; 1075 struct schizo_iommu_state *sis = dt->dt_cookie; 1076 struct schizo_softc *sc = sis->sis_sc; 1077 uint64_t reg; 1078 1079 if ((map->dm_flags & DMF_STREAMED) != 0) { 1080 iommu_dma_methods.dm_dmamap_sync(dt, map, op); 1081 return; 1082 } 1083 1084 if ((map->dm_flags & DMF_LOADED) == 0) 1085 return; 1086 1087 if ((op & BUS_DMASYNC_POSTREAD) != 0) { 1088 if (sc->sc_mode == SCHIZO_MODE_XMS) 1089 mtx_lock_spin(&sc->sc_sync_mtx); 1090 SCHIZO_PCI_WRITE_8(sc, TOMXMS_PCI_DMA_SYNC_PEND, 1091 sc->sc_sync_val); 1092 microuptime(&cur); 1093 end.tv_sec = 1; 1094 end.tv_usec = 0; 1095 timevaladd(&end, &cur); 1096 for (; ((reg = SCHIZO_PCI_READ_8(sc, 1097 TOMXMS_PCI_DMA_SYNC_PEND)) & sc->sc_sync_val) != 0 && 1098 timevalcmp(&cur, &end, <=);) 1099 microuptime(&cur); 1100 if ((reg & sc->sc_sync_val) != 0) 1101 panic("%s: DMA does not sync", __func__); 1102 if (sc->sc_mode == SCHIZO_MODE_XMS) 1103 mtx_unlock_spin(&sc->sc_sync_mtx); 1104 else if ((sc->sc_flags & SCHIZO_FLAGS_BSWAR) != 0) { 1105 ofw_pci_dmamap_sync_stst_order_common(); 1106 return; 1107 } 1108 } 1109 1110 if ((op & BUS_DMASYNC_PREWRITE) != 0) 1111 membar(Sync); 1112 } 1113 1114 static void 1115 schizo_intr_enable(void *arg) 1116 { 1117 struct intr_vector *iv = arg; 1118 struct schizo_icarg *sica = iv->iv_icarg; 1119 1120 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, 1121 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 1122 } 1123 1124 static void 1125 schizo_intr_disable(void *arg) 1126 { 1127 struct intr_vector *iv = arg; 1128 struct schizo_icarg *sica = iv->iv_icarg; 1129 1130 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, iv->iv_vec); 1131 } 1132 1133 static void 1134 schizo_intr_assign(void *arg) 1135 { 1136 struct intr_vector *iv = arg; 1137 struct schizo_icarg *sica = iv->iv_icarg; 1138 1139 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_map, INTMAP_TID( 1140 SCHIZO_PCI_READ_8(sica->sica_sc, sica->sica_map), iv->iv_mid)); 1141 } 1142 1143 static void 1144 schizo_intr_clear(void *arg) 1145 { 1146 struct intr_vector *iv = arg; 1147 struct schizo_icarg *sica = iv->iv_icarg; 1148 1149 SCHIZO_PCI_WRITE_8(sica->sica_sc, sica->sica_clr, INTCLR_IDLE); 1150 } 1151 1152 static int 1153 schizo_setup_intr(device_t dev, device_t child, struct resource *ires, 1154 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 1155 void **cookiep) 1156 { 1157 struct schizo_softc *sc; 1158 u_long vec; 1159 int error; 1160 1161 sc = device_get_softc(dev); 1162 /* 1163 * Make sure the vector is fully specified. 1164 */ 1165 vec = rman_get_start(ires); 1166 if (INTIGN(vec) != sc->sc_ign) { 1167 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 1168 return (EINVAL); 1169 } 1170 1171 if (intr_vectors[vec].iv_ic == &schizo_ic) { 1172 /* 1173 * Ensure we use the right softc in case the interrupt 1174 * is routed to our companion PBM for some odd reason. 1175 */ 1176 sc = ((struct schizo_icarg *)intr_vectors[vec].iv_icarg)-> 1177 sica_sc; 1178 } else if (intr_vectors[vec].iv_ic == NULL) { 1179 /* 1180 * Work around broken firmware which misses entries in 1181 * the ino-bitmap. 1182 */ 1183 error = schizo_intr_register(sc, INTINO(vec)); 1184 if (error != 0) { 1185 device_printf(dev, "could not register interrupt " 1186 "controller for vector 0x%lx (%d)\n", vec, error); 1187 return (error); 1188 } 1189 if (bootverbose) 1190 device_printf(dev, "belatedly registered as " 1191 "interrupt controller for vector 0x%lx\n", vec); 1192 } else { 1193 device_printf(dev, 1194 "invalid interrupt controller for vector 0x%lx\n", vec); 1195 return (EINVAL); 1196 } 1197 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr, 1198 arg, cookiep)); 1199 } 1200 1201 static struct resource * 1202 schizo_alloc_resource(device_t bus, device_t child, int type, int *rid, 1203 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 1204 { 1205 struct schizo_softc *sc; 1206 1207 if (type == SYS_RES_IRQ) { 1208 sc = device_get_softc(bus); 1209 start = end = INTMAP_VEC(sc->sc_ign, end); 1210 } 1211 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end, 1212 count, flags)); 1213 } 1214 1215 static void 1216 schizo_setup_device(device_t bus, device_t child) 1217 { 1218 struct schizo_softc *sc; 1219 uint64_t reg; 1220 int capreg; 1221 1222 sc = device_get_softc(bus); 1223 /* 1224 * Disable bus parking in order to work around a bus hang caused by 1225 * Casinni/Skyhawk combinations. 1226 */ 1227 if (OF_getproplen(ofw_bus_get_node(child), "pci-req-removal") >= 0) 1228 SCHIZO_PCI_SET(sc, STX_PCI_CTRL, SCHIZO_PCI_READ_8(sc, 1229 STX_PCI_CTRL) & ~STX_PCI_CTRL_ARB_PARK); 1230 1231 if (sc->sc_mode == SCHIZO_MODE_XMS) { 1232 /* XMITS NCPQ WAR: set outstanding split transactions to 1. */ 1233 if ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 && 1234 (pci_read_config(child, PCIR_HDRTYPE, 1) & 1235 PCIM_HDRTYPE) != PCIM_HDRTYPE_BRIDGE && 1236 pci_find_cap(child, PCIY_PCIX, &capreg) == 0) 1237 pci_write_config(child, capreg + PCIXR_COMMAND, 1238 pci_read_config(child, capreg + PCIXR_COMMAND, 1239 2) & 0x7c, 2); 1240 /* XMITS 3.x WAR: set BUGCNTL iff value is unexpected. */ 1241 if (sc->sc_mrev >= 4) { 1242 reg = ((sc->sc_flags & SCHIZO_FLAGS_XMODE) != 0 ? 1243 0xa0UL : 0xffUL) << XMS_PCI_X_DIAG_BUGCNTL_SHIFT; 1244 if ((SCHIZO_PCI_READ_8(sc, XMS_PCI_X_DIAG) & 1245 XMS_PCI_X_DIAG_BUGCNTL_MASK) != reg) 1246 SCHIZO_PCI_SET(sc, XMS_PCI_X_DIAG, reg); 1247 } 1248 } 1249 } 1250 1251 static u_int 1252 schizo_get_timecount(struct timecounter *tc) 1253 { 1254 struct schizo_softc *sc; 1255 1256 sc = tc->tc_priv; 1257 return ((SCHIZO_CTRL_READ_8(sc, STX_CTRL_PERF_CNT) & 1258 (STX_CTRL_PERF_CNT_MASK << STX_CTRL_PERF_CNT_CNT0_SHIFT)) >> 1259 STX_CTRL_PERF_CNT_CNT0_SHIFT); 1260 }
Cache object: 6ea424dd42637e0f2b208b42c49a4651
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