Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/sparc64/pci/schizoreg.h
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1 /*- 2 * Copyright (c) 2002 Jason L. Wright (jason@thought.net) 3 * Copyright (c) 2005 by Marius Strobl <marius@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULLAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * from: OpenBSD: schizoreg.h,v 1.8 2005/05/19 18:28:59 mickey Exp 28 * $FreeBSD: releng/8.0/sys/sparc64/pci/schizoreg.h 185133 2008-11-20 18:44:09Z marius $ 29 */ 30 31 #ifndef _SPARC64_PCI_SCHIZOREG_H_ 32 #define _SPARC64_PCI_SCHIZOREG_H_ 33 34 #define STX_NINTR 5 /* 4 via OFW + 1 CDMA */ 35 #define STX_NRANGE 4 36 #define SCZ_NREG 3 37 #define TOM_NREG 4 38 39 #define STX_PCI 0 40 #define STX_CTRL 1 41 #define STX_PCICFG 2 42 #define STX_ICON 3 43 44 /* PCI configuration and status registers */ 45 #define STX_PCI_IOMMU 0x00200 46 #define STX_PCI_IOMMU_CTXFLUSH 0x00218 47 #define STX_PCI_IMAP_BASE 0x01000 48 #define STX_PCI_ICLR_BASE 0x01400 49 #define STX_PCI_INTR_RETRY_TIM 0x01a00 50 #define SCZ_PCI_DMA_SYNC 0x01a08 51 #define TOM_PCI_DMA_SYNC_COMP 0x01a10 52 #define TOMXMS_PCI_DMA_SYNC_PEND 0x01a18 53 #define STX_PCI_CTRL 0x02000 54 #define STX_PCI_AFSR 0x02010 55 #define STX_PCI_AFAR 0x02018 56 #define STX_PCI_DIAG 0x02020 57 #define TOM_PCI_IOC_CSR 0x02248 58 #define TOM_PCI_IOC_TAG 0x02290 59 #define TOM_PCI_IOC_DATA 0x02290 60 #define STX_PCI_STRBUF 0x02800 61 #define STX_PCI_STRBUF_CTXFLUSH 0x02818 62 #define STX_PCI_IOMMU_SVADIAG 0x0a400 63 #define STX_PCI_IOMMU_TLB_CMP_DIAG 0x0a408 64 #define STX_PCI_IOMMU_QUEUE_DIAG 0x0a500 65 #define STX_PCI_IOMMU_TLB_TAG_DIAG 0x0a580 66 #define STX_PCI_IOMMU_TLB_DATA_DIAG 0x0a600 67 #define STX_PCI_IOBIO_DIAG 0x0a808 68 #define STX_PCI_STRBUF_CTXMATCH 0x10000 69 70 /* PCI IOMMU control registers */ 71 #define TOM_PCI_IOMMU_ERR_BAD_VA 0x0000000010000000ULL 72 #define TOM_PCI_IOMMU_ERR_ILLTSBTBW 0x0000000008000000ULL 73 #define TOM_PCI_IOMMU_ECC_ERR 0x0000000006000000ULL 74 #define TOM_PCI_IOMMU_TIMEOUT_ERR 0x0000000004000000ULL 75 #define TOM_PCI_IOMMU_INVALID_ERR 0x0000000002000000ULL 76 #define TOM_PCI_IOMMU_PROTECTION_ERR 0x0000000000000000ULL 77 #define TOM_PCI_IOMMU_ERRMASK \ 78 (TOM_PCI_IOMMU_PROTECTION_ERR | TOM_PCI_IOMMU_INVALID_ERR | \ 79 TOM_PCI_IOMMU_TIMEOUT_ERR | TOM_PCI_IOMMU_ECC_ERR) 80 #define TOM_PCI_IOMMU_ERR 0x0000000001000000ULL 81 82 /* PCI control/status register */ 83 #define SCZ_PCI_CTRL_BUS_UNUS 0x8000000000000000ULL 84 #define TOM_PCI_CTRL_DTO_ERR 0x4000000000000000ULL 85 #define TOM_PCI_CTRL_DTO_IEN 0x2000000000000000ULL 86 #define SCZ_PCI_CTRL_ESLCK 0x0008000000000000ULL 87 #define SCZ_PCI_CTRL_ERRSLOT 0x0007000000000000ULL 88 #define STX_PCI_CTRL_TTO_ERR 0x0000004000000000ULL 89 #define STX_PCI_CTRL_RTRY_ERR 0x0000002000000000ULL 90 #define STX_PCI_CTRL_MMU_ERR 0x0000001000000000ULL 91 #define SCZ_PCI_CTRL_SBH_ERR 0x0000000800000000ULL 92 #define STX_PCI_CTRL_SERR 0x0000000400000000ULL 93 #define SCZ_PCI_CTRL_PCISPD 0x0000000200000000ULL 94 #define TOM_PCI_CTRL_PRM 0x0000000040000000ULL 95 #define TOM_PCI_CTRL_PRO 0x0000000020000000ULL 96 #define TOM_PCI_CTRL_PRL 0x0000000010000000ULL 97 #define STX_PCI_CTRL_PTO 0x0000000003000000ULL 98 #define STX_PCI_CTRL_MMU_IEN 0x0000000000080000ULL 99 #define STX_PCI_CTRL_SBH_IEN 0x0000000000040000ULL 100 #define STX_PCI_CTRL_ERR_IEN 0x0000000000020000ULL 101 #define STX_PCI_CTRL_ARB_PARK 0x0000000000010000ULL 102 #define SCZ_PCI_CTRL_PCIRST 0x0000000000000100ULL 103 #define STX_PCI_CTRL_ARB_MASK 0x00000000000000ffULL 104 105 /* PCI asynchronous fault status register */ 106 #define STX_PCI_AFSR_P_MA 0x8000000000000000ULL 107 #define STX_PCI_AFSR_P_TA 0x4000000000000000ULL 108 #define STX_PCI_AFSR_P_RTRY 0x2000000000000000ULL 109 #define STX_PCI_AFSR_P_PERR 0x1000000000000000ULL 110 #define STX_PCI_AFSR_P_TTO 0x0800000000000000ULL 111 #define STX_PCI_AFSR_P_UNUS 0x0400000000000000ULL 112 #define STX_PCI_AFSR_S_MA 0x0200000000000000ULL 113 #define STX_PCI_AFSR_S_TA 0x0100000000000000ULL 114 #define STX_PCI_AFSR_S_RTRY 0x0080000000000000ULL 115 #define STX_PCI_AFSR_S_PERR 0x0040000000000000ULL 116 #define STX_PCI_AFSR_S_TTO 0x0020000000000000ULL 117 #define STX_PCI_AFSR_S_UNUS 0x0010000000000000ULL 118 #define STX_PCI_AFSR_DWMASK 0x0000030000000000ULL 119 #define STX_PCI_AFSR_BMASK 0x000000ff00000000ULL 120 #define STX_PCI_AFSR_BLK 0x0000000080000000ULL 121 #define STX_PCI_AFSR_CFG 0x0000000040000000ULL 122 #define STX_PCI_AFSR_MEM 0x0000000020000000ULL 123 #define STX_PCI_AFSR_IO 0x0000000010000000ULL 124 125 /* PCI diagnostic register */ 126 #define SCZ_PCI_DIAG_BADECC_DIS 0x0000000000000400ULL 127 #define STX_PCI_DIAG_BYPASS_DIS 0x0000000000000200ULL 128 #define STX_PCI_DIAG_TTO_DIS 0x0000000000000100ULL 129 #define SCZ_PCI_DIAG_RTRYARB_DIS 0x0000000000000080ULL 130 #define STX_PCI_DIAG_RETRY_DIS 0x0000000000000040ULL 131 #define STX_PCI_DIAG_INTRSYNC_DIS 0x0000000000000020ULL 132 #define STX_PCI_DIAG_DMAPARITY_INV 0x0000000000000008ULL 133 #define STX_PCI_DIAG_PIODPARITY_INV 0x0000000000000004ULL 134 #define STX_PCI_DIAG_PIOAPARITY_INV 0x0000000000000002ULL 135 136 /* Tomatillo I/O cache register */ 137 #define TOM_PCI_IOC_PW 0x0000000000080000ULL 138 #define TOM_PCI_IOC_PRM 0x0000000000040000ULL 139 #define TOM_PCI_IOC_PRO 0x0000000000020000ULL 140 #define TOM_PCI_IOC_PRL 0x0000000000010000ULL 141 #define TOM_PCI_IOC_PRM_LEN 0x000000000000c000ULL 142 #define TOM_PCI_IOC_PRM_LEN_SHIFT 14 143 #define TOM_PCI_IOC_PRO_LEN 0x0000000000003000ULL 144 #define TOM_PCI_IOC_PRO_LEN_SHIFT 12 145 #define TOM_PCI_IOC_PRL_LEN 0x0000000000000c00ULL 146 #define TOM_PCI_IOC_PRL_LEN_SHIFT 10 147 #define TOM_PCI_IOC_PREF_OFF 0x0000000000000038ULL 148 #define TOM_PCI_IOC_PREF_OFF_SHIFT 3 149 #define TOM_PCI_IOC_CPRM 0x0000000000000004ULL 150 #define TOM_PCI_IOC_CPRO 0x0000000000000002ULL 151 #define TOM_PCI_IOC_CPRL 0x0000000000000001ULL 152 153 /* Controller configuration and status registers */ 154 /* Note that these are shared on Schizo but per-PBM on Tomatillo. */ 155 #define STX_CTRL_BUS_ERRLOG 0x00018 156 #define STX_CTRL_ECCCTRL 0x00020 157 #define STX_CTRL_UE_AFSR 0x00030 158 #define STX_CTRL_UE_AFAR 0x00038 159 #define STX_CTRL_CE_AFSR 0x00040 160 #define STX_CTRL_CE_AFAR 0x00048 161 #define STX_CTRL_PERF 0x07000 162 #define STX_CTRL_PERF_CNT 0x07008 163 164 /* Safari/JBus error log register */ 165 #define STX_CTRL_BUS_ERRLOG_BADCMD 0x4000000000000000ULL 166 #define SCZ_CTRL_BUS_ERRLOG_SSMDIS 0x2000000000000000ULL 167 #define SCZ_CTRL_BUS_ERRLOG_BADMA 0x1000000000000000ULL 168 #define SCZ_CTRL_BUS_ERRLOG_BADMB 0x0800000000000000ULL 169 #define SCZ_CTRL_BUS_ERRLOG_BADMC 0x0400000000000000ULL 170 #define TOM_CTRL_BUS_ERRLOG_SNOOP_GR 0x0000000000200000ULL 171 #define TOM_CTRL_BUS_ERRLOG_SNOOP_PCI 0x0000000000100000ULL 172 #define TOM_CTRL_BUS_ERRLOG_SNOOP_RD 0x0000000000080000ULL 173 #define TOM_CTRL_BUS_ERRLOG_SNOOP_RDS 0x0000000000020000ULL 174 #define TOM_CTRL_BUS_ERRLOG_SNOOP_RDSA 0x0000000000010000ULL 175 #define TOM_CTRL_BUS_ERRLOG_SNOOP_OWN 0x0000000000008000ULL 176 #define TOM_CTRL_BUS_ERRLOG_SNOOP_RDO 0x0000000000004000ULL 177 #define SCZ_CTRL_BUS_ERRLOG_CPU1PS 0x0000000000002000ULL 178 #define TOM_CTRL_BUS_ERRLOG_WDATA_PERR 0x0000000000002000ULL 179 #define SCZ_CTRL_BUS_ERRLOG_CPU1PB 0x0000000000001000ULL 180 #define TOM_CTRL_BUS_ERRLOG_CTRL_PERR 0x0000000000001000ULL 181 #define SCZ_CTRL_BUS_ERRLOG_CPU0PS 0x0000000000000800ULL 182 #define TOM_CTRL_BUS_ERRLOG_SNOOP_ERR 0x0000000000000800ULL 183 #define SCZ_CTRL_BUS_ERRLOG_CPU0PB 0x0000000000000400ULL 184 #define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_B 0x0000000000000400ULL 185 #define SCZ_CTRL_BUS_ERRLOG_CIQTO 0x0000000000000200ULL 186 #define SCZ_CTRL_BUS_ERRLOG_LPQTO 0x0000000000000100ULL 187 #define TOM_CTRL_BUS_ERRLOG_JBUS_ILL_C 0x0000000000000100ULL 188 #define SCZ_CTRL_BUS_ERRLOG_SFPQTO 0x0000000000000080ULL 189 #define SCZ_CTRL_BUS_ERRLOG_UFPQTO 0x0000000000000040ULL 190 #define TOM_CTRL_BUS_ERRLOG_RD_PERR 0x0000000000000040ULL 191 #define STX_CTRL_BUS_ERRLOG_APERR 0x0000000000000020ULL 192 #define STX_CTRL_BUS_ERRLOG_UNMAP 0x0000000000000010ULL 193 #define STX_CTRL_BUS_ERRLOG_BUSERR 0x0000000000000004ULL 194 #define STX_CTRL_BUS_ERRLOG_TIMEOUT 0x0000000000000002ULL 195 #define SCZ_CTRL_BUS_ERRLOG_ILL 0x0000000000000001ULL 196 197 /* ECC control register */ 198 #define STX_CTRL_ECCCTRL_EE 0x8000000000000000ULL 199 #define STX_CTRL_ECCCTRL_UE 0x4000000000000000ULL 200 #define STX_CTRL_ECCCTRL_CE 0x2000000000000000ULL 201 202 /* Uncorrectable error asynchronous fault status register */ 203 #define STX_CTRL_UE_AFSR_P_PIO 0x8000000000000000ULL 204 #define STX_CTRL_UE_AFSR_P_DRD 0x4000000000000000ULL 205 #define STX_CTRL_UE_AFSR_P_DWR 0x2000000000000000ULL 206 #define STX_CTRL_UE_AFSR_S_PIO 0x1000000000000000ULL 207 #define STX_CTRL_UE_AFSR_S_DRD 0x0800000000000000ULL 208 #define STX_CTRL_UE_AFSR_S_DWR 0x0400000000000000ULL 209 #define STX_CTRL_UE_AFSR_ERRPNDG 0x0300000000000000ULL 210 #define STX_CTRL_UE_AFSR_BMASK 0x000003ff00000000ULL 211 #define STX_CTRL_UE_AFSR_QOFF 0x00000000c0000000ULL 212 #define STX_CTRL_UE_AFSR_AID 0x000000001f000000ULL 213 #define STX_CTRL_UE_AFSR_PARTIAL 0x0000000000800000ULL 214 #define STX_CTRL_UE_AFSR_OWNEDIN 0x0000000000400000ULL 215 #define STX_CTRL_UE_AFSR_MTAGSYND 0x00000000000f0000ULL 216 #define STX_CTRL_UE_AFSR_MTAG 0x000000000000e000ULL 217 #define STX_CTRL_UE_AFSR_ECCSYND 0x00000000000001ffULL 218 219 /* Correctable error asynchronous fault status register */ 220 #define STX_CTRL_CE_AFSR_P_PIO 0x8000000000000000ULL 221 #define STX_CTRL_CE_AFSR_P_DRD 0x4000000000000000ULL 222 #define STX_CTRL_CE_AFSR_P_DWR 0x2000000000000000ULL 223 #define STX_CTRL_CE_AFSR_S_PIO 0x1000000000000000ULL 224 #define STX_CTRL_CE_AFSR_S_DRD 0x0800000000000000ULL 225 #define STX_CTRL_CE_AFSR_S_DWR 0x0400000000000000ULL 226 #define STX_CTRL_CE_AFSR_ERRPNDG 0x0300000000000000ULL 227 #define STX_CTRL_CE_AFSR_BMASK 0x000003ff00000000ULL 228 #define STX_CTRL_CE_AFSR_QOFF 0x00000000c0000000ULL 229 #define STX_CTRL_CE_AFSR_AID 0x000000001f000000ULL 230 #define STX_CTRL_CE_AFSR_PARTIAL 0x0000000000800000ULL 231 #define STX_CTRL_CE_AFSR_OWNEDIN 0x0000000000400000ULL 232 #define STX_CTRL_CE_AFSR_MTAGSYND 0x00000000000f0000ULL 233 #define STX_CTRL_CE_AFSR_MTAG 0x000000000000e000ULL 234 #define STX_CTRL_CE_AFSR_ECCSYND 0x00000000000001ffULL 235 236 /* 237 * Safari/JBus performance control register 238 * NB: for Tomatillo only events 0x00 through 0x08 are documented as 239 * implemented. 240 */ 241 #define SCZ_CTRL_PERF_ZDATA_OUT 0x0000000000000016ULL 242 #define SCZ_CTRL_PERF_ZDATA_IN 0x0000000000000015ULL 243 #define SCZ_CTRL_PERF_ORQFULL 0x0000000000000014ULL 244 #define SCZ_CTRL_PERF_DVMA_WR 0x0000000000000013ULL 245 #define SCZ_CTRL_PERF_DVMA_RD 0x0000000000000012ULL 246 #define SCZ_CTRL_PERF_CYCPSESYS 0x0000000000000011ULL 247 #define STX_CTRL_PERF_PCI_B 0x000000000000000fULL 248 #define STX_CTRL_PERF_PCI_A 0x000000000000000eULL 249 #define STX_CTRL_PERF_UPA 0x000000000000000dULL 250 #define STX_CTRL_PERF_PIOINTRNL 0x000000000000000cULL 251 #define TOM_CTRL_PERF_WRI_WRIS 0x000000000000000bULL 252 #define STX_CTRL_PERF_INTRS 0x000000000000000aULL 253 #define STX_CTRL_PERF_PRTLWRMRGBUF 0x0000000000000009ULL 254 #define STX_CTRL_PERF_FGN_IO_HITS 0x0000000000000008ULL 255 #define STX_CTRL_PERF_FGN_IO_TRNS 0x0000000000000007ULL 256 #define STX_CTRL_PERF_OWN_CHRNT_HITS 0x0000000000000006ULL 257 #define STX_CTRL_PERF_OWN_CHRNT_TRNS 0x0000000000000005ULL 258 #define SCZ_CTRL_PERF_FGN_CHRNT_HITS 0x0000000000000004ULL 259 #define STX_CTRL_PERF_FGN_CHRNT_TRNS 0x0000000000000003ULL 260 #define STX_CTRL_PERF_CYCLES_PAUSE 0x0000000000000002ULL 261 #define STX_CTRL_PERF_BUSCYC 0x0000000000000001ULL 262 #define STX_CTRL_PERF_DIS 0x0000000000000000ULL 263 #define STX_CTRL_PERF_CNT1_SHIFT 11 264 #define STX_CTRL_PERF_CNT0_SHIFT 4 265 266 /* Safari/JBus performance counter register */ 267 #define STX_CTRL_PERF_CNT_MASK 0x00000000ffffffffULL 268 #define STX_CTRL_PERF_CNT_CNT1_SHIFT 32 269 #define STX_CTRL_PERF_CNT_CNT0_SHIFT 0 270 271 /* INO defines */ 272 #define STX_FB0_INO 0x2a /* FB0 int. shared w/ UPA64s */ 273 #define STX_FB1_INO 0x2b /* FB1 int. shared w/ UPA64s */ 274 #define STX_UE_INO 0x30 /* uncorrectable error */ 275 #define STX_CE_INO 0x31 /* correctable error */ 276 #define STX_PCIERR_A_INO 0x32 /* PCI bus A error */ 277 #define STX_PCIERR_B_INO 0x33 /* PCI bus B error */ 278 #define STX_BUS_INO 0x34 /* Safari/JBus error */ 279 #define STX_CDMA_A_INO 0x35 /* PCI bus A CDMA */ 280 #define STX_CDMA_B_INO 0x36 /* PCI bus B CDMA */ 281 #define STX_MAX_INO 0x37 282 283 /* Device space defines */ 284 #define STX_CONF_SIZE 0x1000000 285 #define STX_CONF_BUS_SHIFT 16 286 #define STX_CONF_DEV_SHIFT 11 287 #define STX_CONF_FUNC_SHIFT 8 288 #define STX_CONF_REG_SHIFT 0 289 #define STX_IO_SIZE 0x1000000 290 #define STX_MEM_SIZE 0x100000000 291 292 #define STX_CONF_OFF(bus, slot, func, reg) \ 293 (((bus) << STX_CONF_BUS_SHIFT) | \ 294 ((slot) << STX_CONF_DEV_SHIFT) | \ 295 ((func) << STX_CONF_FUNC_SHIFT) | \ 296 ((reg) << STX_CONF_REG_SHIFT)) 297 298 /* Definitions for the Schizo/Tomatillo configuration space */ 299 #define STX_CS_DEVICE 0 /* bridge CS device number */ 300 #define STX_CS_FUNC 0 /* brdige CS function number */ 301 302 /* Non-Standard registers in the configration space */ 303 /* 304 * NB: for Tomatillo the secondary and subordinate bus number registers 305 * apparently are read-only although documented otherwise; writing to 306 * them just triggers a PCI bus error interrupt or has no effect at best. 307 */ 308 #define STX_CSR_SECBUS 0x40 /* secondary bus number */ 309 #define STX_CSR_SUBBUS 0x41 /* subordinate bus number */ 310 311 /* Width of the physical addresses the IOMMU translates to */ 312 #define STX_IOMMU_BITS 43 313 314 #endif /* !_SPARC64_PCI_SCHIZOREG_H_ */
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