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sys/sparc64/sbus/lsi64854.c
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1 /*- 2 * Copyright (c) 2004 Scott Long 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 /* $NetBSD: lsi64854.c,v 1.25 2005/02/27 00:27:02 perry Exp $ */ 29 30 /*- 31 * Copyright (c) 1998 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Paul Kranenburg. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by the NetBSD 48 * Foundation, Inc. and its contributors. 49 * 4. Neither the name of The NetBSD Foundation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 55 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 56 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 57 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 58 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 59 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 60 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 61 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 62 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 63 * POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 #include <sys/cdefs.h> 67 __FBSDID("$FreeBSD$"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/bus.h> 72 #include <sys/kernel.h> 73 #include <sys/resource.h> 74 #include <sys/lock.h> 75 #include <sys/mutex.h> 76 77 #include <machine/bus.h> 78 79 #include <cam/cam.h> 80 #include <cam/cam_ccb.h> 81 #include <cam/scsi/scsi_all.h> 82 83 #include <sparc64/sbus/lsi64854reg.h> 84 #include <sparc64/sbus/lsi64854var.h> 85 86 #include <dev/esp/ncr53c9xreg.h> 87 #include <dev/esp/ncr53c9xvar.h> 88 89 #ifdef DEBUG 90 #define LDB_SCSI 1 91 #define LDB_ENET 2 92 #define LDB_PP 4 93 #define LDB_ANY 0xff 94 int lsi64854debug = 0; 95 #define DPRINTF(a,x) do { if (lsi64854debug & (a)) printf x ; } while (0) 96 #else 97 #define DPRINTF(a,x) 98 #endif 99 100 #define MAX_DMA_SZ (16*1024*1024) 101 102 static void lsi64854_reset(struct lsi64854_softc *); 103 static void lsi64854_map_scsi(void *, bus_dma_segment_t *, int, int); 104 static int lsi64854_setup(struct lsi64854_softc *, caddr_t *, size_t *, 105 int, size_t *); 106 static int lsi64854_scsi_intr(void *); 107 static int lsi64854_enet_intr(void *); 108 static int lsi64854_setup_pp(struct lsi64854_softc *, caddr_t *, size_t *, 109 int, size_t *); 110 static int lsi64854_pp_intr(void *); 111 112 /* 113 * Finish attaching this DMA device. 114 * Front-end must fill in these fields: 115 * sc_regs 116 * sc_burst 117 * sc_channel (one of SCSI, ENET, PP) 118 * sc_client (one of SCSI, ENET, PP `soft_c' pointers) 119 */ 120 int 121 lsi64854_attach(struct lsi64854_softc *sc) 122 { 123 uint32_t csr; 124 int error; 125 126 /* Indirect functions */ 127 switch (sc->sc_channel) { 128 case L64854_CHANNEL_SCSI: 129 sc->intr = lsi64854_scsi_intr; 130 sc->setup = lsi64854_setup; 131 break; 132 case L64854_CHANNEL_ENET: 133 sc->intr = lsi64854_enet_intr; 134 break; 135 case L64854_CHANNEL_PP: 136 sc->intr = lsi64854_pp_intr; 137 sc->setup = lsi64854_setup_pp; 138 break; 139 default: 140 device_printf(sc->sc_dev, "unknown channel\n"); 141 } 142 sc->reset = lsi64854_reset; 143 144 /* Allocate a dmamap */ 145 error = bus_dma_tag_create( 146 sc->sc_parent_dmat, /* parent */ 147 1, 0, /* alignment, boundary */ 148 BUS_SPACE_MAXADDR, /* lowaddr */ 149 BUS_SPACE_MAXADDR, /* highaddr */ 150 NULL, NULL, /* filter, filterarg */ 151 MAX_DMA_SZ, /* maxsize */ 152 1, /* nsegments */ 153 MAX_DMA_SZ, /* maxsegsize */ 154 BUS_DMA_ALLOCNOW, /* flags */ 155 NULL, NULL, /* lockfunc, lockarg */ 156 &sc->sc_buffer_dmat); 157 if (error != 0) { 158 device_printf(sc->sc_dev, "cannot allocate buffer DMA tag\n"); 159 return (error); 160 } 161 162 error = bus_dmamap_create(sc->sc_buffer_dmat, 0, &sc->sc_dmamap); 163 if (error != 0) { 164 device_printf(sc->sc_dev, "DMA map create failed\n"); 165 bus_dma_tag_destroy(sc->sc_buffer_dmat); 166 return (error); 167 } 168 169 csr = L64854_GCSR(sc); 170 sc->sc_rev = csr & L64854_DEVID; 171 if (sc->sc_rev == DMAREV_HME) 172 return (0); 173 device_printf(sc->sc_dev, "DMA rev. "); 174 switch (sc->sc_rev) { 175 case DMAREV_0: 176 printf(""); 177 break; 178 case DMAREV_ESC: 179 printf("ESC"); 180 break; 181 case DMAREV_1: 182 printf("1"); 183 break; 184 case DMAREV_PLUS: 185 printf("1+"); 186 break; 187 case DMAREV_2: 188 printf("2"); 189 break; 190 default: 191 printf("unknown (0x%x)", sc->sc_rev); 192 } 193 194 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr)); 195 printf("\n"); 196 197 return (0); 198 } 199 200 int 201 lsi64854_detach(struct lsi64854_softc *sc) 202 { 203 204 if (sc->setup) 205 bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); 206 bus_dmamap_destroy(sc->sc_buffer_dmat, sc->sc_dmamap); 207 bus_dma_tag_destroy(sc->sc_buffer_dmat); 208 209 return (0); 210 } 211 212 /* 213 * DMAWAIT waits while condition is true 214 */ 215 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \ 216 int count = 500000; \ 217 while ((COND) && --count > 0) DELAY(1); \ 218 if (count == 0) { \ 219 printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \ 220 (u_long)L64854_GCSR(SC)); \ 221 if (DONTPANIC) \ 222 printf(MSG); \ 223 else \ 224 panic(MSG); \ 225 } \ 226 } while (0) 227 228 #define DMA_DRAIN(sc, dontpanic) do { \ 229 uint32_t csr; \ 230 /* \ 231 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 232 * and "drain" bits while it is still thinking about a \ 233 * request. \ 234 * other revs: D_ESC_R_PEND bit reads as 0 \ 235 */ \ 236 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 237 if (sc->sc_rev != DMAREV_HME) { \ 238 /* \ 239 * Select drain bit based on revision \ 240 * also clears errors and D_TC flag \ 241 */ \ 242 csr = L64854_GCSR(sc); \ 243 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \ 244 csr |= D_ESC_DRAIN; \ 245 else \ 246 csr |= L64854_INVALIDATE; \ 247 \ 248 L64854_SCSR(sc,csr); \ 249 } \ 250 /* \ 251 * Wait for draining to finish \ 252 * rev0 & rev1 call this PACKCNT \ 253 */ \ 254 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\ 255 } while(0) 256 257 #define DMA_FLUSH(sc, dontpanic) do { \ 258 uint32_t csr; \ 259 /* \ 260 * DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \ 261 * and "drain" bits while it is still thinking about a \ 262 * request. \ 263 * other revs: D_ESC_R_PEND bit reads as 0 \ 264 */ \ 265 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\ 266 csr = L64854_GCSR(sc); \ 267 csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \ 268 csr |= L64854_INVALIDATE; /* XXX FAS ? */ \ 269 L64854_SCSR(sc,csr); \ 270 } while(0) 271 272 static void 273 lsi64854_reset(struct lsi64854_softc *sc) 274 { 275 uint32_t csr; 276 277 DMA_FLUSH(sc, 1); 278 csr = L64854_GCSR(sc); 279 280 DPRINTF(LDB_ANY, ("%s: csr 0x%x\n", __func__, csr)); 281 282 /* 283 * XXX is sync needed? 284 if (sc->sc_dmamap->dm_nsegs > 0) 285 bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); 286 */ 287 288 if (sc->sc_rev == DMAREV_HME) 289 L64854_SCSR(sc, csr | D_HW_RESET_FAS366); 290 291 csr |= L64854_RESET; /* reset DMA */ 292 L64854_SCSR(sc, csr); 293 DELAY(200); /* > 10 Sbus clocks(?) */ 294 295 /*DMAWAIT1(sc); why was this here? */ 296 csr = L64854_GCSR(sc); 297 csr &= ~L64854_RESET; /* de-assert reset line */ 298 L64854_SCSR(sc, csr); 299 DELAY(5); /* allow a few ticks to settle */ 300 301 csr = L64854_GCSR(sc); 302 csr |= L64854_INT_EN; /* enable interrupts */ 303 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) { 304 if (sc->sc_rev == DMAREV_HME) 305 csr |= D_TWO_CYCLE; 306 else 307 csr |= D_FASTER; 308 } 309 310 /* Set burst */ 311 switch (sc->sc_rev) { 312 case DMAREV_HME: 313 case DMAREV_2: 314 csr &= ~L64854_BURST_SIZE; 315 if (sc->sc_burst == 32) 316 csr |= L64854_BURST_32; 317 else if (sc->sc_burst == 16) 318 csr |= L64854_BURST_16; 319 else 320 csr |= L64854_BURST_0; 321 break; 322 case DMAREV_ESC: 323 csr |= D_ESC_AUTODRAIN; /* Auto-drain */ 324 if (sc->sc_burst == 32) 325 csr &= ~D_ESC_BURST; 326 else 327 csr |= D_ESC_BURST; 328 break; 329 default: 330 break; 331 } 332 L64854_SCSR(sc, csr); 333 334 if (sc->sc_rev == DMAREV_HME) { 335 bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, 0); 336 sc->sc_dmactl = csr; 337 } 338 sc->sc_active = 0; 339 340 DPRINTF(LDB_ANY, ("%s: done, csr 0x%x\n", __func__, csr)); 341 } 342 343 static void 344 lsi64854_map_scsi(void *arg, bus_dma_segment_t *segs, int nseg, int error) 345 { 346 struct lsi64854_softc *sc; 347 348 sc = (struct lsi64854_softc *)arg; 349 350 if (nseg != 1) 351 panic("%s: cannot map %d segments\n", __func__, nseg); 352 353 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, 354 sc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 355 bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, 356 segs[0].ds_addr); 357 } 358 359 #define DMAMAX(a) (MAX_DMA_SZ - ((a) & (MAX_DMA_SZ-1))) 360 /* 361 * setup a DMA transfer 362 */ 363 static int 364 lsi64854_setup(struct lsi64854_softc *sc, caddr_t *addr, size_t *len, 365 int datain, size_t *dmasize) 366 { 367 long bcnt; 368 uint32_t csr; 369 370 DMA_FLUSH(sc, 0); 371 372 #if 0 373 DMACSR(sc) &= ~D_INT_EN; 374 #endif 375 sc->sc_dmaaddr = addr; 376 sc->sc_dmalen = len; 377 sc->sc_datain = datain; 378 379 /* 380 * The rules say we cannot transfer more than the limit 381 * of this DMA chip (64k for old and 16Mb for new), 382 * and we cannot cross a 16Mb boundary. 383 */ 384 *dmasize = sc->sc_dmasize = 385 ulmin(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 386 387 DPRINTF(LDB_ANY, ("%s: dmasize=%ld\n", __func__, (long)sc->sc_dmasize)); 388 389 /* 390 * XXX what length? 391 */ 392 if (sc->sc_rev == DMAREV_HME) { 393 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET); 394 L64854_SCSR(sc, sc->sc_dmactl); 395 396 bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, 397 *dmasize); 398 } 399 400 /* Program the DMA address */ 401 if (sc->sc_dmasize) 402 if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap, 403 *sc->sc_dmaaddr, sc->sc_dmasize, lsi64854_map_scsi, sc, 0)) 404 panic("%s: cannot allocate DVMA address", __func__); 405 406 if (sc->sc_rev == DMAREV_ESC) { 407 /* DMA ESC chip bug work-around */ 408 bcnt = sc->sc_dmasize; 409 if (((bcnt + (long)*sc->sc_dmaaddr) & PAGE_MASK_8K) != 0) 410 bcnt = roundup(bcnt, PAGE_SIZE_8K); 411 bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, 412 bcnt); 413 } 414 415 /* Setup DMA control register */ 416 csr = L64854_GCSR(sc); 417 418 if (datain) 419 csr |= L64854_WRITE; 420 else 421 csr &= ~L64854_WRITE; 422 csr |= L64854_INT_EN; 423 424 if (sc->sc_rev == DMAREV_HME) 425 csr |= (D_DSBL_SCSI_DRN | D_EN_DMA); 426 427 L64854_SCSR(sc, csr); 428 429 return (0); 430 } 431 432 /* 433 * Pseudo (chained) interrupt from the esp driver to kick the 434 * current running DMA transfer. Called from ncr53c9x_intr() 435 * for now. 436 * 437 * return 1 if it was a DMA continue. 438 */ 439 static int 440 lsi64854_scsi_intr(void *arg) 441 { 442 struct lsi64854_softc *sc = arg; 443 struct ncr53c9x_softc *nsc = sc->sc_client; 444 int trans, resid; 445 uint32_t csr; 446 447 csr = L64854_GCSR(sc); 448 449 DPRINTF(LDB_SCSI, ("%s: addr 0x%x, csr %b\n", __func__, 450 bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR), csr, 451 DDMACSR_BITS)); 452 453 if (csr & (D_ERR_PEND|D_SLAVE_ERR)) { 454 device_printf(sc->sc_dev, "error: csr=%b\n", csr, DDMACSR_BITS); 455 csr &= ~D_EN_DMA; /* Stop DMA */ 456 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 457 csr |= D_INVALIDATE|D_SLAVE_ERR; 458 L64854_SCSR(sc, csr); 459 return (-1); 460 } 461 462 /* This is an "assertion" :) */ 463 if (sc->sc_active == 0) 464 panic("%s: DMA wasn't active", __func__); 465 466 DMA_DRAIN(sc, 0); 467 468 /* DMA has stopped */ 469 csr &= ~D_EN_DMA; 470 L64854_SCSR(sc, csr); 471 sc->sc_active = 0; 472 473 if (sc->sc_dmasize == 0) { 474 /* A "Transfer Pad" operation completed */ 475 DPRINTF(LDB_SCSI, ("%s: discarded %d bytes (tcl=%d, tcm=%d)\n", 476 __func__, NCR_READ_REG(nsc, NCR_TCL) | 477 (NCR_READ_REG(nsc, NCR_TCM) << 8), 478 NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM))); 479 return (0); 480 } 481 482 resid = 0; 483 /* 484 * If a transfer onto the SCSI bus gets interrupted by the device 485 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 486 * as residual since the NCR53C9X counter registers get decremented 487 * as bytes are clocked into the FIFO. 488 */ 489 if (!(csr & D_WRITE) && 490 (resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 491 DPRINTF(LDB_SCSI, ("%s: empty esp FIFO of %d ", __func__, 492 resid)); 493 if (nsc->sc_rev == NCR_VARIANT_FAS366 && 494 (NCR_READ_REG(nsc, NCR_CFG3) & NCRFASCFG3_EWIDE)) 495 resid <<= 1; 496 } 497 498 if ((nsc->sc_espstat & NCRSTAT_TC) == 0) { 499 /* 500 * `Terminal count' is off, so read the residue 501 * out of the NCR53C9X counter registers. 502 */ 503 resid += (NCR_READ_REG(nsc, NCR_TCL) | 504 (NCR_READ_REG(nsc, NCR_TCM) << 8) | 505 ((nsc->sc_cfg2 & NCRCFG2_FE) ? 506 (NCR_READ_REG(nsc, NCR_TCH) << 16) : 0)); 507 508 if (resid == 0 && sc->sc_dmasize == 65536 && 509 (nsc->sc_cfg2 & NCRCFG2_FE) == 0) 510 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 511 resid = 65536; 512 } 513 514 trans = sc->sc_dmasize - resid; 515 if (trans < 0) { /* transfered < 0? */ 516 #if 0 517 /* 518 * This situation can happen in perfectly normal operation 519 * if the ESP is reselected while using DMA to select 520 * another target. As such, don't print the warning. 521 */ 522 device_printf(sc->sc_dev, "xfer (%d) > req (%d)\n", trans, 523 sc->sc_dmasize); 524 #endif 525 trans = sc->sc_dmasize; 526 } 527 528 DPRINTF(LDB_SCSI, ("%s: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 529 __func__, NCR_READ_REG(nsc, NCR_TCL), NCR_READ_REG(nsc, NCR_TCM), 530 (nsc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(nsc, NCR_TCH) : 0, 531 trans, resid)); 532 533 #if 0 /* XXX */ 534 if (sc->sc_dmamap->dm_nsegs > 0) { 535 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, 536 (csr & D_WRITE) != 0 ? BUS_DMASYNC_POSTREAD : 537 BUS_DMASYNC_POSTWRITE); 538 bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); 539 } 540 #endif 541 542 *sc->sc_dmalen -= trans; 543 *sc->sc_dmaaddr += trans; 544 545 #if 0 /* this is not normal operation just yet */ 546 if (*sc->sc_dmalen == 0 || nsc->sc_phase != nsc->sc_prevphase) 547 return (0); 548 549 /* and again */ 550 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE); 551 return (1); 552 #endif 553 return (0); 554 } 555 556 /* 557 * Pseudo (chained) interrupt to le driver to handle DMA errors. 558 */ 559 static int 560 lsi64854_enet_intr(void *arg) 561 { 562 struct lsi64854_softc *sc = arg; 563 uint32_t csr; 564 int i, rv; 565 566 csr = L64854_GCSR(sc); 567 568 /* If the DMA logic shows an interrupt, claim it */ 569 rv = ((csr & E_INT_PEND) != 0) ? 1 : 0; 570 571 if (csr & (E_ERR_PEND|E_SLAVE_ERR)) { 572 device_printf(sc->sc_dev, "error: csr=%b\n", csr, EDMACSR_BITS); 573 csr &= ~L64854_EN_DMA; /* Stop DMA */ 574 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 575 csr |= E_INVALIDATE|E_SLAVE_ERR; 576 L64854_SCSR(sc, csr); 577 /* Will be drained with the LE_C0_IDON interrupt. */ 578 sc->sc_dodrain = 1; 579 return (-1); 580 } 581 582 /* XXX - is this necessary with E_DSBL_WR_INVAL on? */ 583 if (sc->sc_dodrain) { 584 i = 10; 585 csr |= E_DRAIN; 586 L64854_SCSR(sc, csr); 587 while (i-- > 0 && (L64854_GCSR(sc) & E_DRAINING)) 588 DELAY(1); 589 sc->sc_dodrain = 0; 590 } 591 592 return (rv); 593 } 594 595 static void 596 lsi64854_map_pp(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 597 { 598 struct lsi64854_softc *sc; 599 600 sc = (struct lsi64854_softc *)arg; 601 602 if (nsegs != 1) 603 panic("%s: cannot map %d segments\n", __func__, nsegs); 604 605 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, sc->sc_datain ? 606 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 607 bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR, 608 segs[0].ds_addr); 609 610 bus_space_write_4(sc->sc_regt, sc->sc_regh, L64854_REG_CNT, 611 sc->sc_dmasize); 612 } 613 614 /* 615 * setup a DMA transfer 616 */ 617 static int 618 lsi64854_setup_pp(struct lsi64854_softc *sc, caddr_t *addr, size_t *len, 619 int datain, size_t *dmasize) 620 { 621 uint32_t csr; 622 623 DMA_FLUSH(sc, 0); 624 625 sc->sc_dmaaddr = addr; 626 sc->sc_dmalen = len; 627 sc->sc_datain = datain; 628 629 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", __func__, 630 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0)); 631 632 /* 633 * the rules say we cannot transfer more than the limit 634 * of this DMA chip (64k for old and 16Mb for new), 635 * and we cannot cross a 16Mb boundary. 636 */ 637 *dmasize = sc->sc_dmasize = 638 ulmin(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr)); 639 640 DPRINTF(LDB_PP, ("%s: dmasize=%ld\n", __func__, (long)sc->sc_dmasize)); 641 642 /* Program the DMA address */ 643 if (sc->sc_dmasize) 644 if (bus_dmamap_load(sc->sc_buffer_dmat, sc->sc_dmamap, 645 *sc->sc_dmaaddr, sc->sc_dmasize, lsi64854_map_pp, sc, 0)) 646 panic("%s: pp cannot allocate DVMA address", __func__); 647 648 /* Setup DMA control register */ 649 csr = L64854_GCSR(sc); 650 csr &= ~L64854_BURST_SIZE; 651 if (sc->sc_burst == 32) 652 csr |= L64854_BURST_32; 653 else if (sc->sc_burst == 16) 654 csr |= L64854_BURST_16; 655 else 656 csr |= L64854_BURST_0; 657 csr |= P_EN_DMA|P_INT_EN|P_EN_CNT; 658 #if 0 659 /* This bit is read-only in PP csr register */ 660 if (datain) 661 csr |= P_WRITE; 662 else 663 csr &= ~P_WRITE; 664 #endif 665 L64854_SCSR(sc, csr); 666 667 return (0); 668 } 669 670 /* 671 * Parallel port DMA interrupt. 672 */ 673 static int 674 lsi64854_pp_intr(void *arg) 675 { 676 struct lsi64854_softc *sc = arg; 677 int ret, trans, resid = 0; 678 uint32_t csr; 679 680 csr = L64854_GCSR(sc); 681 682 DPRINTF(LDB_PP, ("%s: addr 0x%x, csr %b\n", __func__, 683 bus_space_read_4(sc->sc_regt, sc->sc_regh, L64854_REG_ADDR), csr, 684 PDMACSR_BITS)); 685 686 if (csr & (P_ERR_PEND|P_SLAVE_ERR)) { 687 resid = bus_space_read_4(sc->sc_regt, sc->sc_regh, 688 L64854_REG_CNT); 689 device_printf(sc->sc_dev, "error: resid %d csr=%b\n", resid, 690 csr, PDMACSR_BITS); 691 csr &= ~P_EN_DMA; /* Stop DMA */ 692 /* Invalidate the queue; SLAVE_ERR bit is write-to-clear */ 693 csr |= P_INVALIDATE|P_SLAVE_ERR; 694 L64854_SCSR(sc, csr); 695 return (-1); 696 } 697 698 ret = (csr & P_INT_PEND) != 0; 699 700 if (sc->sc_active != 0) { 701 DMA_DRAIN(sc, 0); 702 resid = bus_space_read_4(sc->sc_regt, sc->sc_regh, 703 L64854_REG_CNT); 704 } 705 706 /* DMA has stopped */ 707 csr &= ~D_EN_DMA; 708 L64854_SCSR(sc, csr); 709 sc->sc_active = 0; 710 711 trans = sc->sc_dmasize - resid; 712 if (trans < 0) /* transfered < 0? */ 713 trans = sc->sc_dmasize; 714 *sc->sc_dmalen -= trans; 715 *sc->sc_dmaaddr += trans; 716 717 #if 0 /* XXX */ 718 if (sc->sc_dmamap->dm_nsegs > 0) { 719 bus_dmamap_sync(sc->sc_buffer_dmat, sc->sc_dmamap, 720 (csr & D_WRITE) != 0 ? BUS_DMASYNC_POSTREAD : 721 BUS_DMASYNC_POSTWRITE); 722 bus_dmamap_unload(sc->sc_buffer_dmat, sc->sc_dmamap); 723 } 724 #endif 725 726 return (ret != 0); 727 }
Cache object: 4b169d36f3645e6a4d981760a854a800
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