The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/sparc64/sbus/lsi64854reg.h

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    1 /*      $NetBSD: lsi64854reg.h,v 1.6 2008/04/28 20:23:50 martin Exp $ */
    2 
    3 /*-
    4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Paul Kranenburg.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   29  * POSSIBILITY OF SUCH DAMAGE.
   30  */
   31 
   32 /*      $FreeBSD: releng/10.4/sys/sparc64/sbus/lsi64854reg.h 219567 2011-03-12 14:33:32Z marius $ */
   33 
   34 /*
   35  * LSI 64854 DMA engine. Contains three independent channels
   36  * designed to interface with (a) a NCR539X SCSI controller,
   37  * (b) a AM7990 Ethernet controller, (c) Parallel port hardware..
   38  */
   39 
   40 /*
   41  * Register offsets to bus handle.
   42  */
   43 #define L64854_REG_CSR          0               /* Control bits */
   44 #define L64854_REG_ADDR         4               /* DMA Address */
   45 #define L64854_REG_CNT          8               /* DMA count */
   46 #define L64854_REG_CNT_MASK     0x00ffffff      /*   only 24 bits */
   47 #define L64854_REG_ENBAR        12              /* ENET Base register */
   48 #define L64854_REG_TEST         12              /* SCSI Test register */
   49 #define L64854_REG_HCR          16              /* PP Hardware Configuration */
   50 #define L64854_REG_OCR          18              /* PP Operation Configuration */
   51 #define L64854_REG_DR           20              /* PP Data register */
   52 #define L64854_REG_TCR          21              /* PP Transfer Control */
   53 #define L64854_REG_OR           22              /* PP Output register */
   54 #define L64854_REG_IR           23              /* PP Input register */
   55 #define L64854_REG_ICR          24              /* PP Interrupt Control */
   56 
   57 
   58 /*
   59  * Control bits common to all three channels.
   60  */
   61 #define L64854_INT_PEND 0x00000001      /* Interrupt pending */
   62 #define L64854_ERR_PEND 0x00000002      /* Error pending */
   63 #define L64854_DRAINING 0x0000000c      /* FIFO draining */
   64 #define L64854_INT_EN   0x00000010      /* Interrupt enable */
   65 #define L64854_INVALIDATE       0x00000020      /* Invalidate FIFO */
   66 #define L64854_SLAVE_ERR        0x00000040      /* Slave access size error */
   67 #define L64854_RESET    0x00000080      /* Reset device */
   68 #define L64854_WRITE    0x00000100      /* 1: xfer to memory */
   69 #define L64854_EN_DMA   0x00000200      /* enable DMA transfers */
   70 
   71 #define L64854_BURST_SIZE       0x000c0000      /* Read/write burst size */
   72 #define  L64854_BURST_0         0x00080000      /*   no bursts (SCSI-only) */
   73 #define  L64854_BURST_16        0x00000000      /*   16-byte bursts */
   74 #define  L64854_BURST_32        0x00040000      /*   32-byte bursts */
   75 #define  L64854_BURST_64        0x000c0000      /*   64-byte bursts (fas) */
   76 
   77 #define L64854_RST_FAS366       0x08000000      /* FAS366 hardware reset */
   78 
   79 #define L64854_DEVID            0xf0000000      /* device ID bits */
   80 
   81 /*
   82  * SCSI DMA control bits.
   83  */
   84 #define D_INT_PEND      L64854_INT_PEND /* interrupt pending */
   85 #define D_ERR_PEND      L64854_ERR_PEND /* error pending */
   86 #define D_DRAINING      L64854_DRAINING /* fifo draining */
   87 #define D_INT_EN        L64854_INT_EN   /* interrupt enable */
   88 #define D_INVALIDATE    L64854_INVALIDATE/* invalidate fifo */
   89 #define D_SLAVE_ERR     L64854_SLAVE_ERR/* slave access size error */
   90 #define D_RESET         L64854_RESET    /* reset scsi */
   91 #define D_WRITE         L64854_WRITE    /* 1 = dev -> mem */
   92 #define D_EN_DMA        L64854_EN_DMA   /* enable DMA requests */
   93 #define D_EN_CNT        0x00002000      /* enable byte counter */
   94 #define D_TC            0x00004000      /* terminal count */
   95 #define D_WIDE_EN       0x00008000      /* enable wide mode SBUS DMA (fas) */
   96 #define D_DSBL_CSR_DRN  0x00010000      /* disable fifo drain on csr */
   97 #define D_DSBL_SCSI_DRN 0x00020000      /* disable fifo drain on reg */
   98 
   99 #define D_DIAG          0x00100000      /* disable fifo drain on addr */
  100 #define D_TWO_CYCLE     0x00200000      /* 2 clocks per transfer */
  101 #define D_FASTER        0x00400000      /* 3 clocks per transfer */
  102 #define D_TCI_DIS       0x00800000      /* disable intr on D_TC */
  103 #define D_EN_NEXT       0x01000000      /* enable auto next address */
  104 #define D_DMA_ON        0x02000000      /* enable dma from scsi XXX */
  105 #define D_DSBL_PARITY_CHK \
  106                         0x02000000      /* disable checking for parity on bus (default 1:fas) */
  107 #define D_A_LOADED      0x04000000      /* address loaded */
  108 #define D_NA_LOADED     0x08000000      /* next address loaded */
  109 #define D_HW_RESET_FAS366 \
  110                         0x08000000      /* hardware reset FAS366 (fas) */
  111 #define D_DEV_ID        L64854_DEVID    /* device ID */
  112 #define  DMAREV_0       0x00000000      /* Sunray DMA */
  113 #define  DMAREV_ESC     0x40000000      /*  DMA ESC array */
  114 #define  DMAREV_1       0x80000000      /* 'DMA' */
  115 #define  DMAREV_PLUS    0x90000000      /* 'DMA+' */
  116 #define  DMAREV_2       0xa0000000      /* 'DMA2' */
  117 #define  DMAREV_HME     0xb0000000      /* 'HME'  */
  118 
  119 /*
  120  * revisions 0,1 and ESC have different bits.
  121  */
  122 #define D_ESC_DRAIN     0x00000040      /* rev0,1,esc: drain fifo */
  123 #define D_ESC_R_PEND    0x00000400      /* rev0,1: request pending */
  124 #define D_ESC_BURST     0x00000800      /* DMA ESC: 16 byte bursts */
  125 #define D_ESC_AUTODRAIN 0x00040000      /* DMA ESC: Auto-drain */
  126 
  127 #define DDMACSR_BITS    "\177\020"                              \
  128         "b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0"          \
  129         "b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0"           \
  130         "b\15ENCNT\0b\16TC\0\b\20DSBL_CSR_DRN\0"                \
  131         "b\21DSBL_SCSI_DRN\0f\22\2BURST\0b\25TWOCYCLE\0"        \
  132         "b\26FASTER\0b\27TCIDIS\0b\30ENNXT\0b\031DMAON\0"       \
  133         "b\32ALOADED\0b\33NALOADED\0"
  134 
  135 
  136 /*
  137  * ENET DMA control bits.
  138  */
  139 #define E_INT_PEND      L64854_INT_PEND /* interrupt pending */
  140 #define E_ERR_PEND      L64854_ERR_PEND /* error pending */
  141 #define E_DRAINING      L64854_DRAINING /* fifo draining */
  142 #define E_INT_EN        L64854_INT_EN   /* interrupt enable */
  143 #define E_INVALIDATE    L64854_INVALIDATE/* invalidate fifo */
  144 #define E_SLAVE_ERR     L64854_SLAVE_ERR/* slave access size error */
  145 #define E_RESET         L64854_RESET    /* reset ENET */
  146 #define E_reserved1     0x00000300      /* */
  147 #define E_DRAIN         0x00000400      /* force Ecache drain */
  148 #define E_DSBL_WR_DRN   0x00000800      /* disable Ecache drain on .. */
  149 #define E_DSBL_RD_DRN   0x00001000      /* disable Ecache drain on .. */
  150 #define E_reserved2     0x00006000      /* */
  151 #define E_ILACC         0x00008000      /* ... */
  152 #define E_DSBL_BUF_WR   0x00010000      /* no buffering of slave writes */
  153 #define E_DSBL_WR_INVAL 0x00020000      /* no Ecache invalidate on slave writes */
  154 
  155 #define E_reserved3     0x00100000      /* */
  156 #define E_LOOP_TEST     0x00200000      /* loopback mode */
  157 #define E_TP_AUI        0x00400000      /* 1 for TP, 0 for AUI */
  158 #define E_reserved4     0x0c800000      /* */
  159 #define E_DEV_ID        L64854_DEVID    /* ID bits */
  160 
  161 #define EDMACSR_BITS    "\177\020"                              \
  162         "b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0"          \
  163         "b\06SLVERR\0b\07RST\0b\10WRITE\0b\12DRAIN\0"           \
  164         "b\13DSBL_WR_DRN\0b\14DSBL_RD_DRN\0b\17ILACC\0"         \
  165         "b\20DSBL_BUF_WR\0b\21DSBL_WR_INVAL\0"                  \
  166         "b\25LOOPTEST\0b\26TP\0"
  167 
  168 /*
  169  * PP DMA control bits.
  170  */
  171 #define P_INT_PEND      L64854_INT_PEND /* interrupt pending */
  172 #define P_ERR_PEND      L64854_ERR_PEND /* error pending */
  173 #define P_DRAINING      L64854_DRAINING /* fifo draining */
  174 #define P_INT_EN        L64854_INT_EN   /* interrupt enable */
  175 #define P_INVALIDATE    L64854_INVALIDATE/* invalidate fifo */
  176 #define P_SLAVE_ERR     L64854_SLAVE_ERR/* slave access size error */
  177 #define P_RESET         L64854_RESET    /* reset PP */
  178 #define P_WRITE         L64854_WRITE    /* 1: xfer to memory */
  179 #define P_EN_DMA        L64854_EN_DMA   /* enable DMA transfers */
  180 #define P_reserved1     0x00001c00      /* */
  181 #define P_EN_CNT        0x00002000      /* enable counter */
  182 #define P_TC            0x00004000      /* terminal count */
  183 #define P_reserved2     0x00038000      /* */
  184 
  185 #define P_DIAG          0x00100000      /* ... */
  186 #define P_reserved3     0x00600000      /* */
  187 #define P_TCI_DIS       0x00800000      /* no interrupt on terminal count */
  188 #define P_EN_NEXT       0x01000000      /* enable DMA chaining */
  189 #define P_DMA_ON        0x02000000      /* DMA xfers enabled */
  190 #define P_A_LOADED      0x04000000      /* addr and byte count valid */
  191 #define P_NA_LOADED     0x08000000      /* next addr & count valid but not used */
  192 #define P_DEV_ID        L64854_DEVID    /* ID bits */
  193 
  194 #define PDMACSR_BITS    "\177\020"                              \
  195         "b\00INT\0b\01ERR\0f\02\02DRAINING\0b\04IEN\0"          \
  196         "b\06SLVERR\0b\07RST\0b\10WRITE\0b\11ENDMA\0"           \
  197         "b\15ENCNT\0b\16TC\0\b\24DIAG\0b\27TCIDIS\0"            \
  198         "b\30ENNXT\0b\031DMAON\0b\32ALOADED\0b\33NALOADED\0"

Cache object: bc89e8dd98abe24eaa4c7a3148c45d26


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