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sys/sparc64/sbus/sbus.c
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1 /*- 2 * Copyright (c) 1998 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Paul Kranenburg. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 /*- 37 * Copyright (c) 1992, 1993 38 * The Regents of the University of California. All rights reserved. 39 * 40 * This software was developed by the Computer Systems Engineering group 41 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 42 * contributed to Berkeley. 43 * 44 * All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the University of 47 * California, Lawrence Berkeley Laboratory. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 1. Redistributions of source code must retain the above copyright 53 * notice, this list of conditions and the following disclaimer. 54 * 2. Redistributions in binary form must reproduce the above copyright 55 * notice, this list of conditions and the following disclaimer in the 56 * documentation and/or other materials provided with the distribution. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 */ 73 /*- 74 * Copyright (c) 1999 Eduardo Horvath 75 * Copyright (c) 2002 by Thomas Moestl <tmm@FreeBSD.org>. 76 * All rights reserved. 77 * 78 * Redistribution and use in source and binary forms, with or without 79 * modification, are permitted provided that the following conditions 80 * are met: 81 * 1. Redistributions of source code must retain the above copyright 82 * notice, this list of conditions and the following disclaimer. 83 * 84 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 85 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 87 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 90 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 91 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 92 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 93 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 94 * SUCH DAMAGE. 95 * 96 * from: @(#)sbus.c 8.1 (Berkeley) 6/11/93 97 * from: NetBSD: sbus.c,v 1.46 2001/10/07 20:30:41 eeh Exp 98 */ 99 100 #include <sys/cdefs.h> 101 __FBSDID("$FreeBSD: releng/6.4/sys/sparc64/sbus/sbus.c 182211 2008-08-26 18:18:30Z marius $"); 102 103 /* 104 * SBus support. 105 */ 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/bus.h> 110 #include <sys/kernel.h> 111 #include <sys/malloc.h> 112 #include <sys/module.h> 113 #include <sys/pcpu.h> 114 #include <sys/reboot.h> 115 116 #include <dev/ofw/ofw_bus.h> 117 #include <dev/ofw/openfirm.h> 118 119 #include <machine/bus.h> 120 #include <machine/bus_private.h> 121 #include <machine/iommureg.h> 122 #include <machine/bus_common.h> 123 #include <machine/intr_machdep.h> 124 #include <machine/nexusvar.h> 125 #include <machine/ofw_upa.h> 126 #include <machine/resource.h> 127 128 #include <sys/rman.h> 129 130 #include <machine/iommuvar.h> 131 132 #include <sparc64/sbus/ofw_sbus.h> 133 #include <sparc64/sbus/sbusreg.h> 134 #include <sparc64/sbus/sbusvar.h> 135 136 struct sbus_devinfo { 137 int sdi_burstsz; 138 int sdi_clockfreq; 139 char *sdi_compat; /* PROM compatible */ 140 char *sdi_model; /* PROM model */ 141 char *sdi_name; /* PROM name */ 142 phandle_t sdi_node; /* PROM node */ 143 int sdi_slot; 144 char *sdi_type; /* PROM device_type */ 145 146 struct resource_list sdi_rl; 147 }; 148 149 /* Range descriptor, allocated for each sc_range. */ 150 struct sbus_rd { 151 bus_addr_t rd_poffset; 152 bus_addr_t rd_pend; 153 int rd_slot; 154 bus_addr_t rd_coffset; 155 bus_addr_t rd_cend; 156 struct rman rd_rman; 157 bus_space_handle_t rd_bushandle; 158 struct resource *rd_res; 159 }; 160 161 struct sbus_softc { 162 bus_space_tag_t sc_bustag; 163 bus_space_handle_t sc_bushandle; 164 bus_dma_tag_t sc_dmatag; 165 bus_dma_tag_t sc_cdmatag; 166 bus_space_tag_t sc_cbustag; 167 int sc_clockfreq; /* clock frequency (in Hz) */ 168 struct upa_regs *sc_reg; 169 int sc_nreg; 170 int sc_nrange; 171 struct sbus_rd *sc_rd; 172 int sc_burst; /* burst transfer sizes supp. */ 173 174 struct resource *sc_sysio_res; 175 int sc_ign; /* IGN for this sysio */ 176 struct iommu_state sc_is; /* IOMMU state (iommuvar.h) */ 177 178 struct resource *sc_ot_ires; 179 void *sc_ot_ihand; 180 struct resource *sc_pf_ires; 181 void *sc_pf_ihand; 182 }; 183 184 struct sbus_clr { 185 struct sbus_softc *scl_sc; 186 bus_addr_t scl_clr; /* clear register */ 187 driver_intr_t *scl_handler; /* handler to call */ 188 void *scl_arg; /* argument for the handler */ 189 void *scl_cookie; /* parent bus int. cookie */ 190 }; 191 192 #define SYSIO_READ8(sc, off) \ 193 bus_space_read_8((sc)->sc_bustag, (sc)->sc_bushandle, (off)) 194 #define SYSIO_WRITE8(sc, off, v) \ 195 bus_space_write_8((sc)->sc_bustag, (sc)->sc_bushandle, (off), (v)) 196 197 static device_probe_t sbus_probe; 198 static device_attach_t sbus_attach; 199 static bus_print_child_t sbus_print_child; 200 static bus_probe_nomatch_t sbus_probe_nomatch; 201 static bus_read_ivar_t sbus_read_ivar; 202 static bus_get_resource_list_t sbus_get_resource_list; 203 static bus_setup_intr_t sbus_setup_intr; 204 static bus_teardown_intr_t sbus_teardown_intr; 205 static bus_alloc_resource_t sbus_alloc_resource; 206 static bus_release_resource_t sbus_release_resource; 207 static bus_activate_resource_t sbus_activate_resource; 208 static bus_deactivate_resource_t sbus_deactivate_resource; 209 static ofw_bus_get_compat_t sbus_get_compat; 210 static ofw_bus_get_model_t sbus_get_model; 211 static ofw_bus_get_name_t sbus_get_name; 212 static ofw_bus_get_node_t sbus_get_node; 213 static ofw_bus_get_type_t sbus_get_type; 214 215 static int sbus_inlist(const char *, const char **); 216 static struct sbus_devinfo * sbus_setup_dinfo(struct sbus_softc *sc, 217 phandle_t node, char *name); 218 static void sbus_destroy_dinfo(struct sbus_devinfo *dinfo); 219 static void sbus_intr_stub(void *); 220 static bus_space_tag_t sbus_alloc_bustag(struct sbus_softc *); 221 static void sbus_overtemp(void *); 222 static void sbus_pwrfail(void *); 223 224 static device_method_t sbus_methods[] = { 225 /* Device interface */ 226 DEVMETHOD(device_probe, sbus_probe), 227 DEVMETHOD(device_attach, sbus_attach), 228 DEVMETHOD(device_shutdown, bus_generic_shutdown), 229 DEVMETHOD(device_suspend, bus_generic_suspend), 230 DEVMETHOD(device_resume, bus_generic_resume), 231 232 /* Bus interface */ 233 DEVMETHOD(bus_print_child, sbus_print_child), 234 DEVMETHOD(bus_probe_nomatch, sbus_probe_nomatch), 235 DEVMETHOD(bus_read_ivar, sbus_read_ivar), 236 DEVMETHOD(bus_setup_intr, sbus_setup_intr), 237 DEVMETHOD(bus_teardown_intr, sbus_teardown_intr), 238 DEVMETHOD(bus_alloc_resource, sbus_alloc_resource), 239 DEVMETHOD(bus_activate_resource, sbus_activate_resource), 240 DEVMETHOD(bus_deactivate_resource, sbus_deactivate_resource), 241 DEVMETHOD(bus_release_resource, sbus_release_resource), 242 DEVMETHOD(bus_get_resource_list, sbus_get_resource_list), 243 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 244 245 /* ofw_bus interface */ 246 DEVMETHOD(ofw_bus_get_compat, sbus_get_compat), 247 DEVMETHOD(ofw_bus_get_model, sbus_get_model), 248 DEVMETHOD(ofw_bus_get_name, sbus_get_name), 249 DEVMETHOD(ofw_bus_get_node, sbus_get_node), 250 DEVMETHOD(ofw_bus_get_type, sbus_get_type), 251 252 { 0, 0 } 253 }; 254 255 static driver_t sbus_driver = { 256 "sbus", 257 sbus_methods, 258 sizeof(struct sbus_softc), 259 }; 260 261 static devclass_t sbus_devclass; 262 263 DRIVER_MODULE(sbus, nexus, sbus_driver, sbus_devclass, 0, 0); 264 MODULE_VERSION(sbus, 1); 265 266 #define OFW_SBUS_TYPE "sbus" 267 #define OFW_SBUS_NAME "sbus" 268 269 static const char *sbus_order_first[] = { 270 "auxio", 271 "dma", 272 NULL 273 }; 274 275 static int 276 sbus_inlist(const char *name, const char **list) 277 { 278 int i; 279 280 if (name == NULL) 281 return (0); 282 for (i = 0; list[i] != NULL; i++) { 283 if (strcmp(name, list[i]) == 0) 284 return (1); 285 } 286 return (0); 287 } 288 289 static int 290 sbus_probe(device_t dev) 291 { 292 char *t; 293 294 t = nexus_get_device_type(dev); 295 if (((t == NULL || strcmp(t, OFW_SBUS_TYPE) != 0)) && 296 strcmp(nexus_get_name(dev), OFW_SBUS_NAME) != 0) 297 return (ENXIO); 298 device_set_desc(dev, "U2S UPA-SBus bridge"); 299 return (0); 300 } 301 302 static int 303 sbus_attach(device_t dev) 304 { 305 struct sbus_softc *sc; 306 struct sbus_devinfo *sdi; 307 struct sbus_ranges *range; 308 struct resource *res; 309 device_t cdev; 310 bus_addr_t phys; 311 bus_size_t size; 312 char *cname; 313 phandle_t child, node; 314 u_int64_t mr; 315 int i, intr, clock, rid, vec; 316 317 sc = device_get_softc(dev); 318 node = nexus_get_node(dev); 319 320 if ((sc->sc_nreg = OF_getprop_alloc(node, "reg", sizeof(*sc->sc_reg), 321 (void **)&sc->sc_reg)) == -1) { 322 panic("%s: error getting reg property", __func__); 323 } 324 if (sc->sc_nreg < 1) 325 panic("%s: bogus properties", __func__); 326 phys = UPA_REG_PHYS(&sc->sc_reg[0]); 327 size = UPA_REG_SIZE(&sc->sc_reg[0]); 328 rid = 0; 329 sc->sc_sysio_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys, 330 phys + size - 1, size, RF_ACTIVE); 331 if (sc->sc_sysio_res == NULL || 332 rman_get_start(sc->sc_sysio_res) != phys) 333 panic("%s: cannot allocate device memory", __func__); 334 sc->sc_bustag = rman_get_bustag(sc->sc_sysio_res); 335 sc->sc_bushandle = rman_get_bushandle(sc->sc_sysio_res); 336 337 if (OF_getprop(node, "interrupts", &intr, sizeof(intr)) == -1) 338 panic("%s: cannot get IGN", __func__); 339 sc->sc_ign = (intr & INTMAP_IGN_MASK) >> INTMAP_IGN_SHIFT; 340 sc->sc_cbustag = sbus_alloc_bustag(sc); 341 342 /* 343 * Record clock frequency for synchronous SCSI. 344 * IS THIS THE CORRECT DEFAULT?? 345 */ 346 if (OF_getprop(node, "clock-frequency", &clock, sizeof(clock)) == -1) 347 clock = 25000000; 348 sc->sc_clockfreq = clock; 349 clock /= 1000; 350 device_printf(dev, "clock %d.%03d MHz\n", clock / 1000, clock % 1000); 351 352 /* 353 * Collect address translations from the OBP. 354 */ 355 if ((sc->sc_nrange = OF_getprop_alloc(node, "ranges", 356 sizeof(*range), (void **)&range)) == -1) { 357 panic("%s: error getting ranges property", __func__); 358 } 359 sc->sc_rd = (struct sbus_rd *)malloc(sizeof(*sc->sc_rd) * sc->sc_nrange, 360 M_DEVBUF, M_NOWAIT); 361 if (sc->sc_rd == NULL) 362 panic("%s: cannot allocate rmans", __func__); 363 /* 364 * Preallocate all space that the SBus bridge decodes, so that nothing 365 * else gets in the way; set up rmans etc. 366 */ 367 for (i = 0; i < sc->sc_nrange; i++) { 368 phys = range[i].poffset | ((bus_addr_t)range[i].pspace << 32); 369 size = range[i].size; 370 sc->sc_rd[i].rd_slot = range[i].cspace; 371 sc->sc_rd[i].rd_coffset = range[i].coffset; 372 sc->sc_rd[i].rd_cend = sc->sc_rd[i].rd_coffset + size; 373 rid = 0; 374 if ((res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, phys, 375 phys + size - 1, size, RF_ACTIVE)) == NULL) 376 panic("%s: cannot allocate decoded range", __func__); 377 sc->sc_rd[i].rd_bushandle = rman_get_bushandle(res); 378 sc->sc_rd[i].rd_rman.rm_type = RMAN_ARRAY; 379 sc->sc_rd[i].rd_rman.rm_descr = "SBus Device Memory"; 380 if (rman_init(&sc->sc_rd[i].rd_rman) != 0 || 381 rman_manage_region(&sc->sc_rd[i].rd_rman, 0, size) != 0) 382 panic("%s: failed to set up memory rman", __func__); 383 sc->sc_rd[i].rd_poffset = phys; 384 sc->sc_rd[i].rd_pend = phys + size; 385 sc->sc_rd[i].rd_res = res; 386 } 387 free(range, M_OFWPROP); 388 389 /* 390 * Get the SBus burst transfer size if burst transfers are supported. 391 * XXX: is the default correct? 392 */ 393 if (OF_getprop(node, "burst-sizes", &sc->sc_burst, 394 sizeof(sc->sc_burst)) == -1 || sc->sc_burst == 0) 395 sc->sc_burst = SBUS_BURST_DEF; 396 397 /* initalise the IOMMU */ 398 399 /* punch in our copies */ 400 sc->sc_is.is_bustag = sc->sc_bustag; 401 sc->sc_is.is_bushandle = sc->sc_bushandle; 402 sc->sc_is.is_iommu = SBR_IOMMU; 403 sc->sc_is.is_dtag = SBR_IOMMU_TLB_TAG_DIAG; 404 sc->sc_is.is_ddram = SBR_IOMMU_TLB_DATA_DIAG; 405 sc->sc_is.is_dqueue = SBR_IOMMU_QUEUE_DIAG; 406 sc->sc_is.is_dva = SBR_IOMMU_SVADIAG; 407 sc->sc_is.is_dtcmp = 0; 408 sc->sc_is.is_sb[0] = SBR_STRBUF; 409 sc->sc_is.is_sb[1] = 0; 410 411 /* 412 * Note: the SBus IOMMU ignores the high bits of an address, so a NULL 413 * DMA pointer will be translated by the first page of the IOTSB. 414 * To detect bugs we'll allocate and ignore the first entry. 415 */ 416 iommu_init(device_get_nameunit(dev), &sc->sc_is, 3, -1, 1); 417 418 /* Create the DMA tag. */ 419 sc->sc_dmatag = nexus_get_dmatag(dev); 420 if (bus_dma_tag_create(sc->sc_dmatag, 8, 1, 0, 0x3ffffffff, NULL, NULL, 421 0x3ffffffff, 0xff, 0xffffffff, 0, NULL, NULL, &sc->sc_cdmatag) != 0) 422 panic("%s: bus_dma_tag_create failed", __func__); 423 /* Customize the tag. */ 424 sc->sc_cdmatag->dt_cookie = &sc->sc_is; 425 sc->sc_cdmatag->dt_mt = &iommu_dma_methods; 426 /* XXX: register as root dma tag (kludge). */ 427 sparc64_root_dma_tag = sc->sc_cdmatag; 428 429 /* Enable the over-temperature and power-fail interrupts. */ 430 rid = 0; 431 mr = SYSIO_READ8(sc, SBR_THERM_INT_MAP); 432 vec = INTVEC(mr); 433 sc->sc_ot_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec, 434 vec, 1, RF_ACTIVE); 435 if (sc->sc_ot_ires == NULL || 436 bus_setup_intr(dev, sc->sc_ot_ires, INTR_TYPE_MISC | INTR_FAST, 437 sbus_overtemp, sc, &sc->sc_ot_ihand) != 0) 438 panic("%s: failed to set up temperature interrupt", __func__); 439 SYSIO_WRITE8(sc, SBR_THERM_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid))); 440 rid = 0; 441 mr = SYSIO_READ8(sc, SBR_POWER_INT_MAP); 442 vec = INTVEC(mr); 443 sc->sc_pf_ires = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, vec, 444 vec, 1, RF_ACTIVE); 445 if (sc->sc_pf_ires == NULL || 446 bus_setup_intr(dev, sc->sc_pf_ires, INTR_TYPE_MISC | INTR_FAST, 447 sbus_pwrfail, sc, &sc->sc_pf_ihand) != 0) 448 panic("%s: failed to set up power fail interrupt", __func__); 449 SYSIO_WRITE8(sc, SBR_POWER_INT_MAP, INTMAP_ENABLE(mr, PCPU_GET(mid))); 450 451 /* Initialize the counter-timer. */ 452 sparc64_counter_init(device_get_nameunit(dev), sc->sc_bustag, 453 sc->sc_bushandle, SBR_TC0); 454 455 /* 456 * Loop through ROM children, fixing any relative addresses 457 * and then configuring each device. 458 */ 459 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 460 if ((OF_getprop_alloc(child, "name", 1, (void **)&cname)) == -1) 461 continue; 462 463 if ((sdi = sbus_setup_dinfo(sc, child, cname)) == NULL) { 464 device_printf(dev, "<%s>: incomplete\n", cname); 465 free(cname, M_OFWPROP); 466 continue; 467 } 468 /* 469 * For devices where there are variants that are actually 470 * split into two SBus devices (as opposed to the first 471 * half of the device being a SBus device and the second 472 * half hanging off of the first one) like 'auxio' and 473 * 'SUNW,fdtwo' or 'dma' and 'esp' probe the SBus device 474 * which is a prerequisite to the driver attaching to the 475 * second one with a lower order. Saves us from dealing 476 * with different probe orders in the respective device 477 * drivers which generally is more hackish. 478 */ 479 cdev = device_add_child_ordered(dev, (OF_child(child) == 0 && 480 sbus_inlist(cname, sbus_order_first)) ? SBUS_ORDER_FIRST : 481 SBUS_ORDER_NORMAL, NULL, -1); 482 if (cdev == NULL) 483 panic("%s: device_add_child_ordered failed", __func__); 484 device_set_ivars(cdev, sdi); 485 } 486 return (bus_generic_attach(dev)); 487 } 488 489 static struct sbus_devinfo * 490 sbus_setup_dinfo(struct sbus_softc *sc, phandle_t node, char *name) 491 { 492 struct sbus_devinfo *sdi; 493 struct sbus_regs *reg; 494 u_int32_t base, iv, *intr; 495 int i, nreg, nintr, slot, rslot; 496 497 sdi = malloc(sizeof(*sdi), M_DEVBUF, M_ZERO | M_WAITOK); 498 if (sdi == NULL) 499 return (NULL); 500 resource_list_init(&sdi->sdi_rl); 501 sdi->sdi_name = name; 502 sdi->sdi_node = node; 503 OF_getprop_alloc(node, "compatible", 1, (void **)&sdi->sdi_compat); 504 OF_getprop_alloc(node, "device_type", 1, (void **)&sdi->sdi_type); 505 OF_getprop_alloc(node, "model", 1, (void **)&sdi->sdi_model); 506 slot = -1; 507 nreg = OF_getprop_alloc(node, "reg", sizeof(*reg), (void **)®); 508 if (nreg == -1) { 509 if (sdi->sdi_type == NULL || 510 strcmp(sdi->sdi_type, "hierarchical") != 0) { 511 sbus_destroy_dinfo(sdi); 512 return (NULL); 513 } 514 } else { 515 for (i = 0; i < nreg; i++) { 516 base = reg[i].sbr_offset; 517 if (SBUS_ABS(base)) { 518 rslot = SBUS_ABS_TO_SLOT(base); 519 base = SBUS_ABS_TO_OFFSET(base); 520 } else 521 rslot = reg[i].sbr_slot; 522 if (slot != -1 && slot != rslot) 523 panic("%s: multiple slots", __func__); 524 slot = rslot; 525 526 resource_list_add(&sdi->sdi_rl, SYS_RES_MEMORY, i, 527 base, base + reg[i].sbr_size, reg[i].sbr_size); 528 } 529 free(reg, M_OFWPROP); 530 } 531 sdi->sdi_slot = slot; 532 533 /* 534 * The `interrupts' property contains the SBus interrupt level. 535 */ 536 nintr = OF_getprop_alloc(node, "interrupts", sizeof(*intr), 537 (void **)&intr); 538 if (nintr != -1) { 539 for (i = 0; i < nintr; i++) { 540 iv = intr[i]; 541 /* 542 * SBus card devices need the slot number encoded into 543 * the vector as this is generally not done. 544 */ 545 if ((iv & INTMAP_OBIO_MASK) == 0) 546 iv |= slot << 3; 547 /* Set the ign as appropriate. */ 548 iv |= sc->sc_ign << INTMAP_IGN_SHIFT; 549 resource_list_add(&sdi->sdi_rl, SYS_RES_IRQ, i, 550 iv, iv, 1); 551 } 552 free(intr, M_OFWPROP); 553 } 554 if (OF_getprop(node, "burst-sizes", &sdi->sdi_burstsz, 555 sizeof(sdi->sdi_burstsz)) == -1) 556 sdi->sdi_burstsz = sc->sc_burst; 557 else 558 sdi->sdi_burstsz &= sc->sc_burst; 559 if (OF_getprop(node, "clock-frequency", &sdi->sdi_clockfreq, 560 sizeof(sdi->sdi_clockfreq)) == -1) 561 sdi->sdi_clockfreq = sc->sc_clockfreq; 562 563 return (sdi); 564 } 565 566 /* Free everything except sdi_name, which is handled separately. */ 567 static void 568 sbus_destroy_dinfo(struct sbus_devinfo *dinfo) 569 { 570 571 resource_list_free(&dinfo->sdi_rl); 572 if (dinfo->sdi_compat != NULL) 573 free(dinfo->sdi_compat, M_OFWPROP); 574 if (dinfo->sdi_model != NULL) 575 free(dinfo->sdi_model, M_OFWPROP); 576 if (dinfo->sdi_type != NULL) 577 free(dinfo->sdi_type, M_OFWPROP); 578 free(dinfo, M_DEVBUF); 579 } 580 581 static int 582 sbus_print_child(device_t dev, device_t child) 583 { 584 struct sbus_devinfo *dinfo; 585 struct resource_list *rl; 586 int rv; 587 588 dinfo = device_get_ivars(child); 589 rl = &dinfo->sdi_rl; 590 rv = bus_print_child_header(dev, child); 591 rv += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 592 rv += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 593 rv += bus_print_child_footer(dev, child); 594 return (rv); 595 } 596 597 static void 598 sbus_probe_nomatch(device_t dev, device_t child) 599 { 600 struct sbus_devinfo *dinfo; 601 struct resource_list *rl; 602 603 dinfo = device_get_ivars(child); 604 rl = &dinfo->sdi_rl; 605 device_printf(dev, "<%s>", dinfo->sdi_name); 606 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx"); 607 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld"); 608 printf(" type %s (no driver attached)\n", 609 dinfo->sdi_type != NULL ? dinfo->sdi_type : "unknown"); 610 } 611 612 static int 613 sbus_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 614 { 615 struct sbus_softc *sc; 616 struct sbus_devinfo *dinfo; 617 618 sc = device_get_softc(dev); 619 if ((dinfo = device_get_ivars(child)) == NULL) 620 return (ENOENT); 621 switch (which) { 622 case SBUS_IVAR_BURSTSZ: 623 *result = dinfo->sdi_burstsz; 624 break; 625 case SBUS_IVAR_CLOCKFREQ: 626 *result = dinfo->sdi_clockfreq; 627 break; 628 case SBUS_IVAR_IGN: 629 *result = sc->sc_ign; 630 break; 631 case SBUS_IVAR_SLOT: 632 *result = dinfo->sdi_slot; 633 break; 634 default: 635 return (ENOENT); 636 } 637 return (0); 638 } 639 640 static struct resource_list * 641 sbus_get_resource_list(device_t dev, device_t child) 642 { 643 struct sbus_devinfo *sdi; 644 645 sdi = device_get_ivars(child); 646 return (&sdi->sdi_rl); 647 } 648 649 /* Write to the correct clr register, and call the actual handler. */ 650 static void 651 sbus_intr_stub(void *arg) 652 { 653 struct sbus_clr *scl; 654 655 scl = (struct sbus_clr *)arg; 656 scl->scl_handler(scl->scl_arg); 657 SYSIO_WRITE8(scl->scl_sc, scl->scl_clr, 0); 658 } 659 660 static int 661 sbus_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, 662 driver_intr_t *intr, void *arg, void **cookiep) 663 { 664 struct sbus_softc *sc; 665 struct sbus_clr *scl; 666 bus_addr_t intrmapptr, intrclrptr, intrptr; 667 u_int64_t intrmap; 668 u_int32_t inr, slot; 669 int error, i; 670 long vec; 671 672 sc = device_get_softc(dev); 673 scl = (struct sbus_clr *)malloc(sizeof(*scl), M_DEVBUF, M_NOWAIT); 674 if (scl == NULL) 675 return (ENOMEM); 676 intrptr = intrmapptr = intrclrptr = 0; 677 intrmap = 0; 678 vec = rman_get_start(ires); 679 inr = INTVEC(vec); 680 if ((inr & INTMAP_OBIO_MASK) == 0) { 681 /* 682 * We're in an SBus slot, register the map and clear 683 * intr registers. 684 */ 685 slot = INTSLOT(vec); 686 intrmapptr = SBR_SLOT0_INT_MAP + slot * 8; 687 intrclrptr = SBR_SLOT0_INT_CLR + 688 (slot * 8 * 8) + (INTPRI(vec) * 8); 689 /* Enable the interrupt, insert IGN. */ 690 intrmap = inr | (sc->sc_ign << INTMAP_IGN_SHIFT); 691 } else { 692 intrptr = SBR_SCSI_INT_MAP; 693 /* Insert IGN */ 694 inr |= sc->sc_ign << INTMAP_IGN_SHIFT; 695 for (i = 0; intrptr <= SBR_RESERVED_INT_MAP && 696 INTVEC(intrmap = SYSIO_READ8(sc, intrptr)) != inr; 697 intrptr += 8, i++) 698 ; 699 if (INTVEC(intrmap) == inr) { 700 /* Register the map and clear intr registers */ 701 intrmapptr = intrptr; 702 intrclrptr = SBR_SCSI_INT_CLR + i * 8; 703 /* Enable the interrupt */ 704 } else 705 panic("%s: IRQ not found!", __func__); 706 } 707 708 scl->scl_sc = sc; 709 scl->scl_arg = arg; 710 scl->scl_handler = intr; 711 scl->scl_clr = intrclrptr; 712 /* Disable the interrupt while we fiddle with it */ 713 SYSIO_WRITE8(sc, intrmapptr, intrmap & ~INTMAP_V); 714 error = BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 715 sbus_intr_stub, scl, cookiep); 716 if (error != 0) { 717 free(scl, M_DEVBUF); 718 return (error); 719 } 720 scl->scl_cookie = *cookiep; 721 *cookiep = scl; 722 723 /* 724 * Clear the interrupt, it might have been triggered before it was 725 * set up. 726 */ 727 SYSIO_WRITE8(sc, intrclrptr, 0); 728 /* 729 * Enable the interrupt and program the target module now we have the 730 * handler installed. 731 */ 732 SYSIO_WRITE8(sc, intrmapptr, INTMAP_ENABLE(intrmap, PCPU_GET(mid))); 733 return (error); 734 } 735 736 static int 737 sbus_teardown_intr(device_t dev, device_t child, 738 struct resource *vec, void *cookie) 739 { 740 struct sbus_clr *scl; 741 int error; 742 743 scl = (struct sbus_clr *)cookie; 744 error = BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, 745 scl->scl_cookie); 746 /* 747 * Don't disable the interrupt for now, so that stray interrupts get 748 * detected... 749 */ 750 if (error != 0) 751 free(scl, M_DEVBUF); 752 return (error); 753 } 754 755 static struct resource * 756 sbus_alloc_resource(device_t bus, device_t child, int type, int *rid, 757 u_long start, u_long end, u_long count, u_int flags) 758 { 759 struct sbus_softc *sc; 760 struct rman *rm; 761 struct resource *rv; 762 struct resource_list *rl; 763 struct resource_list_entry *rle; 764 device_t schild; 765 bus_space_handle_t bh; 766 bus_addr_t toffs; 767 bus_size_t tend; 768 int i, slot; 769 int isdefault, needactivate, passthrough; 770 771 isdefault = (start == 0UL && end == ~0UL); 772 needactivate = flags & RF_ACTIVE; 773 passthrough = (device_get_parent(child) != bus); 774 rle = NULL; 775 sc = device_get_softc(bus); 776 rl = BUS_GET_RESOURCE_LIST(bus, child); 777 switch (type) { 778 case SYS_RES_IRQ: 779 return (resource_list_alloc(rl, bus, child, type, rid, start, 780 end, count, flags)); 781 case SYS_RES_MEMORY: 782 if (!passthrough) { 783 rle = resource_list_find(rl, type, *rid); 784 if (rle == NULL) 785 return (NULL); 786 if (rle->res != NULL) 787 panic("%s: resource entry is busy", __func__); 788 if (isdefault) { 789 start = rle->start; 790 count = ulmax(count, rle->count); 791 end = ulmax(rle->end, start + count - 1); 792 } 793 } 794 rm = NULL; 795 bh = toffs = tend = 0; 796 schild = child; 797 while (device_get_parent(schild) != bus) 798 schild = device_get_parent(schild); 799 slot = sbus_get_slot(schild); 800 for (i = 0; i < sc->sc_nrange; i++) { 801 if (sc->sc_rd[i].rd_slot != slot || 802 start < sc->sc_rd[i].rd_coffset || 803 start > sc->sc_rd[i].rd_cend) 804 continue; 805 /* Disallow cross-range allocations. */ 806 if (end > sc->sc_rd[i].rd_cend) 807 return (NULL); 808 /* We've found the connection to the parent bus */ 809 toffs = start - sc->sc_rd[i].rd_coffset; 810 tend = end - sc->sc_rd[i].rd_coffset; 811 rm = &sc->sc_rd[i].rd_rman; 812 bh = sc->sc_rd[i].rd_bushandle; 813 break; 814 } 815 if (rm == NULL) 816 return (NULL); 817 flags &= ~RF_ACTIVE; 818 rv = rman_reserve_resource(rm, toffs, tend, count, flags, 819 child); 820 if (rv == NULL) 821 return (NULL); 822 rman_set_rid(rv, *rid); 823 rman_set_bustag(rv, sc->sc_cbustag); 824 rman_set_bushandle(rv, bh + rman_get_start(rv)); 825 if (needactivate) { 826 if (bus_activate_resource(child, type, *rid, rv)) { 827 rman_release_resource(rv); 828 return (NULL); 829 } 830 } 831 if (!passthrough) 832 rle->res = rv; 833 return (rv); 834 default: 835 return (NULL); 836 } 837 } 838 839 static int 840 sbus_activate_resource(device_t bus, device_t child, int type, int rid, 841 struct resource *r) 842 { 843 void *p; 844 int error; 845 846 if (type == SYS_RES_IRQ) { 847 return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), 848 child, type, rid, r)); 849 } 850 if (type == SYS_RES_MEMORY) { 851 /* 852 * Need to memory-map the device space, as some drivers depend 853 * on the virtual address being set and useable. 854 */ 855 error = sparc64_bus_mem_map(rman_get_bustag(r), 856 rman_get_bushandle(r), rman_get_size(r), 0, 0, &p); 857 if (error != 0) 858 return (error); 859 rman_set_virtual(r, p); 860 } 861 return (rman_activate_resource(r)); 862 } 863 864 static int 865 sbus_deactivate_resource(device_t bus, device_t child, int type, int rid, 866 struct resource *r) 867 { 868 869 if (type == SYS_RES_IRQ) { 870 return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), 871 child, type, rid, r)); 872 } 873 if (type == SYS_RES_MEMORY) { 874 sparc64_bus_mem_unmap(rman_get_virtual(r), rman_get_size(r)); 875 rman_set_virtual(r, NULL); 876 } 877 return (rman_deactivate_resource(r)); 878 } 879 880 static int 881 sbus_release_resource(device_t bus, device_t child, int type, int rid, 882 struct resource *r) 883 { 884 struct resource_list *rl; 885 struct resource_list_entry *rle; 886 int error, passthrough; 887 888 passthrough = (device_get_parent(child) != bus); 889 rl = BUS_GET_RESOURCE_LIST(bus, child); 890 if (type == SYS_RES_IRQ) 891 return (resource_list_release(rl, bus, child, type, rid, r)); 892 if ((rman_get_flags(r) & RF_ACTIVE) != 0) { 893 error = bus_deactivate_resource(child, type, rid, r); 894 if (error != 0) 895 return (error); 896 } 897 error = rman_release_resource(r); 898 if (error != 0 || passthrough) 899 return (error); 900 rle = resource_list_find(rl, type, rid); 901 if (rle == NULL) 902 panic("%s: cannot find resource", __func__); 903 if (rle->res == NULL) 904 panic("%s: resource entry is not busy", __func__); 905 rle->res = NULL; 906 return (0); 907 } 908 909 /* 910 * Handle an overtemp situation. 911 * 912 * SPARCs have temperature sensors which generate interrupts 913 * if the machine's temperature exceeds a certain threshold. 914 * This handles the interrupt and powers off the machine. 915 * The same needs to be done to PCI controller drivers. 916 */ 917 static void 918 sbus_overtemp(void *arg) 919 { 920 921 printf("DANGER: OVER TEMPERATURE detected\nShutting down NOW.\n"); 922 shutdown_nice(RB_POWEROFF); 923 } 924 925 /* Try to shut down in time in case of power failure. */ 926 static void 927 sbus_pwrfail(void *arg) 928 { 929 930 printf("Power failure detected\nShutting down NOW.\n"); 931 shutdown_nice(0); 932 } 933 934 static bus_space_tag_t 935 sbus_alloc_bustag(struct sbus_softc *sc) 936 { 937 bus_space_tag_t sbt; 938 939 sbt = (bus_space_tag_t)malloc(sizeof(struct bus_space_tag), M_DEVBUF, 940 M_NOWAIT | M_ZERO); 941 if (sbt == NULL) 942 panic("%s: out of memory", __func__); 943 944 sbt->bst_cookie = sc; 945 sbt->bst_parent = sc->sc_bustag; 946 sbt->bst_type = SBUS_BUS_SPACE; 947 return (sbt); 948 } 949 950 static const char * 951 sbus_get_compat(device_t bus, device_t dev) 952 { 953 struct sbus_devinfo *dinfo; 954 955 dinfo = device_get_ivars(dev); 956 return (dinfo->sdi_compat); 957 } 958 959 static const char * 960 sbus_get_model(device_t bus, device_t dev) 961 { 962 struct sbus_devinfo *dinfo; 963 964 dinfo = device_get_ivars(dev); 965 return (dinfo->sdi_model); 966 } 967 968 static const char * 969 sbus_get_name(device_t bus, device_t dev) 970 { 971 struct sbus_devinfo *dinfo; 972 973 dinfo = device_get_ivars(dev); 974 return (dinfo->sdi_name); 975 } 976 977 static phandle_t 978 sbus_get_node(device_t bus, device_t dev) 979 { 980 struct sbus_devinfo *dinfo; 981 982 dinfo = device_get_ivars(dev); 983 return (dinfo->sdi_node); 984 } 985 986 static const char * 987 sbus_get_type(device_t bus, device_t dev) 988 { 989 struct sbus_devinfo *dinfo; 990 991 dinfo = device_get_ivars(dev); 992 return (dinfo->sdi_type); 993 }
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