The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/sparc64/sbus/sbusreg.h

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    1 /*
    2  * Copyright (c) 1996-1999 Eduardo Horvath
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  *
   10  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
   11  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   12  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   13  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
   14  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   15  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   16  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   17  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   18  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   19  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   20  * SUCH DAMAGE.
   21  *
   22  *      from: NetBSD: sbusreg.h,v 1.7 1999/06/07 05:28:03 eeh Exp
   23  *
   24  * $FreeBSD: releng/5.2/sys/sparc64/sbus/sbusreg.h 90618 2002-02-13 16:11:36Z tmm $
   25  */
   26 
   27 #ifndef _SPARC64_SBUS_SBUSREG_H_
   28 #define _SPARC64_SBUS_SBUSREG_H_
   29 
   30 /*
   31  * Sbus device addresses are obtained from the FORTH PROMs.  They come
   32  * in `absolute' and `relative' address flavors, so we have to handle both.
   33  * Relative addresses do *not* include the slot number.
   34  */
   35 #define SBUS_BASE               0xf8000000
   36 #define SBUS_ADDR(slot, off)    (SBUS_BASE + ((slot) << 25) + (off))
   37 #define SBUS_ABS(a)             ((unsigned)(a) >= SBUS_BASE)
   38 #define SBUS_ABS_TO_SLOT(a)     (((a) - SBUS_BASE) >> 25)
   39 #define SBUS_ABS_TO_OFFSET(a)   (((a) - SBUS_BASE) & 0x1ffffff)
   40 
   41 /*
   42  * Sun4u S-bus definitions.  Here's where we deal w/the machine
   43  * dependencies of sysio.
   44  *
   45  * SYSIO implements or is the interface to several things:
   46  *
   47  * o The SBUS interface itself
   48  * o The IOMMU
   49  * o The DVMA units
   50  * o The interrupt controller
   51  * o The counter/timers
   52  *
   53  * Since it has registers to control lots of different things
   54  * as well as several on-board SBUS devices and external SBUS
   55  * slots scattered throughout its address space, it's a pain.
   56  *
   57  * One good point, however, is that all registers are 64-bit.
   58  */
   59 #define SBR_UPA_PORTID          0x0000  /* UPA port ID register */
   60 #define SBR_UPA_CONFIG          0x0008  /* UPA config register */
   61 #define SBR_CS                  0x0010  /* SYSIO control/status register */
   62 #define SBR_ECCC                0x0020  /* ECC control register */
   63 #define SBR_UE_AFS              0x0030  /* Uncorrectable Error AFSR */
   64 #define SBR_UE_AFA              0x0038  /* Uncorrectable Error AFAR */
   65 #define SBR_CE_AFS              0x0040  /* Correctable Error AFSR */
   66 #define SBR_CE_AFA              0x0048  /* Correctable Error AFAR */
   67 #define SBR_PM_CTL              0x0100  /* Performance monitor control reg */
   68 #define SBR_PM_COUNT            0x0108  /* Performance monitor counter reg */
   69 #define SBR_CTL                 0x2000  /* SBUS Control Register */
   70 #define SBR_AFS                 0x2010  /* SBUS AFSR */
   71 #define SBR_AFA                 0x2018  /* SBUS AFAR */
   72 #define SBR_CONFIG0             0x2020  /* SBUS Slot 0 config register */
   73 #define SBR_CONFIG1             0x2028  /* SBUS Slot 1 config register */
   74 #define SBR_CONFIG2             0x2030  /* SBUS Slot 2 config register */
   75 #define SBR_CONFIG3             0x2038  /* SBUS Slot 3 config register */
   76 #define SBR_CONFIG13            0x2040  /* Slot 13 config register <audio> */
   77 #define SBR_CONFIG14            0x2048  /* Slot 14 config register <macio> */
   78 #define SBR_CONFIG15            0x2050  /* Slot 15 config register <slavio> */
   79 #define SBR_IOMMU               0x2400  /* IOMMU register block */
   80 #define SBR_STRBUF              0x2800  /* stream buffer register block */
   81 #define SBR_SLOT0_INT_MAP       0x2c00  /* SBUS slot 0 interrupt map reg */
   82 #define SBR_SLOT1_INT_MAP       0x2c08  /* SBUS slot 1 interrupt map reg */
   83 #define SBR_SLOT2_INT_MAP       0x2c10  /* SBUS slot 2 interrupt map reg */
   84 #define SBR_SLOT3_INT_MAP       0x2c18  /* SBUS slot 3 interrupt map reg */
   85 #define SBR_INTR_RETRY_TIM      0x2c20  /* interrupt retry timer reg */
   86 #define SBR_SCSI_INT_MAP        0x3000  /* SCSI interrupt map reg */
   87 #define SBR_ETHER_INT_MAP       0x3008  /* ethernet interrupt map reg */
   88 #define SBR_BPP_INT_MAP         0x3010  /* parallel interrupt map reg */
   89 #define SBR_AUDIO_INT_MAP       0x3018  /* audio interrupt map reg */
   90 #define SBR_POWER_INT_MAP       0x3020  /* power fail interrupt map reg */
   91 #define SBR_SKBDMS_INT_MAP      0x3028  /* serial/kbd/mouse interrupt map reg */
   92 #define SBR_FD_INT_MAP          0x3030  /* floppy interrupt map reg */
   93 #define SBR_THERM_INT_MAP       0x3038  /* thermal warn interrupt map reg */
   94 #define SBR_KBD_INT_MAP         0x3040  /* kbd [unused] interrupt map reg */
   95 #define SBR_MOUSE_INT_MAP       0x3048  /* mouse [unused] interrupt map reg */
   96 #define SBR_SERIAL_INT_MAP      0x3050  /* second serial interrupt map reg */
   97 #define SBR_TIMER0_INT_MAP      0x3060  /* timer 0 interrupt map reg */
   98 #define SBR_TIMER1_INT_MAP      0x3068  /* timer 1 interrupt map reg */
   99 #define SBR_UE_INT_MAP          0x3070  /* UE interrupt map reg */
  100 #define SBR_CE_INT_MAP          0x3078  /* CE interrupt map reg */
  101 #define SBR_ASYNC_INT_MAP       0x3080  /* SBUS error interrupt map reg */
  102 #define SBR_PWRMGT_INT_MAP      0x3088  /* power mgmt wake interrupt map reg */
  103 #define SBR_UPAGR_INT_MAP       0x3090  /* UPA graphics interrupt map reg */
  104 #define SBR_RESERVED_INT_MAP    0x3098  /* reserved interrupt map reg */
  105 /*
  106  * Note: clear interrupt 0 registers are not really used
  107  */
  108 #define SBR_SLOT0_INT_CLR       0x3400  /* SBUS slot 0 clear int regs 0..7 */
  109 #define SBR_SLOT1_INT_CLR       0x3440  /* SBUS slot 1 clear int regs 0..7 */
  110 #define SBR_SLOT2_INT_CLR       0x3480  /* SBUS slot 2 clear int regs 0..7 */
  111 #define SBR_SLOT3_INT_CLR       0x34c0  /* SBUS slot 3 clear int regs 0..7 */
  112 #define SBR_SCSI_INT_CLR        0x3800  /* SCSI clear int reg */
  113 #define SBR_ETHER_INT_CLR       0x3808  /* ethernet clear int reg */
  114 #define SBR_BPP_INT_CLR         0x3810  /* parallel clear int reg */
  115 #define SBR_AUDIO_INT_CLR       0x3818  /* audio clear int reg */
  116 #define SBR_POWER_INT_CLR       0x3820  /* power fail clear int reg */
  117 #define SBR_SKBDMS_INT_CLR      0x3828  /* serial/kbd/mouse clear int reg */
  118 #define SBR_FD_INT_CLR          0x3830  /* floppy clear int reg */
  119 #define SBR_THERM_INT_CLR       0x3838  /* thermal warn clear int reg */
  120 #define SBR_KBD_INT_CLR         0x3840  /* kbd [unused] clear int reg */
  121 #define SBR_MOUSE_INT_CLR       0x3848  /* mouse [unused] clear int reg */
  122 #define SBR_SERIAL_INT_CLR      0x3850  /* second serial clear int reg */
  123 #define SBR_TIMER0_INT_CLR      0x3860  /* timer 0 clear int reg */
  124 #define SBR_TIMER1_INT_CLR      0x3868  /* timer 1 clear int reg */
  125 #define SBR_UE_INT_CLR          0x3870  /* UE clear int reg */
  126 #define SBR_CE_INT_CLR          0x3878  /* CE clear int reg */
  127 #define SBR_ASYNC_INT_CLR       0x3880  /* SBUS error clr interrupt reg */
  128 #define SBR_PWRMGT_INT_CLR      0x3888  /* power mgmt wake clr interrupt reg */
  129 #define SBR_TC0                 0x3c00  /* timer/counter 0 */
  130 #define SBR_TC1                 0x3c10  /* timer/counter 1 */
  131 #define SBR_IOMMU_SVADIAG       0x4400  /* SBUS virtual addr diag reg */
  132 #define SBR_IOMMU_QUEUE_DIAG    0x4500  /* IOMMU LRU queue diag 0..15 */
  133 #define SBR_IOMMU_TLB_TAG_DIAG  0x4580  /* TLB tag diag 0..15 */
  134 #define SBR_IOMMU_TLB_DATA_DIAG 0x4600  /* TLB data RAM diag 0..31 */
  135 #define SBR_INT_DIAG            0x4800  /* SBUS int state diag reg */
  136 #define SBR_OBIO_DIAG           0x4808  /* OBIO and misc int state diag reg */
  137 #define SBR_STRBUF_DIAG         0x5000  /* Streaming buffer diag regs */
  138 
  139 #endif /* _SPARC64_SBUS_SBUSREG_H_ */
  140 

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