Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/sparc64/sparc64/interrupt.S
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1 /*- 2 * Copyright (c) 2002 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <machine/asm.h> 28 __FBSDID("$FreeBSD: releng/5.2/sys/sparc64/sparc64/interrupt.S 117658 2003-07-16 00:08:43Z jmg $"); 29 30 #include <machine/asi.h> 31 #include <machine/asmacros.h> 32 #include <machine/ktr.h> 33 #include <machine/pstate.h> 34 35 #include "assym.s" 36 37 /* 38 * Handle a vectored interrupt. 39 * 40 * This is either a data bearing mondo vector interrupt, or a cross trap 41 * request from another cpu. In either case the hardware supplies an 42 * interrupt packet, in the form of 3 data words which are read from internal 43 * registers. A data bearing mondo vector packet consists of an interrupt 44 * number in the first data word, and zero in 2nd and 3rd. We use the 45 * interrupt number to find the function, argument and priority from the 46 * intr_vector table, allocate and fill in an intr_request from the per-cpu 47 * free list, link it onto the per-cpu active list and finally post a softint 48 * at the desired priority. Cross trap requests come in 2 forms, direct 49 * and queued. Direct requests are distinguished by the first data word 50 * being zero. The 2nd data word carries a function to call and the 3rd 51 * an argument to pass. The function is jumped to directly. It executes 52 * in nucleus context on interrupt globals and with all interrupts disabled, 53 * therefore it must be fast, and the things that it can do are limited. 54 * Queued cross trap requests are handled much like mondo vectors, except 55 * that the function, argument and priority are contained in the interrupt 56 * packet itself. They are distinguished by the upper 4 bits of the data 57 * word being non-zero, which specifies the priority of the softint to 58 * deliver. 59 * 60 * Register usage: 61 * %g1 - pointer to intr_request 62 * %g2 - pointer to intr_vector, temp once required data is loaded 63 * %g3 - interrupt number for mondo vectors, unused otherwise 64 * %g4 - function, from the interrupt packet for cross traps, or 65 * loaded from the interrupt registers for mondo vecors 66 * %g5 - argument, as above for %g4 67 * %g6 - softint priority 68 */ 69 ENTRY(intr_vector) 70 /* 71 * Load the interrupt packet from the hardware. 72 */ 73 wr %g0, ASI_SDB_INTR_R, %asi 74 ldxa [%g0 + AA_SDB_INTR_D0] %asi, %g3 75 ldxa [%g0 + AA_SDB_INTR_D1] %asi, %g4 76 ldxa [%g0 + AA_SDB_INTR_D2] %asi, %g5 77 stxa %g0, [%g0] ASI_INTR_RECEIVE 78 membar #Sync 79 80 /* 81 * If the first data word is zero this is a direct cross trap request. 82 * The 2nd word points to code to execute and the 3rd is an argument 83 * to pass. Jump to it. 84 */ 85 brnz,a,pt %g3, 1f 86 nop 87 jmpl %g4, %g0 88 nop 89 /* NOTREACHED */ 90 91 /* 92 * If the high 4 bits of the 1st data word are non-zero, this is a 93 * queued cross trap request to be delivered as a softint. The high 94 * 4 bits of the 1st data word specify a priority, and the 2nd and 95 * 3rd a function and argument. 96 */ 97 1: srlx %g3, 60, %g6 98 brnz,a,pn %g6, 2f 99 clr %g3 100 101 /* 102 * Find the function, argument and desired priority from the 103 * intr_vector table. 104 */ 105 SET(intr_vectors, %g4, %g2) 106 sllx %g3, IV_SHIFT, %g4 107 add %g2, %g4, %g2 108 109 ldx [%g2 + IV_FUNC], %g4 110 ldx [%g2 + IV_ARG], %g5 111 lduw [%g2 + IV_PRI], %g6 112 113 /* 114 * Get an intr_request from the free list. There should always be one 115 * unless we are getting an interrupt storm from stray interrupts, in 116 * which case the we will deference a NULL pointer and panic. 117 */ 118 2: ldx [PCPU(IRFREE)], %g1 119 ldx [%g1 + IR_NEXT], %g2 120 stx %g2, [PCPU(IRFREE)] 121 122 /* 123 * Store the vector number, function, argument and priority. 124 */ 125 stw %g3, [%g1 + IR_VEC] 126 stx %g4, [%g1 + IR_FUNC] 127 stx %g5, [%g1 + IR_ARG] 128 stw %g6, [%g1 + IR_PRI] 129 130 /* 131 * Link it onto the end of the active list. 132 */ 133 stx %g0, [%g1 + IR_NEXT] 134 ldx [PCPU(IRTAIL)], %g4 135 stx %g1, [%g4] 136 add %g1, IR_NEXT, %g1 137 stx %g1, [PCPU(IRTAIL)] 138 139 /* 140 * Trigger a softint at the level indicated by the priority. 141 */ 142 mov 1, %g1 143 sllx %g1, %g6, %g1 144 wr %g1, 0, %set_softint 145 146 /* 147 * Done, retry the instruction. 148 */ 149 retry 150 END(intr_vector) 151 152 ENTRY(intr_fast) 153 save %sp, -CCFSZ, %sp 154 155 1: ldx [PCPU(IRHEAD)], %l0 156 brnz,a,pt %l0, 2f 157 nop 158 159 ret 160 restore 161 162 2: wrpr %g0, PSTATE_NORMAL, %pstate 163 164 ldx [%l0 + IR_NEXT], %l1 165 brnz,pt %l1, 3f 166 stx %l1, [PCPU(IRHEAD)] 167 PCPU_ADDR(IRHEAD, %l1) 168 stx %l1, [PCPU(IRTAIL)] 169 170 3: ldx [%l0 + IR_FUNC], %o0 171 ldx [%l0 + IR_ARG], %o1 172 lduw [%l0 + IR_VEC], %o2 173 174 /* load intrcnt[intr_countp[%o2]] into %l4 */ 175 SET(intrcnt, %l7, %l2) /* %l5 = intrcnt */ 176 prefetcha [%l2] ASI_N, 1 177 SET(intr_countp, %l7, %l3) /* %l6 = intr_countp */ 178 sllx %o2, 1, %l4 /* %l4 = vec << 1 */ 179 lduh [%l4 + %l3], %l5 /* %l6 = intr_countp[%o2] */ 180 sllx %l5, 3, %l6 /* %l6 = intr_countp[%o2] << 3 */ 181 add %l6, %l2, %l7 /* %l4 = intrcnt[intr_countp[%o2]] */ 182 183 ATOMIC_INC_ULONG(%l7, %l5, %l2) 184 185 ldx [PCPU(IRFREE)], %l1 186 stx %l1, [%l0 + IR_NEXT] 187 stx %l0, [PCPU(IRFREE)] 188 189 wrpr %g0, PSTATE_KERNEL, %pstate 190 191 call %o0 192 mov %o1, %o0 193 ba,a %xcc, 1b 194 nop 195 END(intr_fast)
Cache object: 5a5b988378a5e4b666928fb3b729cad4
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