Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/sparc64/sparc64/interrupt.S
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1 /*- 2 * Copyright (c) 2002 Jake Burkholder. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <machine/asm.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <machine/asi.h> 31 #include <machine/asmacros.h> 32 #include <machine/intr_machdep.h> 33 #include <machine/ktr.h> 34 #include <machine/pstate.h> 35 36 #include "assym.s" 37 38 /* 39 * Handle a vectored interrupt. 40 * 41 * This is either a data bearing mondo vector interrupt, or a cross trap 42 * request from another cpu. In either case the hardware supplies an 43 * interrupt packet, in the form of 3 data words which are read from internal 44 * registers. A data bearing mondo vector packet consists of an interrupt 45 * number in the first data word, and zero in 2nd and 3rd. We use the 46 * interrupt number to find the function, argument and priority from the 47 * intr_vector table, allocate and fill in an intr_request from the per-cpu 48 * free list, link it onto the per-cpu active list and finally post a softint 49 * at the desired priority. Cross trap requests come in 2 forms, direct 50 * and queued. Direct requests are distinguished by the first data word 51 * being zero. The 2nd data word carries a function to call and the 3rd 52 * an argument to pass. The function is jumped to directly. It executes 53 * in nucleus context on interrupt globals and with all interrupts disabled, 54 * therefore it must be fast, and the things that it can do are limited. 55 * Queued cross trap requests are handled much like mondo vectors, except 56 * that the function, argument and priority are contained in the interrupt 57 * packet itself. They are distinguished by the upper 4 bits of the data 58 * word being non-zero, which specifies the priority of the softint to 59 * deliver. 60 * 61 * Register usage: 62 * %g1 - pointer to intr_request 63 * %g2 - pointer to intr_vector, temp once required data is loaded 64 * %g3 - interrupt number for mondo vectors, unused otherwise 65 * %g4 - function, from the interrupt packet for cross traps, or 66 * loaded from the interrupt registers for mondo vecors 67 * %g5 - argument, as above for %g4 68 * %g6 - softint priority 69 */ 70 ENTRY(intr_vector) 71 /* 72 * Load the interrupt packet from the hardware. 73 */ 74 wr %g0, ASI_SDB_INTR_R, %asi 75 ldxa [%g0 + AA_SDB_INTR_D0] %asi, %g3 76 ldxa [%g0 + AA_SDB_INTR_D1] %asi, %g4 77 ldxa [%g0 + AA_SDB_INTR_D2] %asi, %g5 78 stxa %g0, [%g0] ASI_INTR_RECEIVE 79 membar #Sync 80 81 /* 82 * If the first data word is zero this is a direct cross trap request. 83 * The 2nd word points to code to execute and the 3rd is an argument 84 * to pass. Jump to it. 85 */ 86 brnz,a,pt %g3, 1f 87 nop 88 jmpl %g4, %g0 89 nop 90 /* NOTREACHED */ 91 92 /* 93 * If the high 4 bits of the 1st data word are non-zero, this is a 94 * queued cross trap request to be delivered as a softint. The high 95 * 4 bits of the 1st data word specify a priority, and the 2nd and 96 * 3rd a function and argument. 97 */ 98 1: srlx %g3, 60, %g6 99 brnz,a,pn %g6, 2f 100 clr %g3 101 102 /* 103 * Find the function, argument and desired priority from the 104 * intr_vector table. 105 */ 106 SET(intr_vectors, %g4, %g2) 107 sllx %g3, IV_SHIFT, %g4 108 add %g2, %g4, %g2 109 110 ldx [%g2 + IV_FUNC], %g4 111 ldx [%g2 + IV_ARG], %g5 112 lduw [%g2 + IV_PRI], %g6 113 114 /* 115 * Get an intr_request from the free list. There should always be one 116 * unless we are getting an interrupt storm from stray interrupts, in 117 * which case the we will deference a NULL pointer and panic. 118 */ 119 2: ldx [PCPU(IRFREE)], %g1 120 ldx [%g1 + IR_NEXT], %g2 121 stx %g2, [PCPU(IRFREE)] 122 123 /* 124 * Store the vector number, function, argument and priority. 125 */ 126 stw %g3, [%g1 + IR_VEC] 127 stx %g4, [%g1 + IR_FUNC] 128 stx %g5, [%g1 + IR_ARG] 129 stw %g6, [%g1 + IR_PRI] 130 131 /* 132 * Link it onto the end of the active list. 133 */ 134 stx %g0, [%g1 + IR_NEXT] 135 ldx [PCPU(IRTAIL)], %g4 136 stx %g1, [%g4] 137 add %g1, IR_NEXT, %g1 138 stx %g1, [PCPU(IRTAIL)] 139 140 /* 141 * Trigger a softint at the level indicated by the priority. 142 */ 143 mov 1, %g1 144 sllx %g1, %g6, %g1 145 wr %g1, 0, %set_softint 146 147 /* 148 * Done, retry the instruction. 149 */ 150 retry 151 END(intr_vector) 152 153 ENTRY(intr_fast) 154 save %sp, -CCFSZ, %sp 155 156 /* 157 * Disable interrupts while we fiddle with the interrupt request lists 158 * as interrupts at levels higher than what got us here aren't blocked. 159 */ 160 1: wrpr %g0, PSTATE_NORMAL, %pstate 161 162 ldx [PCPU(IRHEAD)], %l0 163 brnz,a,pt %l0, 2f 164 nop 165 166 wrpr %g0, PSTATE_KERNEL, %pstate 167 168 ret 169 restore 170 171 2: ldx [%l0 + IR_NEXT], %l1 172 brnz,pt %l1, 3f 173 stx %l1, [PCPU(IRHEAD)] 174 PCPU_ADDR(IRHEAD, %l1) 175 stx %l1, [PCPU(IRTAIL)] 176 177 3: ldx [%l0 + IR_FUNC], %o0 178 ldx [%l0 + IR_ARG], %o1 179 lduw [%l0 + IR_VEC], %o2 180 181 ldx [PCPU(IRFREE)], %l1 182 stx %l1, [%l0 + IR_NEXT] 183 stx %l0, [PCPU(IRFREE)] 184 185 wrpr %g0, PSTATE_KERNEL, %pstate 186 187 KASSERT(%o0, "intr_fast: ir_func null") 188 call %o0 189 mov %o1, %o0 190 191 /* intrcnt[intr_countp[%o2]]++ */ 192 SET(intrcnt, %l7, %l2) /* %l2 = intrcnt */ 193 prefetcha [%l2] ASI_N, 1 194 SET(intr_countp, %l7, %l3) /* %l3 = intr_countp */ 195 sllx %o2, 1, %l4 /* %l4 = vec << 1 */ 196 lduh [%l4 + %l3], %l5 /* %l5 = intr_countp[%o2] */ 197 sllx %l5, 3, %l6 /* %l6 = intr_countp[%o2] << 3 */ 198 add %l6, %l2, %l7 /* %l7 = intrcnt[intr_countp[%o2]] */ 199 ldx [%l7], %l2 200 inc %l2 201 stx %l2, [%l7] 202 203 ba,a %xcc, 1b 204 nop 205 END(intr_fast)
Cache object: ebbb964a85c0c4ee1ef0089962c33444
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