The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/sparc64/sparc64/locore.S

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    1 /*-
    2  * Copyright (c) 2001 Jake Burkholder.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <machine/asm.h>
   28 __FBSDID("$FreeBSD: releng/5.2/sys/sparc64/sparc64/locore.S 114188 2003-04-29 00:37:41Z jake $");
   29 
   30 #include <machine/asi.h>
   31 #include <machine/asmacros.h>
   32 #include <machine/pstate.h>
   33 #include <machine/upa.h>
   34 
   35 #include "assym.s"
   36 
   37         .register %g2,#ignore
   38 
   39         .globl  kernbase
   40         .set    kernbase,KERNBASE
   41 
   42 /*
   43  * void _start(caddr_t metadata, u_long o1, u_long o2, u_long o3,
   44  *             u_long ofw_vec)
   45  */
   46 ENTRY(btext)
   47 ENTRY(_start)
   48         /*
   49          * Initialize misc state to known values.  Interrupts disabled, normal
   50          * globals, windows flushed (cr = 0, cs = nwindows - 1), no clean
   51          * windows, pil 0, and floating point disabled.
   52          */
   53         wrpr    %g0, PSTATE_NORMAL, %pstate
   54         flushw
   55         wrpr    %g0, 0, %cleanwin
   56         wrpr    %g0, 0, %pil
   57         wr      %g0, 0, %fprs
   58         wrpr    %g0, 0, %tick
   59 
   60         /*
   61          * Get onto our per-cpu panic stack, which precedes the struct pcpu in
   62          * the per-cpu page.
   63          */
   64         SET(pcpu0 + (PCPU_PAGES * PAGE_SIZE) - PC_SIZEOF, %l1, %l0)
   65         sub     %l0, SPOFF + CCFSZ, %sp
   66 
   67         /*
   68          * Enable interrupts.
   69          */
   70         wrpr    %g0, PSTATE_KERNEL, %pstate
   71 
   72         /*
   73          * Do initial bootstrap to setup pmap and thread0.
   74          */
   75         call    sparc64_init
   76          nop
   77 
   78         /*
   79          * Get onto thread0's kstack.
   80          */
   81         sub     PCB_REG, SPOFF + CCFSZ, %sp
   82 
   83         /*
   84          * And away we go.  This doesn't return.
   85          */
   86         call    mi_startup
   87          nop
   88         sir
   89         ! NOTREACHED
   90 END(_start)
   91 
   92 /*
   93  * void cpu_setregs(struct pcpu *pc)
   94  */
   95 ENTRY(cpu_setregs)
   96         ldx     [%o0 + PC_CURPCB], %o1
   97 
   98         /*
   99          * Disable interrupts, normal globals.
  100          */
  101         wrpr    %g0, PSTATE_NORMAL, %pstate
  102 
  103         /*
  104          * Normal %g6 points to the current thread's pcb, and %g7 points to
  105          * the per-cpu data structure.
  106          */
  107         mov     %o1, PCB_REG
  108         mov     %o0, PCPU_REG
  109 
  110         /*
  111          * Alternate globals.
  112          */
  113         wrpr    %g0, PSTATE_ALT, %pstate
  114 
  115         /*
  116          * Alternate %g5 points to a per-cpu panic stack, %g6 points to the
  117          * current thread's pcb, and %g7 points to the per-cpu data structure.
  118          */
  119         mov     %o0, ASP_REG
  120         mov     %o1, PCB_REG
  121         mov     %o0, PCPU_REG
  122 
  123         /*
  124          * Interrupt globals.
  125          */
  126         wrpr    %g0, PSTATE_INTR, %pstate
  127 
  128         /*
  129          * Interrupt %g7 points to the per-cpu data structure.
  130          */
  131         mov     %o0, PCPU_REG
  132 
  133         /*
  134          * Normal globals again.
  135          */
  136         wrpr    %g0, PSTATE_NORMAL, %pstate
  137 
  138         /*
  139          * Force trap level 1 and take over the trap table.
  140          */
  141         SET(tl0_base, %o2, %o1)
  142         wrpr    %g0, 1, %tl
  143         wrpr    %o1, 0, %tba
  144 
  145         /*
  146          * Re-enable interrupts.
  147          */
  148         wrpr    %g0, PSTATE_KERNEL, %pstate
  149 
  150         retl
  151          nop
  152 END(cpu_setregs)

Cache object: 282900330b0cf934924e821c0487c109


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