locore.S

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    1 /*-
    2  * Copyright (c) 2001 Jake Burkholder.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <machine/asm.h>
   28 __FBSDID("$FreeBSD$");
   29 
   30 #include <machine/asi.h>
   31 #include <machine/asmacros.h>
   32 #include <machine/pstate.h>
   33 
   34 #include "assym.s"
   35 
   36         .register %g2,#ignore
   37 
   38         .globl  kernbase
   39         .set    kernbase,KERNBASE
   40 
   41 /*
   42  * void _start(caddr_t metadata, u_long o1, u_long o2, u_long o3,
   43  *             u_long ofw_vec)
   44  */
   45 ENTRY(btext)
   46 ENTRY(_start)
   47         /*
   48          * Initialize misc state to known values.  Interrupts disabled, normal
   49          * globals, windows flushed (cr = 0, cs = nwindows - 1), no clean
   50          * windows, pil 0, and floating point disabled.
   51          */
   52         wrpr    %g0, PSTATE_NORMAL, %pstate
   53         flushw
   54         wrpr    %g0, 0, %cleanwin
   55         wrpr    %g0, 0, %pil
   56         wr      %g0, 0, %fprs
   57         wrpr    %g0, 0, %tick
   58 
   59         /*
   60          * Get onto our per-cpu panic stack, which precedes the struct pcpu in
   61          * the per-cpu page.
   62          */
   63         SET(pcpu0 + (PCPU_PAGES * PAGE_SIZE) - PC_SIZEOF, %l1, %l0)
   64         sub     %l0, SPOFF + CCFSZ, %sp
   65 
   66         /*
   67          * Enable interrupts.
   68          */
   69         wrpr    %g0, PSTATE_KERNEL, %pstate
   70 
   71         /*
   72          * Do initial bootstrap to setup pmap and thread0.
   73          */
   74         call    sparc64_init
   75          nop
   76 
   77         /*
   78          * Get onto thread0's kstack.
   79          */
   80         sub     PCB_REG, SPOFF + CCFSZ, %sp
   81 
   82         /*
   83          * And away we go.  This doesn't return.
   84          */
   85         call    mi_startup
   86          nop
   87         sir
   88         ! NOTREACHED
   89 END(_start)
   90 
   91 /*
   92  * void cpu_setregs(struct pcpu *pc)
   93  */
   94 ENTRY(cpu_setregs)
   95         ldx     [%o0 + PC_CURPCB], %o1
   96 
   97         /*
   98          * Disable interrupts, normal globals.
   99          */
  100         wrpr    %g0, PSTATE_NORMAL, %pstate
  101 
  102         /*
  103          * Normal %g6 points to the current thread's pcb, and %g7 points to
  104          * the per-cpu data structure.
  105          */
  106         mov     %o1, PCB_REG
  107         mov     %o0, PCPU_REG
  108 
  109         /*
  110          * Alternate globals.
  111          */
  112         wrpr    %g0, PSTATE_ALT, %pstate
  113 
  114         /*
  115          * Alternate %g5 points to a per-cpu panic stack, %g6 points to the
  116          * current thread's pcb, and %g7 points to the per-cpu data structure.
  117          */
  118         mov     %o0, ASP_REG
  119         mov     %o1, PCB_REG
  120         mov     %o0, PCPU_REG
  121 
  122         /*
  123          * Interrupt globals.
  124          */
  125         wrpr    %g0, PSTATE_INTR, %pstate
  126 
  127         /*
  128          * Interrupt %g7 points to the per-cpu data structure.
  129          */
  130         mov     %o0, PCPU_REG
  131 
  132         /*
  133          * Normal globals again.
  134          */
  135         wrpr    %g0, PSTATE_NORMAL, %pstate
  136 
  137         /*
  138          * Force trap level 1 and take over the trap table.
  139          */
  140         SET(tl0_base, %o2, %o1)
  141         wrpr    %g0, 1, %tl
  142         wrpr    %o1, 0, %tba
  143 
  144         /*
  145          * Re-enable interrupts.
  146          */
  147         wrpr    %g0, PSTATE_KERNEL, %pstate
  148 
  149         retl
  150          nop
  151 END(cpu_setregs)

Cache object: d1b3281e96f96d26e967c77a118b5794

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FreeBSD/Linux Kernel Cross Reference sys/sparc64/sparc64/locore.S

FreeBSD/Linux Kernel Cross Reference
sys/sparc64/sparc64/locore.S