spitfire.c

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    1 /*-
    2  * Copyright (c) 2003 Jake Burkholder.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/6.0/sys/sparc64/sparc64/spitfire.c 122464 2003-11-11 06:41:54Z jake $
   27  */
   28 
   29 #include "opt_pmap.h"
   30 
   31 #include <sys/param.h>
   32 #include <sys/linker_set.h>
   33 #include <sys/proc.h>
   34 #include <sys/lock.h>
   35 #include <sys/mutex.h>
   36 #include <sys/smp.h>
   37 #include <sys/sysctl.h>
   38 #include <sys/systm.h>
   39 
   40 #include <vm/vm.h>
   41 #include <vm/pmap.h>
   42 
   43 #include <machine/cache.h>
   44 #include <machine/cpufunc.h>
   45 #include <machine/lsu.h>
   46 #include <machine/smp.h>
   47 #include <machine/tlb.h>
   48 
   49 #define SPITFIRE_TLB_ENTRIES    64
   50 
   51 PMAP_STATS_VAR(spitfire_dcache_npage_inval);
   52 PMAP_STATS_VAR(spitfire_dcache_npage_inval_match);
   53 PMAP_STATS_VAR(spitfire_icache_npage_inval);
   54 PMAP_STATS_VAR(spitfire_icache_npage_inval_match);
   55 
   56 /*
   57  * Enable the level 1 caches.
   58  */
   59 void
   60 spitfire_cache_enable(void)
   61 {
   62         u_long lsu;
   63 
   64         lsu = ldxa(0, ASI_LSU_CTL_REG);
   65         stxa_sync(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC);
   66 }
   67 
   68 /*
   69  * Flush all lines from the level 1 caches.
   70  */
   71 void
   72 spitfire_cache_flush(void)
   73 {
   74         u_long addr;
   75 
   76         for (addr = 0; addr < cache.dc_size; addr += cache.dc_linesize)
   77                 stxa_sync(addr, ASI_DCACHE_TAG, 0);
   78         for (addr = 0; addr < cache.ic_size; addr += cache.ic_linesize)
   79                 stxa_sync(addr, ASI_ICACHE_TAG, 0);
   80 }
   81 
   82 /*
   83  * Flush a physical page from the data cache.
   84  */
   85 void
   86 spitfire_dcache_page_inval(vm_paddr_t pa)
   87 {
   88         u_long target;
   89         void *cookie;
   90         u_long addr;
   91         u_long tag;
   92 
   93         KASSERT((pa & PAGE_MASK) == 0,
   94             ("dcache_page_inval: pa not page aligned"));
   95         PMAP_STATS_INC(spitfire_dcache_npage_inval);
   96         target = pa >> (PAGE_SHIFT - DC_TAG_SHIFT);
   97         cookie = ipi_dcache_page_inval(tl_ipi_spitfire_dcache_page_inval, pa);
   98         for (addr = 0; addr < cache.dc_size; addr += cache.dc_linesize) {
   99                 tag = ldxa(addr, ASI_DCACHE_TAG);
  100                 if (((tag >> DC_VALID_SHIFT) & DC_VALID_MASK) == 0)
  101                         continue;
  102                 tag &= DC_TAG_MASK << DC_TAG_SHIFT;
  103                 if (tag == target) {
  104                         PMAP_STATS_INC(spitfire_dcache_npage_inval_match);
  105                         stxa_sync(addr, ASI_DCACHE_TAG, tag);
  106                 }
  107         }
  108         ipi_wait(cookie);
  109 }
  110 
  111 /*
  112  * Flush a physical page from the instruction cache.
  113  */
  114 void
  115 spitfire_icache_page_inval(vm_paddr_t pa)
  116 {
  117         register u_long tag __asm("%g1");
  118         u_long target;
  119         void *cookie;
  120         u_long addr;
  121 
  122         KASSERT((pa & PAGE_MASK) == 0,
  123             ("icache_page_inval: pa not page aligned"));
  124         PMAP_STATS_INC(spitfire_icache_npage_inval);
  125         target = pa >> (PAGE_SHIFT - IC_TAG_SHIFT);
  126         cookie = ipi_icache_page_inval(tl_ipi_spitfire_icache_page_inval, pa);
  127         for (addr = 0; addr < cache.ic_size; addr += cache.ic_linesize) {
  128                 __asm __volatile("ldda [%1] %2, %%g0" /*, %g1 */
  129                     : "=r" (tag) : "r" (addr), "n" (ASI_ICACHE_TAG));
  130                 if (((tag >> IC_VALID_SHIFT) & IC_VALID_MASK) == 0)
  131                         continue;
  132                 tag &= IC_TAG_MASK << IC_TAG_SHIFT;
  133                 if (tag == target) {
  134                         PMAP_STATS_INC(spitfire_icache_npage_inval_match);
  135                         stxa_sync(addr, ASI_ICACHE_TAG, tag);
  136                 }
  137         }
  138         ipi_wait(cookie);
  139 }
  140 
  141 /*
  142  * Flush all user mappings from the tlb.
  143  */
  144 void
  145 spitfire_tlb_flush_user(void)
  146 {
  147         u_long data;
  148         u_long tag;
  149         int i;
  150 
  151         for (i = 0; i < SPITFIRE_TLB_ENTRIES; i++) {
  152                 data = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG);
  153                 tag = ldxa(TLB_DAR_SLOT(i), ASI_DTLB_TAG_READ_REG);
  154                 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
  155                     TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
  156                         stxa_sync(TLB_DAR_SLOT(i), ASI_DTLB_DATA_ACCESS_REG, 0);
  157                 data = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG);
  158                 tag = ldxa(TLB_DAR_SLOT(i), ASI_ITLB_TAG_READ_REG);
  159                 if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
  160                     TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
  161                         stxa_sync(TLB_DAR_SLOT(i), ASI_ITLB_DATA_ACCESS_REG, 0);
  162         }
  163 }

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FreeBSD/Linux Kernel Cross Reference sys/sparc64/sparc64/spitfire.c

FreeBSD/Linux Kernel Cross Reference
sys/sparc64/sparc64/spitfire.c