Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/sparc64/sparc64/upa.c
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1 /*- 2 * Copyright (c) 2006 Marius Strobl <marius@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/pcpu.h> 36 #include <sys/resource.h> 37 #include <sys/rman.h> 38 39 #include <dev/ofw/ofw_bus.h> 40 #include <dev/ofw/ofw_bus_subr.h> 41 #include <dev/ofw/openfirm.h> 42 43 #include <machine/bus.h> 44 #include <machine/bus_common.h> 45 #include <machine/resource.h> 46 47 #define UPA_NREG 3 48 49 #define UPA_CFG 0 50 #define UPA_IMR1 1 51 #define UPA_IMR2 2 52 53 /* UPA_CFG bank */ 54 #define UPA_CFG_UPA0 0x00 /* UPA0 config register */ 55 #define UPA_CFG_UPA1 0x08 /* UPA1 config register */ 56 #define UPA_CFG_IF 0x10 /* interface config register */ 57 #define UPA_CFG_IF_RST 0x00 58 #define UPA_CFG_IF_POK_RST 0x02 59 #define UPA_CFG_IF_POK 0x03 60 #define UPA_CFG_ESTAR 0x18 /* Estar config register */ 61 #define UPA_CFG_ESTAR_SPEED_FULL 0x01 62 #define UPA_CFG_ESTAR_SPEED_1_2 0x02 63 #define UPA_CFG_ESTAR_SPEED_1_64 0x40 64 65 #define UPA_INO_BASE 0x2a 66 #define UPA_INO_MAX 0x2b 67 68 struct upa_regs { 69 uint64_t phys; 70 uint64_t size; 71 }; 72 73 struct upa_ranges { 74 uint64_t child; 75 uint64_t parent; 76 uint64_t size; 77 }; 78 79 struct upa_devinfo { 80 struct ofw_bus_devinfo udi_obdinfo; 81 struct resource_list udi_rl; 82 }; 83 84 struct upa_softc { 85 struct resource *sc_res[UPA_NREG]; 86 bus_space_tag_t sc_bt[UPA_NREG]; 87 bus_space_handle_t sc_bh[UPA_NREG]; 88 89 uint32_t sc_ign; 90 91 int sc_nrange; 92 struct upa_ranges *sc_ranges; 93 }; 94 95 #define UPA_READ(sc, reg, off) \ 96 bus_space_read_8((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off)) 97 #define UPA_WRITE(sc, reg, off, val) \ 98 bus_space_write_8((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off), (val)) 99 100 static device_probe_t upa_probe; 101 static device_attach_t upa_attach; 102 static bus_alloc_resource_t upa_alloc_resource; 103 static bus_setup_intr_t upa_setup_intr; 104 static bus_print_child_t upa_print_child; 105 static bus_probe_nomatch_t upa_probe_nomatch; 106 static bus_get_resource_list_t upa_get_resource_list; 107 static ofw_bus_get_devinfo_t upa_get_devinfo; 108 109 static void upa_intr_enable(void *); 110 static void upa_intr_disable(void *); 111 static struct upa_devinfo *upa_setup_dinfo(device_t, struct upa_softc *, 112 phandle_t, uint32_t); 113 static void upa_destroy_dinfo(struct upa_devinfo *); 114 static int upa_print_res(struct upa_devinfo *); 115 116 static device_method_t upa_methods[] = { 117 /* Device interface */ 118 DEVMETHOD(device_probe, upa_probe), 119 DEVMETHOD(device_attach, upa_attach), 120 DEVMETHOD(device_shutdown, bus_generic_shutdown), 121 DEVMETHOD(device_suspend, bus_generic_suspend), 122 DEVMETHOD(device_resume, bus_generic_resume), 123 124 /* Bus interface */ 125 DEVMETHOD(bus_print_child, upa_print_child), 126 DEVMETHOD(bus_probe_nomatch, upa_probe_nomatch), 127 DEVMETHOD(bus_read_ivar, bus_generic_read_ivar), 128 DEVMETHOD(bus_write_ivar, bus_generic_write_ivar), 129 DEVMETHOD(bus_alloc_resource, upa_alloc_resource), 130 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 131 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 132 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 133 DEVMETHOD(bus_setup_intr, upa_setup_intr), 134 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 135 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 136 DEVMETHOD(bus_get_resource_list, upa_get_resource_list), 137 138 /* ofw_bus interface */ 139 DEVMETHOD(ofw_bus_get_devinfo, upa_get_devinfo), 140 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 141 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 142 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 143 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 144 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 145 146 { NULL, NULL } 147 }; 148 149 static devclass_t upa_devclass; 150 151 DEFINE_CLASS_0(upa, upa_driver, upa_methods, sizeof(struct upa_softc)); 152 DRIVER_MODULE(upa, nexus, upa_driver, upa_devclass, 0, 0); 153 154 static const struct intr_controller upa_ic = { 155 upa_intr_enable, 156 upa_intr_disable, 157 /* The interrupts are pulse type and thus automatically cleared. */ 158 NULL 159 }; 160 161 struct upa_icarg { 162 struct upa_softc *uica_sc; 163 u_int uica_imr; 164 }; 165 166 static int 167 upa_probe(device_t dev) 168 { 169 const char* compat; 170 171 compat = ofw_bus_get_compat(dev); 172 if (compat != NULL && strcmp(ofw_bus_get_name(dev), "upa") == 0 && 173 strcmp(compat, "upa64s") == 0) { 174 device_set_desc(dev, "UPA bridge"); 175 return (BUS_PROBE_DEFAULT); 176 } 177 return (ENXIO); 178 } 179 180 static int 181 upa_attach(device_t dev) 182 { 183 struct upa_devinfo *udi; 184 struct upa_icarg *uica; 185 struct upa_softc *sc; 186 phandle_t child, node; 187 device_t cdev; 188 uint32_t portid; 189 int i, imr, j, rid; 190 #if 1 191 device_t *children, schizo; 192 u_long scount, sstart, ucount, ustart; 193 int nchildren; 194 #endif 195 196 sc = device_get_softc(dev); 197 node = ofw_bus_get_node(dev); 198 for (i = UPA_CFG; i <= UPA_IMR2; i++) { 199 rid = i; 200 /* 201 * The UPA_IMR{1,2} resources are shared with that of the 202 * Schizo PCI bus B CSR bank. 203 */ 204 #if 0 205 sc->sc_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 206 &rid, ((i == UPA_IMR1 || i == UPA_IMR2) ? RF_SHAREABLE : 207 0) | RF_ACTIVE); 208 if (sc->sc_res[i] == NULL) { 209 device_printf(dev, 210 "could not allocate resource %d\n", i); 211 goto fail; 212 } 213 sc->sc_bt[i] = rman_get_bustag(sc->sc_res[i]); 214 sc->sc_bh[i] = rman_get_bushandle(sc->sc_res[i]); 215 #else 216 /* 217 * Workaround for the fact that rman(9) only allows to 218 * share resources of the same size. 219 */ 220 if (i == UPA_IMR1 || i == UPA_IMR2) { 221 if (bus_get_resource(dev, SYS_RES_MEMORY, i, &ustart, 222 &ucount) != 0) { 223 device_printf(dev, 224 "could not determine UPA resource\n"); 225 goto fail; 226 } 227 if (device_get_children(device_get_parent(dev), 228 &children, &nchildren) != 0) { 229 device_printf(dev, "could not get children\n"); 230 goto fail; 231 } 232 schizo = NULL; 233 for (j = 0; j < nchildren; j++) { 234 if (ofw_bus_get_type(children[j]) != NULL && 235 strcmp(ofw_bus_get_type(children[j]), 236 "pci") == 0 && 237 ofw_bus_get_compat(children[j]) != NULL && 238 strcmp(ofw_bus_get_compat(children[j]), 239 "pci108e,8001") == 0 && 240 ((bus_get_resource_start(children[j], 241 SYS_RES_MEMORY, 0) >> 20) & 1) == 1) { 242 schizo = children[j]; 243 break; 244 } 245 } 246 free(children, M_TEMP); 247 if (schizo == NULL) { 248 device_printf(dev, "could not find Schizo\n"); 249 goto fail; 250 } 251 if (bus_get_resource(schizo, SYS_RES_MEMORY, 0, 252 &sstart, &scount) != 0) { 253 device_printf(dev, 254 "could not determine Schizo resource\n"); 255 goto fail; 256 } 257 sc->sc_res[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, 258 &rid, sstart, sstart + scount - 1, scount, 259 RF_SHAREABLE | RF_ACTIVE); 260 } else 261 sc->sc_res[i] = bus_alloc_resource_any(dev, 262 SYS_RES_MEMORY, &rid, RF_ACTIVE); 263 if (sc->sc_res[i] == NULL) { 264 device_printf(dev, 265 "could not allocate resource %d\n", i); 266 goto fail; 267 } 268 sc->sc_bt[i] = rman_get_bustag(sc->sc_res[i]); 269 sc->sc_bh[i] = rman_get_bushandle(sc->sc_res[i]); 270 if (i == UPA_IMR1 || i == UPA_IMR2) 271 bus_space_subregion(sc->sc_bt[i], sc->sc_bh[i], 272 ustart - sstart, ucount, &sc->sc_bh[i]); 273 #endif 274 } 275 276 if (OF_getprop(node, "portid", &sc->sc_ign, sizeof(sc->sc_ign)) == -1) { 277 device_printf(dev, "could not determine IGN\n"); 278 goto fail; 279 } 280 281 sc->sc_nrange = OF_getprop_alloc(node, "ranges", sizeof(*sc->sc_ranges), 282 (void **)&sc->sc_ranges); 283 if (sc->sc_nrange == -1) { 284 device_printf(dev, "could not determine ranges\n"); 285 goto fail; 286 } 287 288 /* 289 * Hunt through all the interrupt mapping regs and register our 290 * interrupt controller for the corresponding interrupt vectors. 291 */ 292 for (i = UPA_INO_BASE; i <= UPA_INO_MAX; i++) { 293 imr = 0; 294 for (j = UPA_IMR1; j <= UPA_IMR2; j++) { 295 if (INTVEC(UPA_READ(sc, j, 0x0)) == 296 INTMAP_VEC(sc->sc_ign, i)) { 297 imr = j; 298 break; 299 } 300 } 301 if (imr == 0) 302 continue; 303 uica = malloc(sizeof(*uica), M_DEVBUF, M_NOWAIT); 304 if (uica == NULL) 305 panic("%s: could not allocate interrupt controller " 306 "argument", __func__); 307 uica->uica_sc = sc; 308 uica->uica_imr = imr; 309 #ifdef UPA_DEBUG 310 device_printf(dev, "intr map (INO %d) IMR%d: %#lx\n", 311 i, imr, (u_long)UPA_READ(sc, imr, 0x0)); 312 #endif 313 if (intr_controller_register(INTMAP_VEC(sc->sc_ign, i), 314 &upa_ic, uica) != 0) 315 panic("%s: could not register interrupt controller " 316 "for INO %d", __func__, i); 317 } 318 319 /* Make sure the power level is appropriate for normal operation. */ 320 if (UPA_READ(sc, UPA_CFG, UPA_CFG_IF) != UPA_CFG_IF_POK) { 321 if (bootverbose) 322 device_printf(dev, "applying power\n"); 323 UPA_WRITE(sc, UPA_CFG, UPA_CFG_ESTAR, UPA_CFG_ESTAR_SPEED_1_2); 324 UPA_WRITE(sc, UPA_CFG, UPA_CFG_ESTAR, UPA_CFG_ESTAR_SPEED_FULL); 325 (void)UPA_READ(sc, UPA_CFG, UPA_CFG_ESTAR); 326 UPA_WRITE(sc, UPA_CFG, UPA_CFG_IF, UPA_CFG_IF_POK_RST); 327 (void)UPA_READ(sc, UPA_CFG, UPA_CFG_IF); 328 DELAY(20000); 329 UPA_WRITE(sc, UPA_CFG, UPA_CFG_IF, UPA_CFG_IF_POK); 330 (void)UPA_READ(sc, UPA_CFG, UPA_CFG_IF); 331 } 332 333 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 334 /* 335 * The `upa-portid' properties of the children are used as 336 * index for the interrupt mapping registers. 337 * The `upa-portid' properties are also used to make up the 338 * INOs of the children as the values contained in their 339 * `interrupts' properties are bogus. 340 */ 341 if (OF_getprop(child, "upa-portid", &portid, 342 sizeof(portid)) == -1) { 343 device_printf(dev, 344 "could not determine upa-portid of child 0x%lx\n", 345 (unsigned long)child); 346 continue; 347 } 348 if (portid > 1) { 349 device_printf(dev, 350 "upa-portid %d of child 0x%lx invalid\n", portid, 351 (unsigned long)child); 352 continue; 353 } 354 if ((udi = upa_setup_dinfo(dev, sc, child, portid)) == NULL) 355 continue; 356 if ((cdev = device_add_child(dev, NULL, -1)) == NULL) { 357 device_printf(dev, "<%s>: device_add_child failed\n", 358 udi->udi_obdinfo.obd_name); 359 upa_destroy_dinfo(udi); 360 continue; 361 } 362 device_set_ivars(cdev, udi); 363 } 364 365 return (bus_generic_attach(dev)); 366 367 fail: 368 for (i = UPA_CFG; i <= UPA_IMR2 && sc->sc_res[i] != NULL; i++) 369 bus_release_resource(dev, SYS_RES_MEMORY, 370 rman_get_rid(sc->sc_res[i]), sc->sc_res[i]); 371 return (ENXIO); 372 } 373 374 static int 375 upa_print_child(device_t dev, device_t child) 376 { 377 int rv; 378 379 rv = bus_print_child_header(dev, child); 380 rv += upa_print_res(device_get_ivars(child)); 381 rv += bus_print_child_footer(dev, child); 382 return (rv); 383 } 384 385 static void 386 upa_probe_nomatch(device_t dev, device_t child) 387 { 388 const char *type; 389 390 device_printf(dev, "<%s>", ofw_bus_get_name(child)); 391 upa_print_res(device_get_ivars(child)); 392 type = ofw_bus_get_type(child); 393 printf(" type %s (no driver attached)\n", 394 type != NULL ? type : "unknown"); 395 } 396 397 static struct resource * 398 upa_alloc_resource(device_t dev, device_t child, int type, int *rid, 399 u_long start, u_long end, u_long count, u_int flags) 400 { 401 struct resource_list *rl; 402 struct resource_list_entry *rle; 403 struct upa_softc *sc; 404 struct resource *rv; 405 bus_addr_t cend, cstart; 406 int i, isdefault, passthrough; 407 408 isdefault = (start == 0UL && end == ~0UL); 409 passthrough = (device_get_parent(child) != dev); 410 sc = device_get_softc(dev); 411 rl = BUS_GET_RESOURCE_LIST(dev, child); 412 rle = NULL; 413 switch (type) { 414 case SYS_RES_IRQ: 415 return (resource_list_alloc(rl, dev, child, type, rid, start, 416 end, count, flags)); 417 case SYS_RES_MEMORY: 418 if (!passthrough) { 419 rle = resource_list_find(rl, type, *rid); 420 if (rle == NULL) 421 return (NULL); 422 if (rle->res != NULL) 423 panic("%s: resource entry is busy", __func__); 424 if (isdefault) { 425 start = rle->start; 426 count = ulmax(count, rle->count); 427 end = ulmax(rle->end, start + count - 1); 428 } 429 } 430 for (i = 0; i < sc->sc_nrange; i++) { 431 cstart = sc->sc_ranges[i].child; 432 cend = cstart + sc->sc_ranges[i].size - 1; 433 if (start < cstart || start > cend) 434 continue; 435 if (end < cstart || end > cend) 436 return (NULL); 437 start += sc->sc_ranges[i].parent - cstart; 438 end += sc->sc_ranges[i].parent - cstart; 439 rv = bus_generic_alloc_resource(dev, child, type, rid, 440 start, end, count, flags); 441 if (!passthrough) 442 rle->res = rv; 443 return (rv); 444 } 445 /* FALLTHROUGH */ 446 default: 447 return (NULL); 448 } 449 } 450 451 static void 452 upa_intr_enable(void *arg) 453 { 454 struct intr_vector *iv = arg; 455 struct upa_icarg *uica = iv->iv_icarg; 456 457 UPA_WRITE(uica->uica_sc, uica->uica_imr, 0x0, 458 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid)); 459 (void)UPA_READ(uica->uica_sc, uica->uica_imr, 0x0); 460 } 461 462 static void 463 upa_intr_disable(void *arg) 464 { 465 struct intr_vector *iv = arg; 466 struct upa_icarg *uica = iv->iv_icarg; 467 468 UPA_WRITE(uica->uica_sc, uica->uica_imr, 0x0, iv->iv_vec); 469 (void)UPA_READ(uica->uica_sc, uica->uica_imr, 0x0); 470 } 471 472 static int 473 upa_setup_intr(device_t dev, device_t child, struct resource *ires, int flags, 474 driver_filter_t *filt, driver_intr_t *func, void *arg, void **cookiep) 475 { 476 struct upa_softc *sc; 477 u_long vec; 478 479 sc = device_get_softc(dev); 480 /* 481 * Make sure the vector is fully specified and we registered 482 * our interrupt controller for it. 483 */ 484 vec = rman_get_start(ires); 485 if (INTIGN(vec) != sc->sc_ign || intr_vectors[vec].iv_ic != &upa_ic) { 486 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec); 487 return (EINVAL); 488 } 489 return (bus_generic_setup_intr(dev, child, ires, flags, filt, func, 490 arg, cookiep)); 491 } 492 493 static struct resource_list * 494 upa_get_resource_list(device_t dev, device_t child) 495 { 496 struct upa_devinfo *udi; 497 498 udi = device_get_ivars(child); 499 return (&udi->udi_rl); 500 } 501 502 static const struct ofw_bus_devinfo * 503 upa_get_devinfo(device_t dev, device_t child) 504 { 505 struct upa_devinfo *udi; 506 507 udi = device_get_ivars(child); 508 return (&udi->udi_obdinfo); 509 } 510 511 static struct upa_devinfo * 512 upa_setup_dinfo(device_t dev, struct upa_softc *sc, phandle_t node, 513 uint32_t portid) 514 { 515 struct upa_devinfo *udi; 516 struct upa_regs *reg; 517 uint32_t intr; 518 int i, nreg; 519 520 udi = malloc(sizeof(*udi), M_DEVBUF, M_WAITOK | M_ZERO); 521 if (ofw_bus_gen_setup_devinfo(&udi->udi_obdinfo, node) != 0) { 522 free(udi, M_DEVBUF); 523 return (NULL); 524 } 525 resource_list_init(&udi->udi_rl); 526 527 nreg = OF_getprop_alloc(node, "reg", sizeof(*reg), (void **)®); 528 if (nreg == -1) { 529 device_printf(dev, "<%s>: incomplete\n", 530 udi->udi_obdinfo.obd_name); 531 goto fail; 532 } 533 for (i = 0; i < nreg; i++) 534 resource_list_add(&udi->udi_rl, SYS_RES_MEMORY, i, reg[i].phys, 535 reg[i].phys + reg[i].size - 1, reg[i].size); 536 free(reg, M_OFWPROP); 537 538 intr = INTMAP_VEC(sc->sc_ign, (UPA_INO_BASE + portid)); 539 resource_list_add(&udi->udi_rl, SYS_RES_IRQ, 0, intr, intr, 1); 540 541 return (udi); 542 543 fail: 544 upa_destroy_dinfo(udi); 545 return (NULL); 546 } 547 548 static void 549 upa_destroy_dinfo(struct upa_devinfo *dinfo) 550 { 551 552 resource_list_free(&dinfo->udi_rl); 553 ofw_bus_gen_destroy_devinfo(&dinfo->udi_obdinfo); 554 free(dinfo, M_DEVBUF); 555 } 556 557 static int 558 upa_print_res(struct upa_devinfo *udi) 559 { 560 int rv; 561 562 rv = 0; 563 rv += resource_list_print_type(&udi->udi_rl, "mem", SYS_RES_MEMORY, 564 "%#lx"); 565 rv += resource_list_print_type(&udi->udi_rl, "irq", SYS_RES_IRQ, 566 "%ld"); 567 return (rv); 568 }
Cache object: 7d127d5399994ddf442792eaf2529368
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