The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/sqt/bic.h

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    1 /* 
    2  * Mach Operating System
    3  * Copyright (c) 1991 Carnegie Mellon University
    4  * Copyright (c) 1991 Sequent Computer Systems
    5  * All Rights Reserved.
    6  * 
    7  * Permission to use, copy, modify and distribute this software and its
    8  * documentation is hereby granted, provided that both the copyright
    9  * notice and this permission notice appear in all copies of the
   10  * software, derivative works or modified versions, and any portions
   11  * thereof, and that both notices appear in supporting documentation.
   12  * 
   13  * CARNEGIE MELLON AND SEQUENT COMPUTER SYSTEMS ALLOW FREE USE OF
   14  * THIS SOFTWARE IN ITS "AS IS" CONDITION.  CARNEGIE MELLON AND
   15  * SEQUENT COMPUTER SYSTEMS DISCLAIM ANY LIABILITY OF ANY KIND FOR
   16  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   17  * 
   18  * Carnegie Mellon requests users of this software to return to
   19  * 
   20  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   21  *  School of Computer Science
   22  *  Carnegie Mellon University
   23  *  Pittsburgh PA 15213-3890
   24  * 
   25  * any improvements or extensions that they make and grant Carnegie Mellon 
   26  * the rights to redistribute these changes.
   27  */
   28 
   29 /*
   30  * HISTORY
   31  * $Log:        bic.h,v $
   32  * Revision 2.3  91/07/31  17:59:42  dbg
   33  *      Changed copyright.
   34  *      [91/07/31            dbg]
   35  * 
   36  * Revision 2.2  91/05/08  12:53:02  dbg
   37  *      Added from Sequent SYMMETRY sources.
   38  *      [91/04/26  14:48:22  dbg]
   39  * 
   40  */
   41 
   42 /*
   43  * $Header: bic.h,v 2.3 91/07/31 17:59:42 dbg Exp $
   44  *
   45  * Bus Interface Controller (BIC) sub-registers and bits.
   46  */
   47 
   48 /*
   49  * Revision 1.1  89/07/19  14:48:51  kak
   50  * Initial revision
   51  * 
   52  * Revision 2.29  88/11/10  19:24:27  gak
   53  * Add neals requests for CMC and BIC performance counters.
   54  * 
   55  * Revision 2.28  88/03/24  14:06:33  gak
   56  * Remove unused bits from diag control register
   57  * 
   58  * Revision 2.27  88/03/23  07:42:45  gak
   59  * Update for Model B and Rev 3 BIC
   60  * 
   61  */
   62 
   63 #ifndef _SQT_BIC_H_
   64 #define _SQT_BIC_H_
   65 
   66 /*
   67  * BIC ID Register: Read Only.
   68  */
   69 
   70 #define BIC_ID          0x00            /* ID register */
   71 #define     BICI_VAL    0x01            /* what the BIC says it is */
   72 
   73 /*
   74  * BIC Version Register: Read Only.
   75  */
   76 
   77 #define BIC_VERSION     0x01            /* version number */
   78 #define     BICV_VER_MASK       0xF0    /* mask of version number bits */
   79 #define     BICV_REV_MASK       0x0F    /* mask of revision number bits */
   80 
   81 #define     BICV_REVISION(x)    ((x) & BICV_REV_MASK)
   82 #define     BICV_VERSION(x)     (((x) & BICV_VER_MASK) >> 4)
   83 
   84 /*
   85  * BIC Policy Register:  Read/Write.  Resets to 0.  BIC Global.
   86  */
   87 
   88 #define BIC_POLICY      0x02            /* policy register */
   89 #define     BICP_MASK   0xFF            /* useful bits */
   90 #define     BICP_FWRESP 0x80            /* fast write response allowed */
   91 #define     BICP_BSIZ   0x60            /* block size */
   92 #define         BICP_BSIZ_8     0x20            /* block size 8 */
   93 #define         BICP_BSIZ_16    0x00            /* block size 16 */
   94 #define         BICP_BSIZ_32    0x40            /* block size 32 */
   95 #define     BICP_WIDE   0x10            /* wide bus */
   96 #define     BICP_COMPAT 0x08            /* compatibility mode */
   97 #define     BICP_FIXARB 0x04            /* fixed arbitration */
   98 #define     BICP_2DEEP  0x02            /* two deep read pipe */
   99 #define     BICP_DRRESP 0x01            /* delayed read response */
  100 
  101 /*
  102  * BIC Error Control:  Read/Write.  Resets to 0.  BIC Global.
  103  */
  104 
  105 #define BIC_ERRCTL      0x03            /* error control register */
  106 #define     BICEC_MASK          0xBF    /* useful bits */
  107 #define     BICEC_DRV_PAUSE     0x80    /* I'm driving PAUSE */
  108 #define     BICEC_PULSE_BE      0x40    /* (see BICEC_MASK) Always 0 */
  109 #define     BICEC_CT_PERR       0x20    /* parity error seen on cycle type */
  110 #define     BICEC_FRC_PERR      0x10    /* force a parity error */
  111 #define     BICEC_IGN_BERR      0x08    /* ignore Bus Error from bus */
  112 #define     BICEC_ENA_BERR      0x04    /* enable Bus Error signalling */
  113 #define     BICEC_CLR_PAUSE     0x02    /* reset PAUSE on the bus */
  114 #define     BICEC_ENA_PAUSE     0x01    /* enable PAUSE on the bus */
  115 
  116 /*
  117  * BIC Bus Error:  Read Only.  Writing Clears it.  BIC Global.
  118  * Only accessible from "B" (or "1") side of processor board.
  119  * SLIC error bits may not be implemented.
  120  */
  121 
  122 #define BIC_BUSERR      0x04            /* bus error bits */
  123 #define     BICBE_MASK  0x0F            /* useful bits */
  124 #define     BICBE_DBE   SLB_DBE         /* I detected a bus error */
  125 #define     BICBE_SBE   SLB_SBE         /* I saw BusError on backplane */
  126 #define     BICBE_RBE   SLB_RBE         /* I was taking during error */
  127 #define     BICBE_IBE   SLB_IBE         /* I was sending during error */
  128 
  129 /*
  130  * SLIC Error Register: Read Only.  Write Clears.
  131  * Contains data from both SLICs.
  132  */
  133 
  134 #define BIC_SLICERR     0x05            /* SLIC error bits */
  135 #define     BICSE_MASK  0xFF            /* useful bits */
  136 #define     BICSE_DSE1  0x80            /* I detected the SLIC error */
  137 #define     BICSE_SSE1  0x40            /* I saw the SLIC error signalled */
  138 #define     BICSE_RSE1  0x20            /* I received data during SLIC error */
  139 #define     BICSE_ISE1  0x10            /* I transmitted during SLIC error */
  140 #define     BICSE_DSE0  0x08            /* I detected the SLIC error */
  141 #define     BICSE_SSE0  0x04            /* I saw the SLIC error signalled */
  142 #define     BICSE_RSE0  0x02            /* I received data during SLIC error */
  143 #define     BICSE_ISE0  0x01            /* I transmitted during SLIC error */
  144 
  145 /*
  146  * BIC Diagnostic Control:  Read/Write.  Resets to 0.  BIC Global.
  147  */
  148 
  149 #define BIC_DIAGCTL     0x06            /* diagnostic control */
  150 #define     BICDC_MASK  0x01            /* useful bits */
  151 #define     BICDC_FRC_PAUSE     0x01    /* assert PAUSE on the bus */
  152 
  153 /*
  154  * BIC Diagnostic Cycle Type:  Not reset.  BIC Global.
  155  * Separate register to read/write.
  156  */
  157 
  158 #define BIC_DIAG_CYCTYPE        0x07    /* diagnostic cycle type */
  159 #define     BICCT_MASK  0xFF            /* useful bits */
  160 #define     BICCT_PAR   0x80            /* cycle type parity */
  161 #define     BICCT_TYPE  0x7F            /* cycle type mask (6:0) */
  162 
  163 /*
  164  * BIC Diagnostic RW Response Codes:  Not reset.  BIC Global.
  165  * Separate register to read/write.
  166  */
  167 
  168 #define BIC_DIAG_RWRESP         0x08    /* diagnostic RW response codes */
  169 #define     BICRW_MASK          0xFF    /* useful bits */
  170 #define     BICRW_RDRESP        0xF0    /* read response code (mask) */
  171 #define     BICRW_WRRESP        0x0F    /* write response code (mask) */
  172 
  173 /*
  174  * BIC Diagnostic IO Response Codes:  Not reset.  BIC Global.
  175  * Separate register to read/write.
  176  */
  177 
  178 #define BIC_DIAG_IO_RESP        0x09    /* diagnostic IO response codes */
  179 #define BICIO_MASK              0x0F    /* useful bits */
  180 
  181 /*
  182  * BIC Timeout Control: s/w sets on one BIC per system. reset to zero.
  183  *
  184  * Macros specify clock ticks truncated to 16 tick intervals (1.6 uSec).
  185  */
  186 #define BIC_TIMEOUT     0x0A
  187 #define     BICTO_NONE          0x00    /* None */
  188 
  189 #define BICTO_IO(clk_ticks)     ((u_char)((clk_ticks) & 0xF0))
  190 #define BICTO_MEM(clk_ticks)    ((u_char)(((clk_ticks) >> 4) & 0x0F))
  191 
  192 /*
  193  * BIC Access Error:  Read only, Write clears it.  Per channel.
  194  */
  195 
  196 #define BIC_ACCERR0     0x10            /* channel 0 access error */
  197 #define BIC_ACCERR1     0x18            /* channel 1 access error */
  198 #define     BICAE_MASK          0x3f    /* useful bits */
  199 #define     BICAE_OCC           0x20    /* access error has occurred */
  200 #define     BICAE_IO            0x10    /* IO access */
  201 #define     BICAE_READ          0x08    /* read access */
  202 #define     BICAE_RESP_MASK     0x07    /* response code mask */
  203 #define     BICAE_TIMEOUT       0x00    /* response was bus timeout */
  204 #define     BICAE_FATAL         0x03    /* fatal error response */
  205 #define     BICAE_NONFATAL      0x05    /* non-fatal error response */
  206 #define     BICAE_GOOD          0x06    /* good response */
  207 
  208 /*
  209  * BIC Channel Control:  Read/Write.  Resets to 0.  Per channel.
  210  */
  211 
  212 #define BIC_CHNCTL0     0x11            /* channel 0 control */
  213 #define BIC_CHNCTL1     0x19            /* channel 1 control */
  214 #define     BICC_MASK           0xFF    /* useful bits */
  215 #define     BICC_ASYNC          0x80    /* async inputs */
  216 #define     BICC_ACCLCK         0x40    /* accelerator style locking */
  217 #define     BICC_EXT            0x20    /* ext. resp. code gen. for reads */
  218 #define     BICC_IGN_DEVFLT     0x10    /* ignore device fault input */
  219 #define     BICC_IOCHAN         0x08    /* 1=i/o responder */
  220 #define     BICC_BIG_Q          0x04    /* mem bds, INQ0 alter with INQ1 */
  221 #define     BICC_CHAN_RESET     0x02    /* Channel reset, must write & clear */
  222 #define     BICC_NFACC          0x01    /* non fatal errors gen access errors */
  223 
  224 /*
  225  * BIC Diagnostic Request:  Read/Write.  Bit 0 resets to 0.  Per Channel.
  226  */
  227 
  228 #define BIC_DIAGREQ0    0x13            /* channel 0 diagnostic request */
  229 #define BIC_DIAGREQ1    0x1B            /* channel 1 diagnostic request */
  230 #define     BICRQ_MASK  0xFF            /* useful bits */
  231 #define     BICRQ_TYPE  0xE0            /* type(2:0) */
  232 #define         BICRQ_RA        0x00    /* read miss to invalid block */
  233 #define         BICRQ_RAI       0x20    /* write miss to invalid block */
  234 #define         BICRQ_IA        0x40    /* write hit to shared block */
  235 #define         BICRQ_WAI       0x60    /* write to non cacheable block */
  236 #define         BICRQ_RAWA      0x80    /* read miss to modified block */
  237 #define         BUCRQ_RAIWA     0xA0    /* write miss to modified */
  238 #define         BUCRQ_WA        0xE0    /* write back (flush) */
  239 #define     BICRQ_SIZE  0x18            /* size(1:0) */
  240 #define         BICRQ_SIZE4     0x00    /* 4 or fewer bytes */
  241 #define         BICRQ_SIZE8     0x08    /* 8 bytes */
  242 #define         BICRQ_SIZE16    0x10    /* 16 bytes */
  243 #define         BICRQ_SIZE32    0x18    /* 32 bytes */
  244 #define     BICRQ_IOOP  0x04            /* IOOP */
  245 #define     BICRQ_ILOCK 0x02            /* ILOCK */
  246 #define     BICRQ_MKREQ 0x01            /* generate request on positive edge */
  247 
  248 /*
  249  * BIC Channel Diagnostic Control:  Read/Write.  Per channel.
  250  */
  251 
  252 #define BIC_CDIAGCTL0   0x14            /* channel 0 diagnostic control */
  253 #define BIC_CDIAGCTL1   0x1C            /* channel 1 diagnostic control */
  254 #define     BICCDC_MASK         0xFF    /* useful bits */
  255 #define     BICCDC_ENA_RESP     0x80    /* enable diag response mode */
  256 #define     BICCDC_CPBACK       0x40    /* copy back  */
  257 #define     BICCDC_CANCEL       0x20    /* cancel */
  258 #define     BICCDC_ENA_REQ      0x10    /* enable diagnostic request mode */
  259 #define     BICCDC_IBUSY        0x08    /* busy making request */
  260 #define     BICCDC_MODELB       0x04    /* bit set for Model B boards */
  261 #define     BICCDC_DISABLE      0x02    /* disable this channel */
  262 #define     BICCDC_FRC_MUX      0x01    /* force address mux to local bus */
  263 
  264 /*
  265  * BIC Tachometer Controls:
  266  *      The tachometer is a bus cycle type counter for system bus
  267  *      profiling. Refer to the Hardware Functional Specifications 
  268  *      for more information.
  269  */
  270 
  271 #define BIC_TACH0       0x20            /* R/W counter lsb */
  272 #define BIC_TACH1       0x21            /* R/W counter */
  273 #define BIC_TACH2       0x22            /* R/W counter */
  274 #define BIC_TACH3       0x23            /* R/W counter msb */
  275 #define BIC_TACH_SEL0   0x24            /* R/W diag(7), cyc_type(6:0) */
  276 #define BIC_TACH_SEL    BIC_TACH_SEL0   /* for backwards compatibility */
  277 #define     BICTS_DIAG  0x80            /* diag bit within tach select */
  278 #define BIC_TACH_MASK0  0x25            /* R/W 7:0  0: match, 1: don't care */
  279 #define BIC_TACH_MASK   BIC_TACH_MASK0  /* for backwards compatibility */
  280 #define BIC_TACH_ZSTART 0x26            /* W: zero,start; R: stop */
  281 #define BIC_TACH_START  0x27            /* W: start */
  282 #define BIC_TACH_SEL1   0x28
  283 #define BIC_TACH_MASK1  0x29
  284 
  285 #endif  /* _SQT_BIC_H_ */

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