The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/sqt/buscycles.h

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    1 /* 
    2  * Mach Operating System
    3  * Copyright (c) 1991 Carnegie Mellon University
    4  * Copyright (c) 1991 Sequent Computer Systems
    5  * All Rights Reserved.
    6  * 
    7  * Permission to use, copy, modify and distribute this software and its
    8  * documentation is hereby granted, provided that both the copyright
    9  * notice and this permission notice appear in all copies of the
   10  * software, derivative works or modified versions, and any portions
   11  * thereof, and that both notices appear in supporting documentation.
   12  * 
   13  * CARNEGIE MELLON AND SEQUENT COMPUTER SYSTEMS ALLOW FREE USE OF
   14  * THIS SOFTWARE IN ITS "AS IS" CONDITION.  CARNEGIE MELLON AND
   15  * SEQUENT COMPUTER SYSTEMS DISCLAIM ANY LIABILITY OF ANY KIND FOR
   16  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   17  * 
   18  * Carnegie Mellon requests users of this software to return to
   19  * 
   20  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   21  *  School of Computer Science
   22  *  Carnegie Mellon University
   23  *  Pittsburgh PA 15213-3890
   24  * 
   25  * any improvements or extensions that they make and grant Carnegie Mellon 
   26  * the rights to redistribute these changes.
   27  */
   28 
   29 /*
   30  * HISTORY
   31  * $Log:        buscycles.h,v $
   32  * Revision 2.3  91/07/31  17:59:49  dbg
   33  *      Changed copyright.
   34  *      [91/07/31            dbg]
   35  * 
   36  * Revision 2.2  91/05/08  12:53:55  dbg
   37  *      Added, from Sequent SYMMETRY sources.
   38  *      [91/04/26  14:48:45  dbg]
   39  * 
   40  */
   41 
   42 /*
   43  * $Header: buscycles.h,v 2.3 91/07/31 17:59:49 dbg Exp $
   44  *
   45  * Definitions and macros for SB8000 Bus cycles.
   46  */
   47 
   48 /*
   49  * Revision 1.1  89/07/19  14:48:51  kak
   50  * Initial revision
   51  * 
   52  */
   53 
   54 #ifndef _SQT_BUSCYCLES_H_
   55 #define _SQT_BUSCYCLES_H_
   56 
   57 /*
   58  * cycle types for sgs are defined below as a 7 bit field.
   59  * (re: SGS h/w func. spec. "Cycle Type section").
   60  *
   61  * Note: 'x' means don't care and will be set to a one to be
   62  * consistent with the Mentor simulations (aka floats high).
   63  */
   64 #define CT_MASK         0x7F            /* Usable bits */
   65 #define CT_WA4                  0x78    /* 111 1000 */
   66 #define CT_WA4_N                0x38    /* 011 1000 */
   67 #define CT_WA8                  0x7A    /* 111 1010 */
   68 #define CT_WA8_N                0x3A    /* 011 1010 */
   69 #define CT_WA8_W                0x58    /* 101 1000 */
   70 #define CT_WA8_NW               0x18    /* 001 1000 */
   71 #define CT_WA16                 0x68    /* 110 1000 */
   72 #define CT_WA16_N               0x28    /* 010 1000 */
   73 #define CT_WA16_W               0x5A    /* 101 1010 */
   74 #define CT_WA16_NW              0x1A    /* 001 1010 */
   75 #define CT_WA32_W               0x08    /* 000 1000 */
   76 #define CT_WA32_IW              0x48    /* 100 1000 */
   77         
   78 #define CT_WDF                  0x7C    /* x1x 1100 */
   79 #define CT_WDL                  0x7D    /* x1x 1101 */
   80 #define CT_WDF_W                0x5C    /* x0x 1100 */
   81 #define CT_WDL_W                0x5D    /* x0x 1101 */
   82 
   83 #define CT_RA4                  0x71    /* 111 0001 */
   84 #define CT_RA4_I                0x31    /* 011 0001 */
   85 #define CT_RA8                  0x73    /* 111 0011 */
   86 #define CT_RA8_I                0x33    /* 011 0011 */
   87 #define CT_RA8_W                0x51    /* 101 0001 */
   88 #define CT_RA8_IW               0x11    /* 001 0001 */
   89 #define CT_RA16                 0x61    /* 110 0001 */
   90 #define CT_RA16_I               0x21    /* 010 0001 */
   91 #define CT_RA16_W               0x53    /* 101 0011 */
   92 #define CT_RA16_IW              0x13    /* 001 0011 */
   93 #define CT_RA32_W               0x41    /* 100 0001 */
   94 #define CT_RA32_IW              0x01    /* 000 0001 */
   95 
   96 #define CT_RDF                  0x74    /* x1x 0100 */
   97 #define CT_RDF_W                0x54    /* x0x 0100 */
   98 #define CT_RDL                  0x75    /* x1x 0101 */
   99 #define CT_RDL_W                0x55    /* x0x 0101 */
  100 
  101 #define CT_IA                   0x3F    /* 0xx 1111 */
  102 #define CT_ULA                  0x5F    /* 10x 1111 */
  103 #define CT_IDLE                 0x7F    /* 11x 1111 */
  104 
  105 /*
  106  * Cycle type macros.
  107  * (re: BDP func. spec. "Slic Interface section, data byte latches").
  108  */
  109 #define CYCLE63(type)   ((type) & 0x78) /* bits 6:3 of the cycle type */
  110 #define CYCLE21(type)   ((type) & 0x06) /* bits 2:1 of the cycle type */
  111 #define CYCLE0 (type)   ((type) & 0x01) /* bit 0 of the cycle type */
  112 #define CYCLE1 (type)   ((type) & 0x02) /* bit 1 of the cycle type */
  113 #define CYCLE2 (type)   ((type) & 0x04) /* bit 2 of the cycle type */
  114 #define CYCLE3 (type)   ((type) & 0x08) /* bit 3 of the cycle type */
  115 #define CYCLE4 (type)   ((type) & 0x10) /* bit 4 of the cycle type */
  116 #define CYCLE5 (type)   ((type) & 0x20) /* bit 5 of the cycle type */
  117 #define CYCLE6 (type)   ((type) & 0x40) /* bit 6 of the cycle type */
  118 
  119 /*
  120  * Byte Mark definitions        (some but not all combinations)
  121  * (re: none specific, mentions in bdp spec.)
  122  */
  123 #define BM_MASK         0x0F    /* Usable bits */
  124 #define BM_FIRST_4              0x01    /* first 4 bytes valid */
  125 #define BM_SECOND_4             0x02    /* second 4 bytes valid */
  126 #define BM_THIRD_4              0x04    /* third 4 bytes valid */
  127 #define BM_FOURTH_4             0x08    /* fourth 4 bytes valid */
  128 #define BM_FIRST_8              0x03    /* first 8 bytes valid */
  129 #define BM_SECOND_8             0x0C    /* Second 8 bytes valid */
  130 #define BM_FIRST_16             0x0F    /* 16 bytes valid */
  131 
  132 /*
  133  * RdResp(0:3)
  134  * (re: BDP func. spec. "System Bus Interface section").
  135  */
  136 #define RR_MASK         0x0F    /* Usable bits */
  137 #define RR_NO_ERROR             0x0C    /* no error */
  138 #define RR_NON_FATAL            0x0A    /* non-fatal error */
  139 #define RR_FATAL                0x06    /* fatal error */
  140 #define RR_TIMEOUT              0x00    /* bus timeout occurred */
  141 #define RR_NOT_RR               0x0F    /* not a read response */
  142 
  143 /*
  144  * RdResp bit masks
  145  */
  146 #define RR_BITS31       0x0E            /* 3:1 Read Response bits */
  147 
  148 #endif  /* _SQT_BUSCYCLES_H_ */

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