The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/sqt/hwparam.h

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    1 /* 
    2  * Mach Operating System
    3  * Copyright (c) 1991 Carnegie Mellon University
    4  * Copyright (c) 1991 Sequent Computer Systems
    5  * All Rights Reserved.
    6  * 
    7  * Permission to use, copy, modify and distribute this software and its
    8  * documentation is hereby granted, provided that both the copyright
    9  * notice and this permission notice appear in all copies of the
   10  * software, derivative works or modified versions, and any portions
   11  * thereof, and that both notices appear in supporting documentation.
   12  * 
   13  * CARNEGIE MELLON AND SEQUENT COMPUTER SYSTEMS ALLOW FREE USE OF
   14  * THIS SOFTWARE IN ITS "AS IS" CONDITION.  CARNEGIE MELLON AND
   15  * SEQUENT COMPUTER SYSTEMS DISCLAIM ANY LIABILITY OF ANY KIND FOR
   16  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   17  * 
   18  * Carnegie Mellon requests users of this software to return to
   19  * 
   20  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   21  *  School of Computer Science
   22  *  Carnegie Mellon University
   23  *  Pittsburgh PA 15213-3890
   24  * 
   25  * any improvements or extensions that they make and grant Carnegie Mellon 
   26  * the rights to redistribute these changes.
   27  */
   28 
   29 /*
   30  * HISTORY
   31  * $Log:        hwparam.h,v $
   32  * Revision 2.3  91/07/31  18:00:51  dbg
   33  *      Changed copyright.
   34  *      [91/07/31            dbg]
   35  * 
   36  * Revision 2.2  91/05/08  12:56:01  dbg
   37  *      Added, from Sequent SYMMETRY sources.
   38  *      [91/04/26  14:51:55  dbg]
   39  * 
   40  */
   41 
   42 /*
   43  * $Header: hwparam.h,v 2.3 91/07/31 18:00:51 dbg Exp $
   44  *
   45  * hwparam.h
   46  *      Define physical addresses and other parameters of the hardware.
   47  */
   48 
   49 /* $Log:        hwparam.h,v $
   50  * Revision 2.3  91/07/31  18:00:51  dbg
   51  *      Changed copyright.
   52  *      [91/07/31            dbg]
   53  * 
   54  * Revision 2.2  91/05/08  12:56:01  dbg
   55  *      Added, from Sequent SYMMETRY sources.
   56  *      [91/04/26  14:51:55  dbg]
   57  * 
   58  * Revision 2.1.2.1  91/04/26  14:51:55  dbg
   59  *      Added, from Sequent SYMMETRY sources.
   60  * 
   61  * Revision 2.1.1.1  91/02/26  11:02:26  dbg
   62  *      Added, from Sequent SYMMETRY sources.
   63  *      [91/02/26            dbg]
   64  * 
   65  * Revision 1.2  89/07/20  18:05:01  kak
   66  * moved balance includes
   67  * 
   68  * Revision 1.1  89/07/05  13:15:32  kak
   69  * Initial revision
   70  * 
   71  */
   72 
   73 #ifndef _SQT_HWPARAM_H_
   74 #define _SQT_HWPARAM_H_
   75 
   76 /*
   77  * Physical addresses in processor board address space.
   78  */
   79 
   80 #ifdef  KXX
   81 
   82 #define PHYS_SLIC       0x1BF0000       /* phys loc in CPU addr space */
   83 #define PHYS_SLIC_INTR  0x1BF1000       /* slic's interrupt vector register */
   84 #define PHYS_CACHE0SET  0x1BF8000       /* cache 0 set data */
   85 #define PHYS_CACHE1SET  0x1BF9000       /* cache 1 set data */
   86 #define PHYS_STATICRAM  0x1BFA000       /* local static RAM */
   87 #define PHYS_CACHE0REV  0x1BFC000       /* cache set 0 (parity reversed) */
   88 #define PHYS_CACHE1REV  0x1BFD000       /* cache set 1 (parity reversed) */
   89 #define PHYS_RAMREV     0x1BFE000       /* local static RAM (parity reversed) */
   90 
   91 #define PHYS_MBAD       0x1C00000       /* MBAd base address (phys) */
   92 
   93 /*
   94  * Maximum processor addressable main-memory address is limited to 24Meg
   95  * on K20, due to naive mapping of SLIC in machine/startup.c
   96  * (alloclocalIO(), maplocalIO()).
   97  */
   98 
   99 #define MAX_PROC_ADDR_MEM (24*1024*1024)
  100 
  101 #else   Real HW
  102 
  103 #include <sqt/SGSproc.h>                /* SGS processor specific definitions */
  104 
  105 #endif  KXX
  106 
  107 /*
  108  * Define addressibility of Multi-bus interface.
  109  */
  110 
  111 #define VIRT_MBAD       PHYS_MBAD       /* MBAd base address (virt) */
  112 #define MBAD_ADDR_SPACE (1024*1024)     /* 1M address space */
  113 
  114 #define VA_MBAd(i)      (VIRT_MBAD + (i) * MBAD_ADDR_SPACE)
  115 #define PA_MBAd(i)      (PHYS_MBAD + (i) * MBAD_ADDR_SPACE)
  116 
  117 /*
  118  * For backwards compatibility -- MBAds started at fixed address.
  119  */
  120 
  121 #define OLD_VIRT_MBAD   0x0800000       /* MBAd base address (virt) */
  122 
  123 #endif  /* _SQT_HWPARAM_H_ */

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