Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/sqt/intctl.h
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1 /* 2 * Mach Operating System 3 * Copyright (c) 1991 Carnegie Mellon University 4 * Copyright (c) 1991 Sequent Computer Systems 5 * All Rights Reserved. 6 * 7 * Permission to use, copy, modify and distribute this software and its 8 * documentation is hereby granted, provided that both the copyright 9 * notice and this permission notice appear in all copies of the 10 * software, derivative works or modified versions, and any portions 11 * thereof, and that both notices appear in supporting documentation. 12 * 13 * CARNEGIE MELLON AND SEQUENT COMPUTER SYSTEMS ALLOW FREE USE OF 14 * THIS SOFTWARE IN ITS "AS IS" CONDITION. CARNEGIE MELLON AND 15 * SEQUENT COMPUTER SYSTEMS DISCLAIM ANY LIABILITY OF ANY KIND FOR 16 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 17 * 18 * Carnegie Mellon requests users of this software to return to 19 * 20 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 21 * School of Computer Science 22 * Carnegie Mellon University 23 * Pittsburgh PA 15213-3890 24 * 25 * any improvements or extensions that they make and grant Carnegie Mellon 26 * the rights to redistribute these changes. 27 */ 28 29 /* 30 * HISTORY 31 * $Log: intctl.h,v $ 32 * Revision 2.3 91/07/31 18:01:00 dbg 33 * Changed copyright. 34 * [91/07/31 dbg] 35 * 36 * Revision 2.2 91/05/08 12:56:21 dbg 37 * Converted for pure kernel and GCC. 38 * [91/04/26 14:52:18 dbg] 39 * 40 */ 41 42 /* 43 * $Header: intctl.h,v 2.3 91/07/31 18:01:00 dbg Exp $ 44 */ 45 46 /* 47 * Revision 1.1 89/07/05 13:15:33 kak 48 * Initial revision 49 * 50 * Revision 2.14 89/02/27 10:40:22 djg 51 * increased slic synchronisation timmings to 22Mhz (=12 cylces) 52 * 53 * Revision 2.13 88/11/10 08:25:31 djg 54 * bak242 55 * 56 */ 57 #ifndef _SQT_INTCTL_H_ 58 #define _SQT_INTCTL_H_ 59 60 #define TMPOS_GROUP 1 /* SLIC group used by processors */ 61 #define SLICBINS 8 /* 8 bins in current SLIC */ 62 #define MSGSPERBIN 256 /* Interrupt vectors per bin */ 63 64 /* 65 * SPL masks for SLIC. 66 */ 67 68 #define SPL0 0xFF /* all interrupts enabled */ 69 #define SPL1 0xFE /* bins 1-7 enabled, 0 disabled */ 70 #define SPL2 0xFC /* bins 2-7 enabled, 0-1 disabled */ 71 #define SPL3 0xF8 /* bins 3-7 enabled, 0-2 disabled */ 72 #define SPL_HOLE 0xF0 /* bins 4-7 enabled, 0-3 disabled */ 73 #define SPL4 0xE0 /* bins 5-7 enabled, 0-4 disabled */ 74 #define SPL5 0xC0 /* bins 6-7 enabled, 0-5 disabled */ 75 #define SPL6 0x80 /* bin 7 enabled, 0-6 disabled */ 76 #define SPL7 0x00 /* all interrupts disabled */ 77 78 /* 79 * Mnemonics for various implementation SPL's. 80 * SPLFD chosen to insure proper nesting of spl's in ioctl's. 81 */ 82 83 #define SPLNET SPL1 /* block network SW interrupts */ 84 #define SPLFD SPL1 /* file-descriptor manipulation */ 85 #define SPLTTY SPL4 /* block tty interrupts */ 86 #define SPLBUF SPL6 /* buffer-cache: all but clock(s) off */ 87 #define SPLSWP SPL6 /* swap-buf headers: similarly */ 88 #define SPLFS SPL6 /* inodes-list/file-sys: similarly */ 89 #define SPLIMP SPL6 /* network devices, etc */ 90 #define SPLMEM SPL6 /* memory list manipulation */ 91 #define SPLHI SPL7 /* block all interrupts */ 92 93 /* 94 * Bit positions of Software Interrupts 95 */ 96 97 #define NETINTR 0x01 98 #define SOFTCLOCK 0x10 99 #define RESCHED 0x40 100 #define PMAPUPDATE 0x80 101 102 /* 103 * NMI Interrupt messages 104 */ 105 106 #define PAUSESELF 0x01 107 108 #ifndef ASSEMBLER 109 /* 110 * Bin_header structure used for bin 1-7 interrupts. 111 * We allocate one for bin0 for convenience, although it isn't used. 112 * 113 * locore.s assumes this data-structure is 8-bytes big. If this 114 * changes, *MUST* change locore.s (dev_common handler). 115 */ 116 117 struct bin_header { 118 int bh_size; /* # entries */ 119 int (**bh_hdlrtab)(); /* real interrupt handlers */ 120 }; 121 122 extern struct bin_header int_bin_table[]; 123 extern int bin_alloc[]; 124 extern int bin_intr[]; 125 extern unsigned char ivecall(); 126 127 /* 128 * The following interfaces (ivecres, ivecpeek, and ivecinit) may 129 * be used by custom hardware configuration software to ease setting 130 * up interrupt handling. 131 * 132 * ivecres: reserve interrupt vector slots. 133 * ivecpeek: peek at the next interrupt vector to be allocated 134 * iveninit: assign an interrupt handler to a vector 135 */ 136 137 #define ivecres(bin, count) bin_intr[(bin)] += (count) 138 #define ivecpeek(bin) bin_alloc[(bin)] 139 #define ivecinit(bin, vector, handler) \ 140 int_bin_table[(bin)].bh_hdlrtab[(vector)] = (handler) 141 142 /* 143 * Typedef for spl mask. 144 */ 145 typedef int spl_t; 146 147 /* 148 * In-line spl interfaces -- mask some set of SLIC interrupts, return 149 * previous mask. 150 * 151 * Only low order byte of return value is meaningful; upper 3 bytes are 152 * not set and not used by splx(). 153 * 154 * All insure SLIC can't accept an interrupt once the "spl" is complete. 155 * Must do a read to synch with the write of new SLIC mask, then pad by 156 * at lease 8 cycles. This insures that a pending SLIC interrupt (or one 157 * accepted while the mask is being written) is taken before the spl() 158 * completes. Reading the slic local mask provides the synch and takes 159 * enough extra time so 2 nops are enough pad. (at 16Mhz) 160 */ 161 162 #define splnet spl1 163 #define splimp spl6 164 #define splhi spl7 /* block all interrupts */ 165 166 #endif ASSEMBLER 167 168 169 #ifndef __GNUC__ 170 #if !defined(GENASSYM) && !defined(lint) 171 172 asm spl0() 173 { 174 movb SLIC_MASK, %al /* old interrupt mask */ 175 movb $SPL0, SLIC_MASK /* write new interrupt mask */ 176 } 177 178 asm spl1() 179 { 180 movb SLIC_MASK, %al /* old interrupt mask */ 181 /PEEPOFF /* turn off peephole optimizer*/ 182 movb $SPL1, SLIC_MASK /* write new interrupt mask */ 183 movb SLIC_MASK, %dl /* dummy read to synch write */ 184 /***************SLICSYNC 2***************************************/ 185 nop /* pad out +3 cycles */ 186 nop /* pad out +3 cycles */ 187 #if MHz == 20 188 movl %eax,%eax /* pad out +2 cycles */ 189 movl %eax,%eax /* pad out +2 cycles */ 190 #endif 191 192 /PEEPON /* turn peephole opt back on */ 193 } 194 195 asm spl2() 196 { 197 movb SLIC_MASK, %al /* old interrupt mask */ 198 /PEEPOFF /* turn off peephole optimizer*/ 199 movb $SPL2, SLIC_MASK /* write new interrupt mask */ 200 movb SLIC_MASK, %dl /* dummy read to synch write */ 201 /***************SLICSYNC 2***************************************/ 202 nop /* pad out +3 cycles */ 203 nop /* pad out +3 cycles */ 204 #if MHz == 20 205 movl %eax,%eax /* pad out +2 cycles */ 206 movl %eax,%eax /* pad out +2 cycles */ 207 #endif 208 /PEEPON /* turn peephole opt back on */ 209 } 210 211 asm spl3() 212 { 213 movb SLIC_MASK, %al /* old interrupt mask */ 214 /PEEPOFF /* turn off peephole optimizer*/ 215 movb $SPL3, SLIC_MASK /* write new interrupt mask */ 216 movb SLIC_MASK, %dl /* dummy read to synch write */ 217 /***************SLICSYNC 2***************************************/ 218 nop /* pad out +3 cycles */ 219 nop /* pad out +3 cycles */ 220 #if MHz == 20 221 movl %eax,%eax /* pad out +2 cycles */ 222 movl %eax,%eax /* pad out +2 cycles */ 223 #endif 224 /PEEPON /* turn peephole opt back on */ 225 } 226 227 asm spl4() 228 { 229 movb SLIC_MASK, %al /* old interrupt mask */ 230 /PEEPOFF /* turn off peephole optimizer*/ 231 movb $SPL4, SLIC_MASK /* write new interrupt mask */ 232 movb SLIC_MASK, %dl /* dummy read to synch write */ 233 /***************SLICSYNC 2***************************************/ 234 nop /* pad out +3 cycles */ 235 nop /* pad out +3 cycles */ 236 #if MHz == 20 237 movl %eax,%eax /* pad out +2 cycles */ 238 movl %eax,%eax /* pad out +2 cycles */ 239 #endif 240 /PEEPON /* turn peephole opt back on */ 241 } 242 243 asm spl5() 244 { 245 movb SLIC_MASK, %al /* old interrupt mask */ 246 /PEEPOFF /* turn off peephole optimizer*/ 247 movb $SPL5, SLIC_MASK /* write new interrupt mask */ 248 movb SLIC_MASK, %dl /* dummy read to synch write */ 249 /***************SLICSYNC 2***************************************/ 250 nop /* pad out +3 cycles */ 251 nop /* pad out +3 cycles */ 252 #if MHz == 20 253 movl %eax,%eax /* pad out +2 cycles */ 254 movl %eax,%eax /* pad out +2 cycles */ 255 #endif 256 /PEEPON /* turn peephole opt back on */ 257 } 258 259 asm spl6() 260 { 261 movb SLIC_MASK, %al /* old interrupt mask */ 262 /PEEPOFF /* turn off peephole optimizer*/ 263 movb $SPL6, SLIC_MASK /* write new interrupt mask */ 264 movb SLIC_MASK, %dl /* dummy read to synch write */ 265 /***************SLICSYNC 2***************************************/ 266 nop /* pad out +3 cycles */ 267 nop /* pad out +3 cycles */ 268 #if MHz == 20 269 movl %eax,%eax /* pad out +2 cycles */ 270 movl %eax,%eax /* pad out +2 cycles */ 271 #endif 272 /PEEPON /* turn peephole opt back on */ 273 } 274 275 asm spl7() 276 { 277 movb SLIC_MASK, %al /* old interrupt mask */ 278 /PEEPOFF /* turn off peephole optimizer*/ 279 movb $SPL7, SLIC_MASK /* write new interrupt mask */ 280 movb SLIC_MASK, %dl /* dummy read to synch write */ 281 /***************SLICSYNC 2***************************************/ 282 nop /* pad out +3 cycles */ 283 nop /* pad out +3 cycles */ 284 #if MHz == 20 285 movl %eax,%eax /* pad out +2 cycles */ 286 movl %eax,%eax /* pad out +2 cycles */ 287 #endif 288 /PEEPON /* turn peephole opt back on */ 289 } 290 291 /* 292 * splx() lowers interrupt mask to a previous value. No write-synch or padding 293 * necessary since mask is allowing more interrupts, not masking more. 294 * DEBUG uses out-of-line version that tests mask is lowering. 295 */ 296 297 #ifndef DEBUG 298 asm splx(oldmask) 299 { 300 %reg oldmask; 301 movl oldmask, %eax 302 movb %al, SLIC_MASK 303 %con oldmask; 304 movb oldmask, SLIC_MASK 305 %mem oldmask; 306 movb oldmask, %al 307 movb %al, SLIC_MASK 308 } 309 #endif DEBUG 310 311 #endif !GENASSYM && !lint 312 #endif __GNUC__ 313 314 #endif _SQT_INTCTL_H_
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