Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/sqt/intctl.h
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1 /* 2 * Mach Operating System 3 * Copyright (c) 1993,1991 Carnegie Mellon University 4 * Copyright (c) 1991 Sequent Computer Systems 5 * All Rights Reserved. 6 * 7 * Permission to use, copy, modify and distribute this software and its 8 * documentation is hereby granted, provided that both the copyright 9 * notice and this permission notice appear in all copies of the 10 * software, derivative works or modified versions, and any portions 11 * thereof, and that both notices appear in supporting documentation. 12 * 13 * CARNEGIE MELLON AND SEQUENT COMPUTER SYSTEMS ALLOW FREE USE OF 14 * THIS SOFTWARE IN ITS "AS IS" CONDITION. CARNEGIE MELLON AND 15 * SEQUENT COMPUTER SYSTEMS DISCLAIM ANY LIABILITY OF ANY KIND FOR 16 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 17 * 18 * Carnegie Mellon requests users of this software to return to 19 * 20 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 21 * School of Computer Science 22 * Carnegie Mellon University 23 * Pittsburgh PA 15213-3890 24 * 25 * any improvements or extensions that they make and grant Carnegie Mellon 26 * the rights to redistribute these changes. 27 */ 28 29 /* 30 * HISTORY 31 * $Log: intctl.h,v $ 32 * Revision 2.4 93/11/17 18:46:12 dbg 33 * Include machine/machspl.h for declarations of spl_t and spl 34 * routines. 35 * [93/05/25 dbg] 36 * 37 * Revision 2.3 91/07/31 18:01:00 dbg 38 * Changed copyright. 39 * [91/07/31 dbg] 40 * 41 * Revision 2.2 91/05/08 12:56:21 dbg 42 * Converted for pure kernel and GCC. 43 * [91/04/26 14:52:18 dbg] 44 * 45 */ 46 47 /* 48 * $Header: intctl.h,v 2.4 93/11/17 18:46:12 dbg Exp $ 49 */ 50 51 /* 52 * Revision 1.1 89/07/05 13:15:33 kak 53 * Initial revision 54 * 55 * Revision 2.14 89/02/27 10:40:22 djg 56 * increased slic synchronisation timmings to 22Mhz (=12 cylces) 57 * 58 * Revision 2.13 88/11/10 08:25:31 djg 59 * bak242 60 * 61 */ 62 #ifndef _SQT_INTCTL_H_ 63 #define _SQT_INTCTL_H_ 64 65 66 #define TMPOS_GROUP 1 /* SLIC group used by processors */ 67 #define SLICBINS 8 /* 8 bins in current SLIC */ 68 #define MSGSPERBIN 256 /* Interrupt vectors per bin */ 69 70 /* 71 * SPL masks for SLIC. 72 */ 73 74 #define SPL0 0xFF /* all interrupts enabled */ 75 #define SPL1 0xFE /* bins 1-7 enabled, 0 disabled */ 76 #define SPL2 0xFC /* bins 2-7 enabled, 0-1 disabled */ 77 #define SPL3 0xF8 /* bins 3-7 enabled, 0-2 disabled */ 78 #define SPL_HOLE 0xF0 /* bins 4-7 enabled, 0-3 disabled */ 79 #define SPL4 0xE0 /* bins 5-7 enabled, 0-4 disabled */ 80 #define SPL5 0xC0 /* bins 6-7 enabled, 0-5 disabled */ 81 #define SPL6 0x80 /* bin 7 enabled, 0-6 disabled */ 82 #define SPL7 0x00 /* all interrupts disabled */ 83 84 /* 85 * Mnemonics for various implementation SPL's. 86 * SPLFD chosen to insure proper nesting of spl's in ioctl's. 87 */ 88 89 #define SPLNET SPL1 /* block network SW interrupts */ 90 #define SPLFD SPL1 /* file-descriptor manipulation */ 91 #define SPLTTY SPL4 /* block tty interrupts */ 92 #define SPLBUF SPL6 /* buffer-cache: all but clock(s) off */ 93 #define SPLSWP SPL6 /* swap-buf headers: similarly */ 94 #define SPLFS SPL6 /* inodes-list/file-sys: similarly */ 95 #define SPLIMP SPL6 /* network devices, etc */ 96 #define SPLMEM SPL6 /* memory list manipulation */ 97 #define SPLHI SPL7 /* block all interrupts */ 98 99 /* 100 * Bit positions of Software Interrupts 101 */ 102 103 #define NETINTR 0x01 104 #define SOFTCLOCK 0x10 105 #define RESCHED 0x40 106 #define PMAPUPDATE 0x80 107 108 /* 109 * NMI Interrupt messages 110 */ 111 112 #define PAUSESELF 0x01 113 114 #ifndef ASSEMBLER 115 /* 116 * Bin_header structure used for bin 1-7 interrupts. 117 * We allocate one for bin0 for convenience, although it isn't used. 118 * 119 * locore.s assumes this data-structure is 8-bytes big. If this 120 * changes, *MUST* change locore.s (dev_common handler). 121 */ 122 123 struct bin_header { 124 int bh_size; /* # entries */ 125 int (**bh_hdlrtab)(); /* real interrupt handlers */ 126 }; 127 128 extern struct bin_header int_bin_table[]; 129 extern int bin_alloc[]; 130 extern int bin_intr[]; 131 extern unsigned char ivecall(); 132 133 /* 134 * The following interfaces (ivecres, ivecpeek, and ivecinit) may 135 * be used by custom hardware configuration software to ease setting 136 * up interrupt handling. 137 * 138 * ivecres: reserve interrupt vector slots. 139 * ivecpeek: peek at the next interrupt vector to be allocated 140 * iveninit: assign an interrupt handler to a vector 141 */ 142 143 #define ivecres(bin, count) bin_intr[(bin)] += (count) 144 #define ivecpeek(bin) bin_alloc[(bin)] 145 #define ivecinit(bin, vector, handler) \ 146 int_bin_table[(bin)].bh_hdlrtab[(vector)] = (handler) 147 148 /* 149 * In-line spl interfaces -- mask some set of SLIC interrupts, return 150 * previous mask. 151 * 152 * Only low order byte of return value is meaningful; upper 3 bytes are 153 * not set and not used by splx(). 154 * 155 * All insure SLIC can't accept an interrupt once the "spl" is complete. 156 * Must do a read to synch with the write of new SLIC mask, then pad by 157 * at lease 8 cycles. This insures that a pending SLIC interrupt (or one 158 * accepted while the mask is being written) is taken before the spl() 159 * completes. Reading the slic local mask provides the synch and takes 160 * enough extra time so 2 nops are enough pad. (at 16Mhz) 161 */ 162 163 #include <machine/machspl.h> /* SPL declarations */ 164 165 #define splnet() spl1() 166 167 #undef splimp 168 extern spl_t splimp(void); 169 170 #define splhi() splhigh() /* block all interrupts */ 171 172 #endif /* ASSEMBLER */ 173 174 175 #ifndef __GNUC__ 176 #if !defined(GENASSYM) && !defined(lint) 177 178 asm spl0() 179 { 180 movb SLIC_MASK, %al /* old interrupt mask */ 181 movb $SPL0, SLIC_MASK /* write new interrupt mask */ 182 } 183 184 asm spl1() 185 { 186 movb SLIC_MASK, %al /* old interrupt mask */ 187 /PEEPOFF /* turn off peephole optimizer*/ 188 movb $SPL1, SLIC_MASK /* write new interrupt mask */ 189 movb SLIC_MASK, %dl /* dummy read to synch write */ 190 /***************SLICSYNC 2***************************************/ 191 nop /* pad out +3 cycles */ 192 nop /* pad out +3 cycles */ 193 #if MHz == 20 194 movl %eax,%eax /* pad out +2 cycles */ 195 movl %eax,%eax /* pad out +2 cycles */ 196 #endif 197 198 /PEEPON /* turn peephole opt back on */ 199 } 200 201 asm spl2() 202 { 203 movb SLIC_MASK, %al /* old interrupt mask */ 204 /PEEPOFF /* turn off peephole optimizer*/ 205 movb $SPL2, SLIC_MASK /* write new interrupt mask */ 206 movb SLIC_MASK, %dl /* dummy read to synch write */ 207 /***************SLICSYNC 2***************************************/ 208 nop /* pad out +3 cycles */ 209 nop /* pad out +3 cycles */ 210 #if MHz == 20 211 movl %eax,%eax /* pad out +2 cycles */ 212 movl %eax,%eax /* pad out +2 cycles */ 213 #endif 214 /PEEPON /* turn peephole opt back on */ 215 } 216 217 asm spl3() 218 { 219 movb SLIC_MASK, %al /* old interrupt mask */ 220 /PEEPOFF /* turn off peephole optimizer*/ 221 movb $SPL3, SLIC_MASK /* write new interrupt mask */ 222 movb SLIC_MASK, %dl /* dummy read to synch write */ 223 /***************SLICSYNC 2***************************************/ 224 nop /* pad out +3 cycles */ 225 nop /* pad out +3 cycles */ 226 #if MHz == 20 227 movl %eax,%eax /* pad out +2 cycles */ 228 movl %eax,%eax /* pad out +2 cycles */ 229 #endif 230 /PEEPON /* turn peephole opt back on */ 231 } 232 233 asm spl4() 234 { 235 movb SLIC_MASK, %al /* old interrupt mask */ 236 /PEEPOFF /* turn off peephole optimizer*/ 237 movb $SPL4, SLIC_MASK /* write new interrupt mask */ 238 movb SLIC_MASK, %dl /* dummy read to synch write */ 239 /***************SLICSYNC 2***************************************/ 240 nop /* pad out +3 cycles */ 241 nop /* pad out +3 cycles */ 242 #if MHz == 20 243 movl %eax,%eax /* pad out +2 cycles */ 244 movl %eax,%eax /* pad out +2 cycles */ 245 #endif 246 /PEEPON /* turn peephole opt back on */ 247 } 248 249 asm spl5() 250 { 251 movb SLIC_MASK, %al /* old interrupt mask */ 252 /PEEPOFF /* turn off peephole optimizer*/ 253 movb $SPL5, SLIC_MASK /* write new interrupt mask */ 254 movb SLIC_MASK, %dl /* dummy read to synch write */ 255 /***************SLICSYNC 2***************************************/ 256 nop /* pad out +3 cycles */ 257 nop /* pad out +3 cycles */ 258 #if MHz == 20 259 movl %eax,%eax /* pad out +2 cycles */ 260 movl %eax,%eax /* pad out +2 cycles */ 261 #endif 262 /PEEPON /* turn peephole opt back on */ 263 } 264 265 asm spl6() 266 { 267 movb SLIC_MASK, %al /* old interrupt mask */ 268 /PEEPOFF /* turn off peephole optimizer*/ 269 movb $SPL6, SLIC_MASK /* write new interrupt mask */ 270 movb SLIC_MASK, %dl /* dummy read to synch write */ 271 /***************SLICSYNC 2***************************************/ 272 nop /* pad out +3 cycles */ 273 nop /* pad out +3 cycles */ 274 #if MHz == 20 275 movl %eax,%eax /* pad out +2 cycles */ 276 movl %eax,%eax /* pad out +2 cycles */ 277 #endif 278 /PEEPON /* turn peephole opt back on */ 279 } 280 281 asm spl7() 282 { 283 movb SLIC_MASK, %al /* old interrupt mask */ 284 /PEEPOFF /* turn off peephole optimizer*/ 285 movb $SPL7, SLIC_MASK /* write new interrupt mask */ 286 movb SLIC_MASK, %dl /* dummy read to synch write */ 287 /***************SLICSYNC 2***************************************/ 288 nop /* pad out +3 cycles */ 289 nop /* pad out +3 cycles */ 290 #if MHz == 20 291 movl %eax,%eax /* pad out +2 cycles */ 292 movl %eax,%eax /* pad out +2 cycles */ 293 #endif 294 /PEEPON /* turn peephole opt back on */ 295 } 296 297 /* 298 * splx() lowers interrupt mask to a previous value. No write-synch or padding 299 * necessary since mask is allowing more interrupts, not masking more. 300 * DEBUG uses out-of-line version that tests mask is lowering. 301 */ 302 303 #ifndef DEBUG 304 asm splx(oldmask) 305 { 306 %reg oldmask; 307 movl oldmask, %eax 308 movb %al, SLIC_MASK 309 %con oldmask; 310 movb oldmask, SLIC_MASK 311 %mem oldmask; 312 movb oldmask, %al 313 movb %al, SLIC_MASK 314 } 315 #endif /* DEBUG */ 316 317 #endif /* !GENASSYM && !lint */ 318 #endif /* __GNUC__ */ 319 320 #endif /* _SQT_INTCTL_H_ */
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