FreeBSD/Linux Kernel Cross Reference
sys/sqt/trap.h
1 /*
2 * Mach Operating System
3 * Copyright (c) 1991 Carnegie Mellon University
4 * Copyright (c) 1991 Sequent Computer Systems
5 * All Rights Reserved.
6 *
7 * Permission to use, copy, modify and distribute this software and its
8 * documentation is hereby granted, provided that both the copyright
9 * notice and this permission notice appear in all copies of the
10 * software, derivative works or modified versions, and any portions
11 * thereof, and that both notices appear in supporting documentation.
12 *
13 * CARNEGIE MELLON AND SEQUENT COMPUTER SYSTEMS ALLOW FREE USE OF
14 * THIS SOFTWARE IN ITS "AS IS" CONDITION. CARNEGIE MELLON AND
15 * SEQUENT COMPUTER SYSTEMS DISCLAIM ANY LIABILITY OF ANY KIND FOR
16 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
17 *
18 * Carnegie Mellon requests users of this software to return to
19 *
20 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
21 * School of Computer Science
22 * Carnegie Mellon University
23 * Pittsburgh PA 15213-3890
24 *
25 * any improvements or extensions that they make and grant Carnegie Mellon
26 * the rights to redistribute these changes.
27 */
28
29 /*
30 * HISTORY
31 * $Log: trap.h,v $
32 * Revision 2.3 91/07/31 18:04:46 dbg
33 * Changed copyright.
34 * [91/07/31 dbg]
35 *
36 * Revision 2.2 91/05/08 13:01:23 dbg
37 * Added, from Sequent SYMMETRY sources.
38 * [91/02/26 dbg]
39 *
40 */
41
42 /*
43 * $Header: trap.h,v 2.3 91/07/31 18:04:46 dbg Exp $
44 *
45 * trap.h
46 * Trap type values.
47 *
48 * Values of types match Intel 80386 vector numbers.
49 */
50
51 /*
52 * Revision 1.1 89/07/05 13:15:50 kak
53 * Initial revision
54 *
55 */
56
57 #ifndef _SQT_TRAP_H_
58 #define _SQT_TRAP_H_
59
60 /*
61 * Interrupts, traps, and exceptions use the Interrupt Descriptor Table
62 * (IDT), indexed for the particular interrupt, trap, or exception.
63 *
64 * There is a copy of this table per processor to avoid LOCK# contention
65 * during IDT access (see plocal.h).
66 */
67
68 #define T_DIVERR 0 /* integer zero-divide, divide error */
69 #define T_DBG 1 /* debug exceptions */
70 #define T_NMI 2 /* non-maskable interrupt */
71 #define T_INT3 3 /* single-byte interrupt (breakpoint) */
72 #define T_INTO 4 /* interrupt on overflow */
73 #define T_CHECK 5 /* array bounds check */
74 #define T_UND 6 /* undefined/illegal op-code */
75 #define T_DNA 7 /* device not available (FPU) */
76 #define T_SYSERR 8 /* system error (serious problem) */
77 #define T_RES 9 /* reserved vector (9,15) */
78 #define T_BADTSS 10 /* invalid task-state segment */
79 #define T_NOTPRES 11 /* segment/gate not present */
80 #define T_STKFLT 12 /* stack fault */
81 #define T_GPFLT 13 /* general protection fault */
82 #define T_PGFLT 14 /* page fault */
83 #define T_COPERR 16 /* co-processor error (FPU) */
84 /*
85 * Intel reserves thru 31.
86 */
87 #define T_SWTCH 17 /* redispatch (SW only, no IDT access)*/
88 #define T_USER 0x20 /* value to OR if USER trap */
89
90 /*
91 * SLIC interrupt vectors.
92 */
93
94 #define T_BIN0 32 /* Bin 0 interrupt (SW interrupt) */
95 #define T_BIN1 33 /* Bin 1 interrupt (SW interrupt) */
96 #define T_BIN2 34 /* Bin 2 interrupt (SW interrupt) */
97 #define T_BIN3 35 /* Bin 3 interrupt (SW interrupt) */
98 #define T_BIN4 36 /* Bin 4 interrupt (SW interrupt) */
99 #define T_BIN5 37 /* Bin 5 interrupt (SW interrupt) */
100 #define T_BIN6 38 /* Bin 6 interrupt (SW interrupt) */
101 #define T_BIN7 39 /* Bin 7 interrupt (SW interrupt) */
102
103 /*
104 * System calls use "INT n" instructions to have same stack entry as
105 * traps and exceptions. There is one syscall entry per number of
106 * arguments, to streamline argument copying. Call gates don't work
107 * due to different stack frame and the detail semantics (don't work
108 * well thru syscall interfaces (libc)).
109 */
110
111 #define T_SVC0 40 /* 0-arg system call */
112 #define T_SVC1 41 /* 1-arg system call */
113 #define T_SVC2 42 /* 2-arg system call */
114 #define T_SVC3 43 /* 3-arg system call */
115 #define T_SVC4 44 /* 4-arg system call */
116 #define T_SVC5 45 /* 5-arg system call */
117 #define T_SVC6 46 /* 6-arg system call */
118
119 #ifdef FPA
120 /*
121 * Weitek FPA exception vectors.
122 */
123
124 #define T_FPA 64 /* FPA exception interrupt */
125 #endif FPA
126
127 #define T_MACH 128 /* Mach system call entry */
128
129 /*
130 * IDT gets fully filled out (256 entries) -- see IDT_SIZE in machime/gdt.h.
131 * Higher number entries are made illegal by vectoring all illegal entries
132 * to "t_res" -- generates T_RES trap.
133 */
134
135 #endif /* _SQT_TRAP_H_ */
Cache object: c899ed81bcab264f3b134aa684e23aec
|