1 /*-
2 * Copyright (c) 2006 Kip Macy <kmacy@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #include <sys/cdefs.h>
30
31 #include <machine/asm.h>
32 #include <machine/asi.h>
33 #include <machine/asmacros.h>
34 #include <machine/hypervisorvar.h>
35 #include <machine/pstate.h>
36
37 #include "assym.s"
38 /*
39 * Section 9 API Versioning
40 *
41 */
42
43 /*
44 * request and check for a version of the hypervisor apis
45 * which may be compatible
46 *
47 * arg0 api_group (%o0)
48 * arg1 major_number (%o1)
49 * arg2 req_minor_number (%o2)
50 *
51 * ret0 status (%o0)
52 * ret1 act_minor_number (%o1)
53 *
54 */
55 ENTRY(api_set_version)
56 mov API_SET_VERSION, %o5
57 ta CORE_TRAP
58 retl
59 stx %o1, [%o3]
60 END(api_set_version)
61
62 /*
63 * retrieve the major and minor number of the most recently
64 * successfully negotiated API
65 *
66 * arg0 api_group (%o0)
67 *
68 * ret0 status (%o0)
69 * ret1 major_number (%o1)
70 * ret2 major_number (%o2)
71 *
72 */
73 ENTRY(api_get_version)
74 mov %o2, %o4
75 mov %o1, %o3
76 mov API_GET_VERSION, %o5
77 ta CORE_TRAP
78 retl
79 stx %o1, [%o4]
80
81 END(api_get_version)
82
83 /*
84 * Section 10 Domain Services
85 *
86 */
87
88 /*
89 * stop all CPUs in the virtual machine domain and place them
90 * in the stopped state
91 *
92 * arg0 exit_code (%o0)
93 *
94 */
95 ENTRY(hv_mach_exit)
96 mov MACH_EXIT, %o5
97 ta FAST_TRAP
98 retl
99 nop
100 END(hv_mach_exit)
101
102 /*
103 * copy the most current machine description into buffer
104 * upon success or EINVAL the service returns the actual
105 * size of the machine description
106 *
107 * arg0 buffer (%o0)
108 * arg1 length (%o1)
109 *
110 * ret0 status (%o0)
111 * ret1 length (%o1)
112 *
113 */
114 ENTRY(hv_mach_desc)
115 mov %o1, %o2
116 ldx [%o1], %o1
117 mov MACH_DESC, %o5
118 ta FAST_TRAP
119 retl
120 stx %o1, [%o2]
121 END(hv_mach_desc)
122
123 /*
124 * execute a software initiated reset of a virtual machine domain
125 *
126 */
127 ENTRY(hv_mach_sir)
128 mov MACH_SIR, %o5
129 ta FAST_TRAP
130 retl
131 nop
132 END(hv_mach_sir)
133
134 /*
135 * report the guests soft state to the hypervisor
136 *
137 * arg0 soft_state (%o0)
138 * arg1 soft_state_desc_ptr (%o1)
139 *
140 * ret0 status (%o0)
141 *
142 */
143 ENTRY(hv_mach_set_soft_state)
144 mov MACH_SET_SOFT_STATE, %o5
145 ta FAST_TRAP
146 retl
147 nop
148 END(hv_mach_set_soft_state)
149
150 /*
151 * retrieve the current value of the guest's software state
152 *
153 * arg0 soft_desc_ptr (%o0)
154 *
155 * ret0 status (%o0)
156 * arg1 soft_state (%o1)
157 *
158 */
159 ENTRY(hv_mach_get_soft_state)
160 mov %o1, %o2
161 mov MACH_SET_SOFT_STATE, %o5
162 ta FAST_TRAP
163 retl
164 stx %o1, [%o2]
165 END(hv_mach_get_soft_state)
166
167 /*
168 * set a watchdog timer, 0 disables, upon success
169 * time_remaining contains the time previously remaining
170 *
171 * arg0 timeout (%o0)
172 *
173 * ret0 status (%o0)
174 * ret1 time_remaining (%o1)
175 *
176 */
177 ENTRY(hv_mach_watchdog)
178 mov %o1, %o2
179 mov MACH_WATCHDOG, %o5
180 ta FAST_TRAP
181 brnz,pn %o0, 1f
182 nop
183 stx %o1, [%o2]
184 1: retl
185 nop
186 END(hv_mach_watchdog)
187
188 /*
189 * Section 11 CPU Services
190 *
191 */
192
193 /*
194 * start CPU with id cpuid with pc in %pc and real trap base address
195 * of rtba
196 *
197 * arg0 cpuid (%o0)
198 * arg1 pc (%o1)
199 * arg2 rtba (%o2)
200 * arg3 target_arg0 (%o3)
201 *
202 * ret0 status (%o0)
203 *
204 */
205 ENTRY(hv_cpu_start)
206 mov CPU_START, %o5
207 ta FAST_TRAP
208 retl
209 nop
210 END(hv_cpu_start)
211
212 /*
213 * stop CPU with id cpuid
214 *
215 * arg0 cpuid (%o0)
216 *
217 * ret0 status (%o0)
218 *
219 */
220 ENTRY(hv_cpu_stop)
221 mov CPU_STOP, %o5
222 ta FAST_TRAP
223 retl
224 nop
225 END(hv_cpu_stop)
226
227 /*
228 * set the real trap base address of the local cpu to rtba
229 * upon success the previous_rtba contains the address of the
230 * old rtba
231 *
232 * arg0 rtba (%o0)
233 *
234 * ret0 status (%o0)
235 * ret1 previous_rtba(%o1)
236 *
237 */
238 ENTRY(hv_cpu_set_rtba)
239 mov %o1, %o2
240 mov CPU_SET_RTBA, %o5
241 ta FAST_TRAP
242 retl
243 stx %o1, [%o2]
244
245 END(hv_cpu_set_rtba)
246
247 /*
248 * return the current real trap base address
249 *
250 * ret0 status (%o0)
251 * ret1 rtba (%o1)
252 *
253 */
254 ENTRY(hv_cpu_get_rtba)
255 mov CPU_GET_RTBA, %o5
256 ta FAST_TRAP
257 retl
258 nop
259 END(hv_cpu_get_rtba)
260
261 /*
262 * suspend execution on current cpu
263 *
264 * ret0 status (%o0)
265 *
266 */
267 ENTRY(hv_cpu_yield)
268 mov CPU_YIELD, %o5
269 ta FAST_TRAP
270 retl
271 nop
272 END(hv_cpu_yield)
273
274 /*
275 * configure queue of size nentries to be placed at base raddr
276 *
277 * arg0 queue (%o0)
278 * arg1 base raddr (%o1)
279 * arg2 nentries (%o2)
280 *
281 * ret0 status (%o0)
282 *
283 */
284 ENTRY(hv_cpu_qconf)
285 mov CPU_QCONF, %o5
286 ta FAST_TRAP
287 retl
288 nop
289 END(hv_cpu_qconf)
290
291 /*
292 * return configuration of queue queue
293 *
294 * arg0 queue (%o0)
295 *
296 * ret0 status (%o0)
297 * ret1 base raddr (%o1)
298 * ret2 nentries (%o2)
299 *
300 */
301 ENTRY(hv_cpu_qinfo)
302 END(hv_cpu_qinfo)
303
304 /*
305 * send cpu mondo interrupt to cpulist
306 *
307 * arg0 ncpus (%o0)
308 * arg1 cpu list ra (%o1)
309 * arg2 mondo data ra(%o2)
310 *
311 * ret0 status (%o0)
312 *
313 */
314 ENTRY(hv_cpu_mondo_send)
315 ldx [PCPU(MONDO_DATA_RA)], %o2
316 mov CPU_MONDO_SEND, %o5
317 ta FAST_TRAP
318 retl
319 membar #Sync
320 END(hv_cpu_mondo_send)
321
322 /*
323 * return the hypervisor id for the current cpu
324 *
325 * ret0 status (%o0)
326 * ret1 cpuid (%o1)
327 *
328 */
329 ENTRY(hv_cpu_myid)
330 mov %o0, %o2
331 mov CPU_MYID, %o5
332 ta FAST_TRAP
333 stx %o1, [%o2]
334 retl
335 nop
336 END(hv_cpu_myid)
337
338 /*
339 * retrieve the current state of cpu cpuid
340 *
341 * arg0 cpuid (%o0)
342 *
343 * ret0 status (%o0)
344 * ret1 state (%o1)
345 *
346 */
347 ENTRY(hv_cpu_state)
348 mov %o1, %o2
349 mov CPU_STATE, %o5
350 ta FAST_TRAP
351 stx %o1, [%o2]
352 retl
353 nop
354 END(hv_cpu_state)
355
356 /*
357 * Section 12 MMU Services
358 *
359 */
360
361 /*
362 * set the tsb(s) for the current cpu for context 0
363 *
364 * arg0 ntsb (%o0)
365 * arg1 tsbdptr (%o1)
366 *
367 * ret0 status (%o0)
368 *
369 */
370 ENTRY(hv_mmu_tsb_ctx0)
371 mov MMU_TSB_CTX0, %o5
372 ta FAST_TRAP
373 retl
374 nop
375 END(hv_mmu_tsb_ctx0)
376
377 /*
378 * set the tsb(s) for the current cpu for non-zero contexts
379 *
380 * arg0 ntsb (%o0)
381 * arg1 tsbptr (%o1)
382 *
383 * ret0 status (%o0)
384 *
385 */
386 ENTRY(hv_mmu_tsb_ctxnon0)
387 mov MMU_TSB_CTXNON0, %o5
388 ta FAST_TRAP
389 retl
390 nop
391 END(hv_mmu_tsb_ctxnon0)
392
393 /*
394 * demap any page mapping of virtual address vaddr in context ctx
395 *
396 * arg0 reserved (%o0)
397 * arg1 reserved (%o1)
398 * arg2 vaddr (%o2)
399 * arg3 ctx (%o3)
400 * arg4 flags (%o4)
401 *
402 * ret0 status (%o0)
403 *
404 */
405 ENTRY(hv_mmu_demap_page)
406 mov MMU_DEMAP_PAGE, %o5
407 ta FAST_TRAP
408 retl
409 nop
410 END(hv_mmu_demap_page)
411
412 /*
413 * demap all non-permanent virtual address mappings in context ctx
414 *
415 * arg0 reserved (%o0)
416 * arg1 reserved (%o1)
417 * arg2 ctx (%o2)
418 * arg3 flags (%o3)
419 *
420 * ret0 status (%o0)
421 *
422 */
423 ENTRY(hv_mmu_demap_ctx)
424 mov MMU_DEMAP_CTX, %o5
425 ta FAST_TRAP
426 retl
427 nop
428 END(hv_mmu_demap_ctx)
429
430 /*
431 * demap all non-permanent virtual address mappings for the current
432 * virtual cpu
433 *
434 * arg0 reserved (%o0)
435 * arg1 reserved (%o1)
436 * arg2 flags (%o2)
437 *
438 * ret0 status (%o0)
439 *
440 */
441 ENTRY(hv_mmu_demap_all)
442 mov MMU_DEMAP_ALL, %o5
443 ta FAST_TRAP
444 retl
445 nop
446 END(hv_mmu_demap_all)
447
448 /*
449 * create a non-permanent mapping for the calling virtual cpu
450 *
451 * arg0 vaddr (%o0)
452 * arg1 context (%o1)
453 * arg2 TTE (%o2)
454 * arg3 flags (%o3)
455 *
456 * ret0 status (%o0)
457 *
458 */
459 ENTRY(hv_mmu_map_addr)
460 mov MMU_MAP_ADDR, %o5
461 ta FAST_TRAP
462 retl
463 nop
464 END(hv_mmu_map_addr)
465
466 /*
467 * create a permanent mapping for the calling virtual cpu
468 *
469 * arg0 vaddr (%o0)
470 * arg1 reserved (%o1)
471 * arg2 TTE (%o2)
472 * arg3 flags (%o3)
473 *
474 * ret0 status (%o0)
475 *
476 */
477 ENTRY(hv_mmu_map_perm_addr)
478 mov MMU_MAP_PERM_ADDR, %o5
479 ta FAST_TRAP
480 retl
481 nop
482 END(hv_mmu_map_perm_addr)
483
484 /*
485 * demap virtual address vaddr in context ctx on current virtual cpu
486 *
487 * arg0 vaddr (%o0)
488 * arg1 ctx (%o1)
489 * arg2 flags (%o2)
490 *
491 * ret0 status (%o0)
492 *
493 */
494 ENTRY(hv_mmu_unmap_addr)
495 mov MMU_UNMAP_ADDR, %o5
496 ta FAST_TRAP
497 retl
498 nop
499 END(hv_mmu_unmap_addr)
500
501 /*
502 * demap any permanent mapping at virtual address vaddr on current virtual cpu
503 *
504 * arg0 vaddr (%o0)
505 * arg1 reserved (%o1)
506 * arg2 flags (%o2)
507 *
508 * ret0 status (%o0)
509 *
510 */
511 ENTRY(hv_mmu_unmap_perm_addr)
512 mov %o1, %o2
513 clr %o1
514 mov MMU_UNMAP_PERM_ADDR, %o5
515 ta FAST_TRAP
516 retl
517 nop
518 END(hv_mmu_unmap_perm_addr)
519
520 /*
521 * configure the MMU fault status area for the current virtual cpu
522 *
523 * arg0 raddr (%o0)
524 *
525 * ret0 status (%o0)
526 * ret1 prev_raddr (%o1)
527 *
528 */
529 ENTRY(hv_mmu_fault_area_conf)
530 mov %o1, %o2
531 mov MMU_FAULT_AREA_CONF, %o5
532 ta FAST_TRAP
533 retl
534 stx %o1, [%o2]
535 END(hv_mmu_fault_area_conf)
536
537 /*
538 * enable or disable virtual address translation for the current virtual cpu
539 *
540 * arg0 enable_flag (%o0)
541 * arg1 return_target (%o1)
542 *
543 * ret0 status (%o0)
544 *
545 */
546 ENTRY(hv_mmu_enable)
547 mov MMU_ENABLE, %o5
548 ta FAST_TRAP
549 retl
550 nop
551 END(hv_mmu_enable)
552
553 /*
554 * return the TSB configuration as previously defined by mmu_tsb_ctx0
555 *
556 * arg0 maxtsbs (%o0)
557 * arg1 buffer_ra (%o1)
558 *
559 * ret0 status (%o0)
560 * ret1 ntsbs (%o1)
561 *
562 */
563 ENTRY(hv_mmu_tsb_ctx0_info)
564 mov %o1, %o2
565 mov MMU_TSB_CTX0_INFO, %o5
566 ta FAST_TRAP
567 retl
568 stx %o1, [%o2]
569 END(hv_mmu_tsb_ctx0_info)
570
571 /*
572 * return the TSB configuration as previously defined by mmu_tsb_ctxnon0
573 *
574 * arg0 maxtsbs (%o0)
575 * arg1 buffer_ra (%o1)
576 *
577 * ret0 status (%o0)
578 * ret1 ntsbs (%o1)
579 *
580 */
581 ENTRY(hv_mmu_tsb_ctxnon0_info)
582 mov %o1, %o2
583 mov MMU_TSB_CTXNON0_INFO, %o5
584 ta FAST_TRAP
585 retl
586 stx %o1, [%o2]
587 END(hv_mmu_tsb_ctxnon0_info)
588
589 /*
590 * return the MMU fault status area defined for the current virtual cpu
591 *
592 * ret0 status (%o0)
593 * ret1 mmfsara (%o1)
594 *
595 */
596 ENTRY(hv_mmu_fault_area_info)
597 mov %o0, %o2
598 mov MMU_FAULT_AREA_INFO, %o5
599 ta FAST_TRAP
600 retl
601 stx %o1, [%o2]
602
603 END(hv_mmu_fault_area_info)
604
605 /*
606 * Section 13 Cache and Memory Services
607 *
608 */
609
610 /*
611 * zero from raddr to raddr+length-1
612 *
613 * arg0 raddr (%o0)
614 * arg1 length (%o1)
615 *
616 * ret0 status (%o0)
617 * ret1 length scrubbed (%o1)
618 *
619 */
620 ENTRY(hv_mem_scrub)
621 mov MEM_SCRUB, %o5
622 ta FAST_TRAP
623 stx %o1, [%o2]
624 retl
625 nop
626 END(hv_mem_scrub)
627
628 /*
629 * for the memory address range from raddr to raddr+length-1
630 * for the next access within that range from main system memory
631 *
632 * arg0 raddr (%o0)
633 * arg1 length (%o1)
634 *
635 * ret0 status (%o0)
636 * ret1 length synced (%o1)
637 *
638 */
639 ENTRY(hv_mem_sync)
640 mov MEM_SYNC, %o5
641 ta FAST_TRAP
642 stx %o1, [%o2]
643 retl
644 nop
645 END(hv_mem_sync)
646
647 /*
648 * Section 14 Device Interrupt Services
649 *
650 */
651
652 /*
653 * converts a device specific interrupt number given by
654 * devhandle and devino to a system specific ino (sysino)
655 *
656 * arg0 devhandle (%o0)
657 * arg1 devino (%o1)
658 *
659 * ret0 status (%o0)
660 * ret1 sysino (%o1)
661 *
662 */
663 ENTRY(hv_intr_devino_to_sysino)
664 mov INTR_DEVINO2SYSINO, %o5
665 ta FAST_TRAP
666 retl
667 stx %o1, [%o2]
668 END(hv_intr_devino_to_sysino)
669
670 /*
671 * return intr enabled state
672 *
673 * arg0 sysino (%o0)
674 *
675 * ret0 status (%o0)
676 * ret1 intr_enabled (%o1)
677 *
678 */
679 ENTRY(hv_intr_getenabled)
680 mov %o1, %o2
681 mov INTR_GETENABLED, %o5
682 ta FAST_TRAP
683 retl
684 st %o1, [%o2]
685 END(hv_intr_getenabled)
686
687 /*
688 * set intr enabled state
689 *
690 * arg0 sysino (%o0)
691 * arg1 intr_enabled (%o1)
692 *
693 * ret0 status (%o0)
694 *
695 */
696 ENTRY(hv_intr_setenabled)
697 mov INTR_SETENABLED, %o5
698 ta FAST_TRAP
699 retl
700 nop
701 END(hv_intr_setenabled)
702
703 /*
704 * return current state of the interrupt given
705 * by the sysino
706 *
707 * arg0 sysino (%o0)
708 *
709 * ret0 status (%o0)
710 * ret1 intr_state (%o1)
711 *
712 */
713 ENTRY(hv_intr_getstate)
714 mov %o1, %o2
715 mov INTR_GETSTATE, %o5
716 ta FAST_TRAP
717 retl
718 st %o1, [%o2]
719 END(hv_intr_getstate)
720
721 /*
722 * set the current state of the interrupt given
723 * by the sysino
724 *
725 * arg0 sysino (%o0)
726 * arg1 intr_state (%o1)
727 *
728 * ret0 status (%o0)
729 *
730 */
731 ENTRY(hv_intr_setstate)
732 mov INTR_SETSTATE, %o5
733 ta FAST_TRAP
734 retl
735 nop
736 END(hv_intr_setstate)
737
738 /*
739 * return the cpuid that is the current target of the
740 * interrupt given by the sysino
741 *
742 * arg0 sysino (%o0)
743 *
744 * ret0 status (%o0)
745 * ret1 cpuid (%o1)
746 *
747 */
748 ENTRY(hv_intr_gettarget)
749 mov %o1, %o2
750 mov INTR_GETTARGET, %o5
751 ta FAST_TRAP
752 retl
753 st %o1, [%o2]
754 END(hv_intr_gettarget)
755
756 /*
757 * set the target to cpuid that for the
758 * interrupt given by the sysino
759 *
760 * arg0 sysino (%o0)
761 * arg1 cpuid (%o1)
762 *
763 * ret0 status (%o0)
764 *
765 */
766 ENTRY(hv_intr_settarget)
767 mov INTR_SETTARGET, %o5
768 ta FAST_TRAP
769 retl
770 nop
771 END(hv_intr_settarget)
772
773 /*
774 * get the cookie value that will be delivered
775 * in word 0 of a dev_mondo packet to a guest
776 *
777 * arg0 devhandle (%o0)
778 * arg1 devino (%o1)
779 *
780 * ret0 status (%o0)
781 * ret1 cookie_value (%o1)
782 *
783 */
784 ENTRY(hv_vintr_getcookie)
785 mov VINTR_GETCOOKIE, %o5
786 ta FAST_TRAP
787 retl
788 stx %o1, [%o2]
789 END(hv_vintr_getcookie)
790
791 /*
792 * set the cookie value that will be delivered
793 * in word 0 of a dev_mondo packet to a guest
794 *
795 * arg0 devhandle (%o0)
796 * arg1 devino (%o1)
797 * ret2 cookie_value (%o2)
798 *
799 * ret0 status (%o0)
800 *
801 */
802 ENTRY(hv_vintr_setcookie)
803 mov VINTR_SETCOOKIE, %o5
804 ta FAST_TRAP
805 retl
806 nop
807 END(hv_vintr_setcookie)
808
809 /*
810 * get the enabled status of the interrupt
811 * defined by devino
812 *
813 * arg0 devhandle (%o0)
814 * arg1 devino (%o1)
815 *
816 * ret0 status (%o0)
817 * ret1 intr_enabled (%o1)
818 *
819 */
820 ENTRY(hv_vintr_getenabled)
821 mov VINTR_GETENABLED, %o5
822 ta FAST_TRAP
823 retl
824 st %o1, [%o2]
825 END(hv_vintr_getenabled)
826
827 /*
828 * set the enabled status of the interrupt
829 * defined by devino
830 *
831 * arg0 devhandle (%o0)
832 * arg1 devino (%o1)
833 * arg2 intr_enabled (%o2)
834 *
835 * ret0 status (%o0)
836 *
837 */
838 ENTRY(hv_vintr_setenabled)
839 mov VINTR_SETENABLED, %o5
840 ta FAST_TRAP
841 retl
842 nop
843 END(hv_vintr_setenabled)
844
845 /*
846 * get the current state of the interrupt
847 * defined by devino
848 *
849 * arg0 devhandle (%o0)
850 * arg1 devino (%o1)
851 *
852 * ret0 status (%o0)
853 * ret1 intr_state (%o1)
854 *
855 */
856 ENTRY(hv_vintr_getstate)
857 mov VINTR_GETSTATE, %o5
858 ta FAST_TRAP
859 retl
860 st %o1, [%o2]
861 END(hv_vintr_getstate)
862
863 /*
864 * set the current state of the interrupt
865 * defined by devino
866 *
867 * arg0 devhandle (%o0)
868 * arg1 devino (%o1)
869 * arg2 intr_state (%o2)
870 *
871 * ret0 status (%o0)
872 *
873 */
874 ENTRY(hv_vintr_setstate)
875 mov VINTR_SETSTATE, %o5
876 ta FAST_TRAP
877 retl
878 nop
879 END(hv_vintr_setstate)
880
881 /*
882 * get the cpuid that is the current target
883 * of the interrupt defined by devino
884 *
885 * arg0 devhandle (%o0)
886 * arg1 devino (%o1)
887 *
888 * ret0 status (%o0)
889 * ret1 cpuid (%o1)
890 *
891 */
892 ENTRY(hv_vintr_gettarget)
893 mov VINTR_GETTARGET, %o5
894 ta FAST_TRAP
895 retl
896 st %o1, [%o2]
897 END(hv_vintr_gettarget)
898
899 /*
900 * set the cpuid that is the current target
901 * of the interrupt defined by devino
902 *
903 * arg0 devhandle (%o0)
904 * arg1 devino (%o1)
905 * arg2 cpuid (%o2)
906 *
907 * ret0 status (%o0)
908 *
909 */
910 ENTRY(hv_vintr_settarget)
911 mov VINTR_SETTARGET, %o5
912 ta FAST_TRAP
913 retl
914 nop
915 END(hv_vintr_settarget)
916
917
918 /*
919 * Section 15 Time of Day Services
920 *
921 */
922
923 /*
924 * get the current time of day
925 *
926 * ret0 status (%o0)
927 * ret1 time-of-day (%o1)
928 *
929 */
930 ENTRY(hv_tod_get)
931 mov %o0, %o2
932 mov TOD_GET, %o5
933 ta FAST_TRAP
934 retl
935 stx %o1, [%o2]
936 END(hv_tod_get)
937
938 /*
939 * set the current time-of-day
940 * arg0 tod (%o0)
941 *
942 * ret0 status (%o0)
943 *
944 */
945 ENTRY(hv_tod_set)
946 mov TOD_SET, %o5
947 ta FAST_TRAP
948 retl
949 nop
950 END(hv_tod_set)
951
952 /*
953 * Section 16 Console Services
954 *
955 */
956
957 /*
958 * return a character from the console device
959 *
960 * ret0 status (%o0)
961 * ret1 character (%o1)
962 *
963 */
964 ENTRY(hv_cons_getchar)
965 mov %o0, %o2
966 mov CONS_GETCHAR, %o5
967 ta FAST_TRAP
968 brnz,a %o0, 1f
969 mov 1, %o0
970
971 cmp %o1, H_BREAK
972 be 1f
973 mov %o1, %o0
974
975 cmp %o1, H_HUP
976 be 1f
977 mov %o1, %o0
978
979 stb %o1, [%o2]
980 mov 0, %o0
981 1:
982 retl
983 nop
984 END(hv_cons_getchar)
985
986 /*
987 * send a character to the console device
988 * arg0 char (%o0)
989 *
990 * ret0 status (%o0)
991 *
992 */
993 ENTRY(hv_cons_putchar)
994 mov CONS_PUTCHAR, %o5
995 ta FAST_TRAP
996 retl
997 nop
998 END(hv_cons_putchar)
999
1000 /*
1001 * write characters in raddr to console
1002 * arg0 raddr (%o0)
1003 * arg1 size (%o1)
1004 *
1005 * ret0 status (%o0)
1006 * ret1 char written (%o1)
1007 *
1008 */
1009 ENTRY(hv_cons_write)
1010 mov %o2, %o3
1011 mov CONS_WRITE, %o5
1012 ta FAST_TRAP
1013 brnz,a %o0, 1f ! failure, just return error
1014 mov 1, %o0
1015 stx %o1, [%o3]
1016 1: retl
1017 nop
1018 END(hv_cons_write)
1019
1020 /*
1021 * read up to size characters from console in to raddr
1022 * arg0 raddr (%o0)
1023 * arg1 size
1024 *
1025 * ret0 status (%o0)
1026 * ret1 char written (%o1)
1027 *
1028 */
1029 ENTRY(hv_cons_read)
1030 mov %o2, %o3
1031 mov CONS_READ, %o5
1032 ta FAST_TRAP
1033 brnz,a %o0, 1f ! failure, just return error
1034 mov 1, %o0
1035
1036 cmp %o1, H_BREAK
1037 be 1f
1038 mov %o1, %o0
1039
1040 cmp %o1, H_HUP
1041 be 1f
1042 mov %o1, %o0
1043
1044 stx %o1, [%o3]
1045 1: retl
1046 nop
1047 END(hv_cons_read)
1048
1049
1050 /*
1051 * Section 17 Core Dump Services
1052 *
1053 */
1054
1055 /*
1056 * declare a domain dump buffer to the hypervisor
1057 * arg0 raddr (%o0)
1058 * arg1 size (%o1)
1059 *
1060 * ret0 status (%o0)
1061 * ret1 required size of the dump buffer (%o1)
1062 *
1063 */
1064 ENTRY(hv_dump_buf_update)
1065 mov DUMP_BUF_UPDATE, %o5
1066 ta FAST_TRAP
1067 retl
1068 stx %o1, [%o2]
1069 END(hv_dump_buf_update)
1070
1071 /*
1072 * return the currently configured dump buffer description
1073 *
1074 * ret0 status (%o0)
1075 * ret1 ra of the current dump buffer (%o1)
1076 * ret2 size of the current dump buffer (%o2)
1077 *
1078 */
1079 ENTRY(hv_dump_buf_info)
1080 mov %o0, %o3
1081 mov %o1, %o4
1082 mov DUMP_BUF_INFO, %o5
1083 ta FAST_TRAP
1084 stx %o1, [%o3]
1085 retl
1086 stx %o2, [%o4]
1087 END(hv_dump_buf_info)
1088
1089 /*
1090 * Section 18 Trap Trace Services
1091 *
1092 */
1093
1094 /*
1095 * arg0 RA base of buffer (%o0)
1096 * arg1 buf size in no. of entries (%o1)
1097 *
1098 * ret0 status (%o0)
1099 * ret1 minimum size in no. of entries on failure,
1100 * actual size in no. of entries on success (%o1)
1101 *
1102 */
1103 ENTRY(hv_ttrace_buf_conf)
1104 mov TTRACE_BUF_CONF, %o5
1105 ta FAST_TRAP
1106 retl
1107 stx %o1, [%o2]
1108 END(hv_ttrace_buf_conf)
1109
1110 /*
1111 * return the size and location of a previously declare
1112 * trap-trace buffer
1113 *
1114 * ret0 status (%o0)
1115 * ret1 RA base of buffer (%o1)
1116 * ret2 size in no. of entries (%o2)
1117 *
1118 */
1119 ENTRY(hv_ttrace_buf_info)
1120 mov %o0, %o3
1121 mov %o1, %o4
1122 mov TTRACE_BUF_INFO, %o5
1123 ta FAST_TRAP
1124 stx %o1, [%o3]
1125 retl
1126 stx %o2, [%o4]
1127 END(hv_ttrace_buf_info)
1128
1129 /*
1130 * enable / disable trap tracing
1131 *
1132 * arg0 enable / disable (%o0)
1133 *
1134 * ret0 status (%o0)
1135 * ret1 previous enable state (%o1)
1136 *
1137 */
1138 ENTRY(hv_ttrace_enable)
1139 mov %o1, %o2
1140 mov TTRACE_ENABLE, %o5
1141 ta FAST_TRAP
1142 retl
1143 stx %o1, [%o2]
1144 END(hv_ttrace_enable)
1145
1146 /*
1147 * TTRACE_FREEZE
1148 * arg0 enable/ freeze (%o0)
1149 *
1150 * ret0 status (%o0)
1151 * ret1 previous freeze state (%o1)
1152 *
1153 */
1154 ENTRY(hv_ttrace_freeze)
1155 mov %o1, %o2
1156 mov TTRACE_FREEZE, %o5
1157 ta FAST_TRAP
1158 retl
1159 stx %o1, [%o2]
1160 END(hv_ttrace_freeze)
1161
1162 /*
1163 * add an entry to the trap trace buffer
1164 *
1165 * arg0 tag (16-bits) (%o0)
1166 * arg1 data word 0 (%o1)
1167 * arg2 data word 1 (%o2)
1168 * arg3 data word 2 (%o3)
1169 * arg4 data word 3 (%o4)
1170 *
1171 * ret0 status (%o0)
1172 *
1173 */
1174 ENTRY(hv_ttrace_addentry)
1175 ta TTRACE_ADDENTRY
1176 retl
1177 nop
1178 END(hv_ttrace_addentry)
1179
1180 /*
1181 * Section 19 Logical Domain Channel Services
1182 *
1183 */
1184
1185 /*
1186 * configure ldc tx queue
1187 *
1188 * arg0 ldc_id (%o0)
1189 * arg1 base_raddr (%o1)
1190 * arg2 nentries (%o2)
1191 *
1192 * ret0 status (%o0)
1193 *
1194 */
1195 ENTRY(hv_ldc_tx_qconf)
1196 mov LDC_TX_QCONF, %o5
1197 ta FAST_TRAP
1198 retl
1199 nop
1200 END(hv_ldc_tx_qconf)
1201
1202 /*
1203 * return configuration info for ldc tx queue
1204 *
1205 * arg0 ldc_id (%o0)
1206 *
1207 * ret0 status (%o0)
1208 * ret1 base_raddr (%o1)
1209 * ret2 nentries (%o2)
1210 *
1211 */
1212 ENTRY(hv_ldc_tx_qinfo)
1213 mov %o1, %o3
1214 mov %o2, %o4
1215 mov LDC_TX_QINFO, %o5
1216 ta FAST_TRAP
1217 brnz %o0, 1f
1218 nop
1219 stx %o1, [%o3]
1220 stx %o2, [%o4]
1221 1: retl
1222 nop
1223 END(hv_ldc_tx_qinfo)
1224
1225 /*
1226 * get the state of the ldc tx queue
1227 *
1228 * arg0 ldc_id (%o0)
1229 *
1230 * ret0 status (%o0)
1231 * ret1 head_offset (%o1)
1232 * ret2 tail_offset (%o2)
1233 * ret3 channel_state (%o3)
1234 *
1235 */
1236 ENTRY(hv_ldc_tx_get_state)
1237 mov %o1, %o4
1238 mov LDC_TX_GET_STATE, %o5
1239 ta FAST_TRAP
1240 brnz %o0, 1f
1241 nop
1242 stx %o1, [%o4]
1243 stx %o2, [%o4 + 8]
1244 stx %o3, [%o4 + 16]
1245 1: retl
1246 nop
1247 END(hv_ldc_tx_get_state)
1248
1249 /*
1250 * update the tail pointer of the ldc tx queue
1251 *
1252 * arg0 ldc_id (%o0)
1253 * arg1 tail_offset (%o1)
1254 *
1255 * ret0 status (%o0)
1256 *
1257 */
1258 ENTRY(hv_ldc_tx_set_qtail)
1259 mov LDC_TX_SET_QTAIL, %o5
1260 ta FAST_TRAP
1261 retl
1262 nop
1263 END(hv_ldc_tx_set_qtail)
1264
1265 /*
1266 * configure ldc rx queue
1267 *
1268 * arg0 ldc_id (%o0)
1269 * arg1 base_raddr (%o1)
1270 * arg2 nentries (%o2)
1271 *
1272 * ret0 status (%o0)
1273 *
1274 */
1275 ENTRY(hv_ldc_rx_qconf)
1276 mov LDC_RX_QCONF, %o5
1277 ta FAST_TRAP
1278 retl
1279 nop
1280 END(hv_ldc_rx_qconf)
1281
1282 /*
1283 * return configuration info for ldc rx queue
1284 *
1285 * arg0 ldc_id (%o0)
1286 *
1287 * ret0 status (%o0)
1288 * ret1 base_raddr (%o1)
1289 * ret2 nentries (%o2)
1290 *
1291 */
1292 ENTRY(hv_ldc_rx_qinfo)
1293 mov %o1, %o3
1294 mov %o2, %o4
1295 mov LDC_RX_QINFO, %o5
1296 ta FAST_TRAP
1297 brnz %o0, 1f
1298 nop
1299 stx %o1, [%o3]
1300 stx %o2, [%o4]
1301 1: retl
1302 nop
1303 END(hv_ldc_rx_qinfo)
1304
1305 /*
1306 * get the state of the ldc rx queue
1307 *
1308 * arg0 ldc_id (%o0)
1309 *
1310 * ret0 status (%o0)
1311 * ret1 head_offset (%o1)
1312 * ret2 tail_offset (%o2)
1313 * ret3 channel_state (%o3)
1314 *
1315 */
1316 ENTRY(hv_ldc_rx_get_state)
1317 mov %o1, %o4
1318 mov LDC_RX_GET_STATE, %o5
1319 ta FAST_TRAP
1320 brnz %o0, 1f
1321 nop
1322 stx %o1, [%o4]
1323 stx %o2, [%o4 + 8]
1324 stx %o3, [%o4 + 16]
1325 1: retl
1326 nop
1327 END(hv_ldc_rx_get_state)
1328
1329 /*
1330 * update the head pointer of the ldc rx queue
1331 *
1332 * arg0 ldc_id (%o0)
1333 * arg1 head_offset (%o1)
1334 *
1335 * ret0 status (%o0)
1336 *
1337 */
1338 ENTRY(hv_ldc_rx_set_qhead)
1339 mov LDC_RX_SET_QHEAD, %o5
1340 ta FAST_TRAP
1341 retl
1342 nop
1343 END(hv_ldc_rx_set_qhead)
1344
1345 /*
1346 * declare an export map table
1347 *
1348 * arg0 channel (%o0)
1349 * arg1 base_ra (%o1)
1350 * arg2 nentries (%o2)
1351 *
1352 * ret0 status (%o0)
1353 *
1354 */
1355 ENTRY(hv_ldc_set_map_table)
1356 mov LDC_SET_MAPTABLE, %o5
1357 ta FAST_TRAP
1358 retl
1359 nop
1360 END(hv_ldc_set_map_table)
1361
1362 /*
1363 * retrieve the current map table configuration associated
1364 * with the given domain channel
1365 *
1366 * arg0 channel (%o0)
1367 *
1368 * ret0 status (%o0)
1369 * ret1 base_ra (%o1)
1370 * ret2 nentries (%o2)
1371 *
1372 */
1373 ENTRY(hv_ldc_get_map_table)
1374 mov %o1, %o3
1375 mov %o2, %o4
1376 mov LDC_GET_MAPTABLE, %o5
1377 ta FAST_TRAP
1378 stx %o1, [%o3]
1379 retl
1380 stx %o2, [%o4]
1381 END(hv_ldc_get_map_table)
1382
1383 /*
1384 * copy data into or out of a local memory region form or to
1385 * the logical domain at the other end of the specified domain
1386 * channel
1387 *
1388 * arg0 channel (%o0)
1389 * arg1 flags (%o1)
1390 * arg2 cookie (%o2)
1391 * arg3 raddr (%o3)
1392 * arg4 length (%o4)
1393 *
1394 * ret0 status (%o0)
1395 * ret1 ret_length (%o1)
1396 *
1397 */
1398 ENTRY(hv_ldc_copy)
1399 END(hv_ldc_copy)
1400
1401 /*
1402 * attempt to map into the local guest's real address space the
1403 * page identified by the shared memory cookie
1404 *
1405 * arg0 channel (%o0)
1406 * arg1 cookie (%o1)
1407 *
1408 * ret0 status (%o0)
1409 * ret1 raddr (%o1)
1410 * ret2 perms (%o2)
1411 *
1412 */
1413 ENTRY(hv_ldc_mapin)
1414 mov %o3, %o4
1415 mov %o2, %o3
1416 mov LDC_MAPIN, %o5
1417 ta FAST_TRAP
1418 stx %o1, [%o3]
1419 retl
1420 stx %o2, [%o4]
1421 END(hv_ldc_mapin)
1422
1423 /*
1424 * attempt unmap from the local guest's real address space the imported
1425 * page mapped at the real address raddr
1426 *
1427 * arg0 raddr (%o0)
1428 *
1429 * ret0 status (%o0)
1430 *
1431 */
1432 ENTRY(hv_ldc_unmap)
1433 mov LDC_UNMAP, %o5
1434 ta FAST_TRAP
1435 retl
1436 nop
1437 END(hv_ldc_unmap)
1438
1439 /*
1440 * forcibly unmap from a remote guest's real address space a page
1441 * previously exported by the local guest
1442 *
1443 * arg0 channel (%o0)
1444 * arg1 cookie (%o1)
1445 * arg2 revoke_cookie (%o2)
1446 *
1447 * ret0 status (%o0)
1448 *
1449 */
1450 ENTRY(hv_ldc_revoke)
1451 mov LDC_REVOKE, %o5
1452 ta FAST_TRAP
1453 retl
1454 nop
1455 END(hv_ldc_revoke)
1456
1457 /*
1458 * Section 20 PCI I/O Services
1459 *
1460 */
1461
1462 /*
1463 * create iommu mappings in the device defined by devhandle
1464 *
1465 * arg0 devhandle (%o0)
1466 * arg1 tsbid (%o1)
1467 * arg2 nttes (%o2)
1468 * arg3 io_attributes (%o3)
1469 * arg4 io_page_list_p (%o4)
1470 *
1471 * ret0 status (%o0)
1472 * ret1 nttes_mapped (%o1)
1473 *
1474 */
1475 ENTRY(hv_pci_iommu_map)
1476 save %sp, -CCFSZ, %sp
1477 mov %i0, %o0
1478 mov %i1, %o1
1479 mov %i2, %o2
1480 mov %i3, %o3
1481 mov %i4, %o4
1482 mov PCI_IOMMU_MAP, %o5
1483 ta FAST_TRAP
1484 brnz %o0, 1f
1485 mov %o0, %i0
1486 stuw %o1, [%i5]
1487 1:
1488 ret
1489 restore
1490 END(hv_pci_iommu_map)
1491
1492 /*
1493 * demap and flush iommu mappings in the device defined by devhandle
1494 *
1495 * arg0 devhandle (%o0)
1496 * arg1 tsbid (%o1)
1497 * arg2 nttes (%o2)
1498 *
1499 * ret0 status (%o0)
1500 * ret1 nttes_demapped (%o1)
1501 *
1502 */
1503 ENTRY(hv_pci_iommu_demap)
1504 mov PCI_IOMMU_DEMAP, %o5
1505 ta FAST_TRAP
1506 brz,a %o0, 1f
1507 stuw %o1, [%o3]
1508 1: retl
1509 nop
1510 END(hv_pci_iommu_demap)
1511
1512 /*
1513 * read and return the mapping in the device defined by devhandle
1514 *
1515 * arg0 devhandle (%o0)
1516 * arg1 tsbid (%o1)
1517 *
1518 * ret0 status (%o0)
1519 * ret1 io_attributes (%o1)
1520 * ret2 ra (%o2)
1521 *
1522 */
1523 ENTRY(hv_pci_iommu_getmap)
1524 mov %o3, %o4
1525 mov %o2, %o3
1526 mov PCI_IOMMU_GETMAP, %o5
1527 ta FAST_TRAP
1528 brnz %o0, 1f
1529 nop
1530 st %o1, [%o3]
1531 stx %o2, [%o4]
1532 1: retl
1533 nop
1534 END(hv_pci_iommu_getmap)
1535
1536 /*
1537 * create a "special" mapping in the device given by devhandle
1538 *
1539 * arg0 devhandle (%o0)
1540 * arg1 r_addr (%o1)
1541 * arg2 io_attributes (%o2)
1542 *
1543 * ret0 status (%o0)
1544 * ret1 io_addr (%o1)
1545 *
1546 */
1547 ENTRY(hv_pci_iommu_getbypass)
1548 mov PCI_IOMMU_GETBYPASS, %o5
1549 ta FAST_TRAP
1550 brnz %o0, 1f
1551 nop
1552 stx %o1, [%o3]
1553 1: retl
1554 nop
1555 END(hv_pci_iommu_getbypass)
1556
1557 /*
1558 * read PCI configuration space for adapter specified by devhandle
1559 *
1560 * arg0 devhandle (%o0)
1561 * arg1 pci_device (%o1)
1562 * arg2 pci_config_offset(%o2)
1563 * arg3 size (%o3)
1564 *
1565 * ret0 status (%o0)
1566 * ret1 error_flag (%o1)
1567 * ret2 data (%o2)
1568 *
1569 */
1570 ENTRY(hv_pci_config_get)
1571 mov PCI_CONFIG_GET, %o5
1572 ta FAST_TRAP
1573 brnz %o0, 1f
1574 movrnz %o1, -1, %o2
1575 brz,a %o1, 1f
1576 stuw %o2, [%o4]
1577 1: retl
1578 nop
1579 END(hv_pci_config_get)
1580
1581 /*
1582 * write PCI config space for the PCI adapter
1583 * specified by devhandle
1584 *
1585 * arg0 devhandle (%o0)
1586 * arg1 pci_device (%o1)
1587 * arg2 pci_config_offset(%o2)
1588 * arg3 size (%o3)
1589 * arg4 data (%o4)
1590 *
1591 * ret0 status (%o0)
1592 * ret1 error_flag (%o1)
1593 *
1594 */
1595 ENTRY(hv_pci_config_put)
1596 mov PCI_CONFIG_PUT, %o5
1597 ta FAST_TRAP
1598 retl
1599 nop
1600 END(hv_pci_config_put)
1601
1602 /*
1603 * read the io-address given by devhandle, raddr, and size
1604 *
1605 * arg0 devhandle (%o0)
1606 * arg1 raddr (%o1)
1607 * arg2 size (%o2)
1608 *
1609 * ret0 status (%o0)
1610 * ret1 error_flag (%o1)
1611 * ret2 data (%o2)
1612 *
1613 */
1614 ENTRY(hv_pci_peek)
1615 mov PCI_PEEK, %o5
1616 ta FAST_TRAP
1617 brnz %o0, 1f
1618 nop
1619 st %o1, [%o3]
1620 stx %o2, [%o4]
1621 1: retl
1622 nop
1623 END(hv_pci_peek)
1624
1625 /*
1626 * attempt to write data to the io-address
1627 * specified by devhandle, raddr, and size
1628 *
1629 * arg0 devhandle (%o0)
1630 * arg1 raddr (%o1)
1631 * arg2 size (%o2)
1632 * arg3 data (%o3)
1633 * arg4 pci_device (%o4)
1634 *
1635 * ret0 status (%o0)
1636 * ret1 error_flag (%o1)
1637 *
1638 */
1639 ENTRY(hv_pci_poke)
1640 save %sp, -CCFSZ, %sp
1641 mov %i0, %o0
1642 mov %i1, %o1
1643 mov %i2, %o2
1644 mov %i3, %o3
1645 mov %i4, %o4
1646 mov PCI_POKE, %o5
1647 ta FAST_TRAP
1648 brnz %o0, 1f
1649 mov %o0, %i0
1650 stuw %o1, [%i5]
1651 1:
1652 ret
1653 restore
1654 END(hv_pci_poke)
1655
1656 /*
1657 * attempt to write data to the io-address
1658 * specified by devhandle, raddr, and size
1659 *
1660 * arg0 devhandle (%o0)
1661 * arg1 raddr (%o1)
1662 * arg2 size (%o2)
1663 * arg3 io_sync_direction(%o3)
1664 *
1665 * ret0 status (%o0)
1666 * ret1 nsynced (%o1)
1667 *
1668 */
1669 ENTRY(hv_pci_dma_sync)
1670 mov PCI_DMA_SYNC, %o5
1671 ta FAST_TRAP
1672 brnz %o0, 1f
1673 nop
1674 stx %o1, [%o4]
1675 1: retl
1676 nop
1677 END(hv_pci_dma_sync)
1678
1679 /*
1680 * Section 21 MSI Services
1681 *
1682 */
1683
1684 ENTRY(hv_pci_msiq_conf)
1685 END(hv_pci_msiq_conf)
1686
1687 ENTRY(hv_pci_msiq_info)
1688 END(hv_pci_msiq_info)
1689
1690 ENTRY(hv_pci_msiq_getvalid)
1691 END(hv_pci_msiq_getvalid)
1692
1693 ENTRY(hv_pci_msiq_setvalid)
1694 END(hv_pci_msiq_setvalid)
1695
1696 ENTRY(hv_pci_msiq_getstate)
1697 END(hv_pci_msiq_getstate)
1698
1699 ENTRY(hv_pci_msiq_setstate)
1700 END(hv_pci_msiq_setstate)
1701
1702 ENTRY(hv_pci_msiq_gethead)
1703 END(hv_pci_msiq_gethead)
1704
1705 ENTRY(hv_pci_msiq_sethead)
1706 END(hv_pci_msiq_sethead)
1707
1708 ENTRY(hv_pci_msiq_gettail)
1709 END(hv_pci_msiq_gettail)
1710
1711 ENTRY(hv_pci_msi_getvalid)
1712 END(hv_pci_msi_getvalid)
1713
1714 ENTRY(hv_pci_msi_setvalid)
1715 END(hv_pci_msi_setvalid)
1716
1717 ENTRY(hv_pci_msi_getmsiq)
1718 END(hv_pci_msi_getmsiq)
1719
1720 ENTRY(hv_pci_msi_setmsiq)
1721 END(hv_pci_msi_setmsiq)
1722
1723 ENTRY(hv_pci_msi_getstate)
1724 END(hv_pci_msi_getstate)
1725
1726 ENTRY(hv_pci_msi_setstate)
1727 END(hv_pci_msi_setstate)
1728
1729 ENTRY(hv_pci_msg_getmsiq)
1730 END(hv_pci_msg_getmsiq)
1731
1732 ENTRY(hv_pci_msg_setmsiq)
1733 END(hv_pci_msg_setmsiq)
1734
1735 ENTRY(hv_pci_msg_getvalid)
1736 END(hv_pci_msg_getvalid)
1737
1738 ENTRY(hv_pci_msg_setvalid)
1739 END(hv_pci_msg_setvalid)
1740
1741 /*
1742 * Section 22 UltraSPARC T1 Performance Counters
1743 *
1744 */
1745
1746
1747 /*
1748 * read the value of the DRAM/JBus performance register as selected by
1749 * the perfreg argument
1750 *
1751 * arg0 perfreg (%o0)
1752 *
1753 * ret0 status (%o0)
1754 * ret1 value (%o1)
1755 *
1756 */
1757 ENTRY(hv_niagara_get_perfreg)
1758 mov %o1, %o2
1759 mov NIAGARA_GET_PERFREG, %o5
1760 ta FAST_TRAP
1761 retl
1762 stx %o1, [%o2]
1763 END(hv_niagara_get_perfreg)
1764
1765 /*
1766 * set the value of the DRAM/JBus performance register as selected by
1767 * the perfreg argument
1768 *
1769 * arg0 perfreg (%o0)
1770 * arg1 value (%o1)
1771 *
1772 * ret0 status (%o0)
1773 *
1774 */
1775 ENTRY(hv_niagara_set_perfreg)
1776 mov NIAGARA_SET_PERFREG, %o5
1777 ta FAST_TRAP
1778 retl
1779 nop
1780 END(hv_niagara_set_perfreg)
1781
1782 /*
1783 * Section 23 UltraSPARC T1 MMU Statistics Counters
1784 *
1785 */
1786
1787 /*
1788 * enable MMU statistics collection and supply the buffer to deposit the
1789 * results for the current virtual cpu
1790 *
1791 * arg0 raddr (%o0)
1792 *
1793 * ret0 status (%o0)
1794 * ret1 prev_raddr (%o1)
1795 *
1796 */
1797 ENTRY(hv_niagara_mmustat_conf)
1798 mov %o1, %o2
1799 mov NIAGARA_MMUSTAT_CONF, %o5
1800 ta FAST_TRAP
1801 retl
1802 stx %o1, [%o2]
1803 END(hv_niagara_mmustat_conf)
1804
1805 /*
1806 * query the status and the real address for the currently configured buffer
1807 *
1808 * ret0 status (%o0)
1809 * ret1 raddr (%o1)
1810 *
1811 */
1812 ENTRY(hv_niagara_mmustat_info)
1813 mov %o0, %o2
1814 mov NIAGARA_MMUSTAT_INFO, %o5
1815 ta FAST_TRAP
1816 retl
1817 stx %o1, [%o2]
1818 END(hv_niagara_mmustat_info)
1819
1820 /*
1821 * Simulator Services
1822 *
1823 */
1824
1825 ENTRY(hv_magic_trap_on)
1826 ta 0x77
1827 retl
1828 nop
1829 END(hv_magic_trap_on)
1830
1831 ENTRY(hv_magic_trap_off)
1832 ta 0x78
1833 retl
1834 nop
1835 END(hv_magic_trap_off)
1836
1837
1838 ENTRY(hv_sim_read)
1839 mov SIM_READ, %o5
1840 ta FAST_TRAP
1841 retl
1842 nop
1843 END(hv_read)
1844
1845 ENTRY(hv_sim_write)
1846 mov SIM_WRITE, %o5
1847 ta FAST_TRAP
1848 retl
1849 nop
1850 END(hv_write)
1851
1852
Cache object: d586b2e7d33abf5ad2786d3f17959a1a
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