FreeBSD/Linux Kernel Cross Reference
sys/sys/pmc.h
1 /*-
2 * Copyright (c) 2003-2008, Joseph Koshy
3 * Copyright (c) 2007 The FreeBSD Foundation
4 * All rights reserved.
5 *
6 * Portions of this software were developed by A. Joseph Koshy under
7 * sponsorship from the FreeBSD Foundation and Google, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD: releng/10.3/sys/sys/pmc.h 294046 2016-01-14 22:02:21Z jtl $
31 */
32
33 #ifndef _SYS_PMC_H_
34 #define _SYS_PMC_H_
35
36 #include <dev/hwpmc/pmc_events.h>
37
38 #include <machine/pmc_mdep.h>
39 #include <machine/profile.h>
40
41 #define PMC_MODULE_NAME "hwpmc"
42 #define PMC_NAME_MAX 64 /* HW counter name size */
43 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */
44
45 /*
46 * Kernel<->userland API version number [MMmmpppp]
47 *
48 * Major numbers are to be incremented when an incompatible change to
49 * the ABI occurs that older clients will not be able to handle.
50 *
51 * Minor numbers are incremented when a backwards compatible change
52 * occurs that allows older correct programs to run unchanged. For
53 * example, when support for a new PMC type is added.
54 *
55 * The patch version is incremented for every bug fix.
56 */
57 #define PMC_VERSION_MAJOR 0x03
58 #define PMC_VERSION_MINOR 0x01
59 #define PMC_VERSION_PATCH 0x0000
60
61 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \
62 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH)
63
64 /*
65 * Kinds of CPUs known.
66 *
67 * We keep track of CPU variants that need to be distinguished in
68 * some way for PMC operations. CPU names are grouped by manufacturer
69 * and numbered sparsely in order to minimize changes to the ABI involved
70 * when new CPUs are added.
71 */
72
73 #define __PMC_CPUS() \
74 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \
75 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \
76 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \
77 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \
78 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \
79 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \
80 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \
81 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \
82 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \
83 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
84 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
85 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
86 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \
87 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
88 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \
89 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \
90 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \
91 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \
92 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \
93 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \
94 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \
95 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \
96 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \
97 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \
98 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
99 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
100 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
101 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \
102 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \
103 __PMC_CPU(GENERIC, 0x400, "Generic")
104
105 enum pmc_cputype {
106 #undef __PMC_CPU
107 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V,
108 __PMC_CPUS()
109 };
110
111 #define PMC_CPU_FIRST PMC_CPU_AMD_K7
112 #define PMC_CPU_LAST PMC_CPU_GENERIC
113
114 /*
115 * Classes of PMCs
116 */
117
118 #define __PMC_CLASSES() \
119 __PMC_CLASS(TSC) /* CPU Timestamp counter */ \
120 __PMC_CLASS(K7) /* AMD K7 performance counters */ \
121 __PMC_CLASS(K8) /* AMD K8 performance counters */ \
122 __PMC_CLASS(P5) /* Intel Pentium counters */ \
123 __PMC_CLASS(P6) /* Intel Pentium Pro counters */ \
124 __PMC_CLASS(P4) /* Intel Pentium-IV counters */ \
125 __PMC_CLASS(IAF) /* Intel Core2/Atom, fixed function */ \
126 __PMC_CLASS(IAP) /* Intel Core...Atom, programmable */ \
127 __PMC_CLASS(UCF) /* Intel Uncore fixed function */ \
128 __PMC_CLASS(UCP) /* Intel Uncore programmable */ \
129 __PMC_CLASS(XSCALE) /* Intel XScale counters */ \
130 __PMC_CLASS(MIPS24K) /* MIPS 24K */ \
131 __PMC_CLASS(OCTEON) /* Cavium Octeon */ \
132 __PMC_CLASS(PPC7450) /* Motorola MPC7450 class */ \
133 __PMC_CLASS(PPC970) /* IBM PowerPC 970 class */ \
134 __PMC_CLASS(SOFT) /* Software events */
135
136 enum pmc_class {
137 #undef __PMC_CLASS
138 #define __PMC_CLASS(N) PMC_CLASS_##N ,
139 __PMC_CLASSES()
140 };
141
142 #define PMC_CLASS_FIRST PMC_CLASS_TSC
143 #define PMC_CLASS_LAST PMC_CLASS_SOFT
144
145 /*
146 * A PMC can be in the following states:
147 *
148 * Hardware states:
149 * DISABLED -- administratively prohibited from being used.
150 * FREE -- HW available for use
151 * Software states:
152 * ALLOCATED -- allocated
153 * STOPPED -- allocated, but not counting events
154 * RUNNING -- allocated, and in operation; 'pm_runcount'
155 * holds the number of CPUs using this PMC at
156 * a given instant
157 * DELETED -- being destroyed
158 */
159
160 #define __PMC_HWSTATES() \
161 __PMC_STATE(DISABLED) \
162 __PMC_STATE(FREE)
163
164 #define __PMC_SWSTATES() \
165 __PMC_STATE(ALLOCATED) \
166 __PMC_STATE(STOPPED) \
167 __PMC_STATE(RUNNING) \
168 __PMC_STATE(DELETED)
169
170 #define __PMC_STATES() \
171 __PMC_HWSTATES() \
172 __PMC_SWSTATES()
173
174 enum pmc_state {
175 #undef __PMC_STATE
176 #define __PMC_STATE(S) PMC_STATE_##S,
177 __PMC_STATES()
178 __PMC_STATE(MAX)
179 };
180
181 #define PMC_STATE_FIRST PMC_STATE_DISABLED
182 #define PMC_STATE_LAST PMC_STATE_DELETED
183
184 /*
185 * An allocated PMC may used as a 'global' counter or as a
186 * 'thread-private' one. Each such mode of use can be in either
187 * statistical sampling mode or in counting mode. Thus a PMC in use
188 *
189 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling
190 * SC i.e., SYSTEM COUNTER -- system-wide counting mode
191 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling
192 * TC i.e., THREAD COUNTER -- thread virtual, counting mode
193 *
194 * Statistical profiling modes rely on the PMC periodically delivering
195 * a interrupt to the CPU (when the configured number of events have
196 * been measured), so the PMC must have the ability to generate
197 * interrupts.
198 *
199 * In counting modes, the PMC counts its configured events, with the
200 * value of the PMC being read whenever needed by its owner process.
201 *
202 * The thread specific modes "virtualize" the PMCs -- the PMCs appear
203 * to be thread private and count events only when the profiled thread
204 * actually executes on the CPU.
205 *
206 * The system-wide "global" modes keep the PMCs running all the time
207 * and are used to measure the behaviour of the whole system.
208 */
209
210 #define __PMC_MODES() \
211 __PMC_MODE(SS, 0) \
212 __PMC_MODE(SC, 1) \
213 __PMC_MODE(TS, 2) \
214 __PMC_MODE(TC, 3)
215
216 enum pmc_mode {
217 #undef __PMC_MODE
218 #define __PMC_MODE(M,N) PMC_MODE_##M = N,
219 __PMC_MODES()
220 };
221
222 #define PMC_MODE_FIRST PMC_MODE_SS
223 #define PMC_MODE_LAST PMC_MODE_TC
224
225 #define PMC_IS_COUNTING_MODE(mode) \
226 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC)
227 #define PMC_IS_SYSTEM_MODE(mode) \
228 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC)
229 #define PMC_IS_SAMPLING_MODE(mode) \
230 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS)
231 #define PMC_IS_VIRTUAL_MODE(mode) \
232 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC)
233
234 /*
235 * PMC row disposition
236 */
237
238 #define __PMC_DISPOSITIONS(N) \
239 __PMC_DISP(STANDALONE) /* global/disabled counters */ \
240 __PMC_DISP(FREE) /* free/available */ \
241 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \
242 __PMC_DISP(UNKNOWN) /* sentinel */
243
244 enum pmc_disp {
245 #undef __PMC_DISP
246 #define __PMC_DISP(D) PMC_DISP_##D ,
247 __PMC_DISPOSITIONS()
248 };
249
250 #define PMC_DISP_FIRST PMC_DISP_STANDALONE
251 #define PMC_DISP_LAST PMC_DISP_THREAD
252
253 /*
254 * Counter capabilities
255 *
256 * __PMC_CAPS(NAME, VALUE, DESCRIPTION)
257 */
258
259 #define __PMC_CAPS() \
260 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \
261 __PMC_CAP(USER, 1, "count user-mode events") \
262 __PMC_CAP(SYSTEM, 2, "count system-mode events") \
263 __PMC_CAP(EDGE, 3, "do edge detection of events") \
264 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \
265 __PMC_CAP(READ, 5, "read PMC counter") \
266 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \
267 __PMC_CAP(INVERT, 7, "invert comparision sense") \
268 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \
269 __PMC_CAP(PRECISE, 9, "perform precise sampling") \
270 __PMC_CAP(TAGGING, 10, "tag upstream events") \
271 __PMC_CAP(CASCADE, 11, "cascade counters")
272
273 enum pmc_caps
274 {
275 #undef __PMC_CAP
276 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) ,
277 __PMC_CAPS()
278 };
279
280 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT
281 #define PMC_CAP_LAST PMC_CAP_CASCADE
282
283 /*
284 * PMC Event Numbers
285 *
286 * These are generated from the definitions in "dev/hwpmc/pmc_events.h".
287 */
288
289 enum pmc_event {
290 #undef __PMC_EV
291 #undef __PMC_EV_BLOCK
292 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 ,
293 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N ,
294 __PMC_EVENTS()
295 };
296
297 /*
298 * PMC SYSCALL INTERFACE
299 */
300
301 /*
302 * "PMC_OPS" -- these are the commands recognized by the kernel
303 * module, and are used when performing a system call from userland.
304 */
305 #define __PMC_OPS() \
306 __PMC_OP(CONFIGURELOG, "Set log file") \
307 __PMC_OP(FLUSHLOG, "Flush log file") \
308 __PMC_OP(GETCPUINFO, "Get system CPU information") \
309 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \
310 __PMC_OP(GETMODULEVERSION, "Get module version") \
311 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \
312 __PMC_OP(PMCADMIN, "Set PMC state") \
313 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \
314 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \
315 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \
316 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \
317 __PMC_OP(PMCRELEASE, "Release a PMC") \
318 __PMC_OP(PMCRW, "Read/Set a PMC") \
319 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \
320 __PMC_OP(PMCSTART, "Start a PMC") \
321 __PMC_OP(PMCSTOP, "Stop a PMC") \
322 __PMC_OP(WRITELOG, "Write a cookie to the log file") \
323 __PMC_OP(CLOSELOG, "Close log file") \
324 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list")
325
326
327 enum pmc_ops {
328 #undef __PMC_OP
329 #define __PMC_OP(N, D) PMC_OP_##N,
330 __PMC_OPS()
331 };
332
333
334 /*
335 * Flags used in operations on PMCs.
336 */
337
338 #define PMC_F_FORCE 0x00000001 /*OP ADMIN force operation */
339 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */
340 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */
341 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */
342 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */
343 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */
344 #define PMC_F_KGMON 0x00000040 /*OP ALLOCATE kgmon(8) profiling */
345 /* V2 API */
346 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */
347
348 /* internal flags */
349 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/
350 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */
351 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */
352
353 #define PMC_CALLCHAIN_DEPTH_MAX 128
354
355 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/
356
357 /*
358 * Cookies used to denote allocated PMCs, and the values of PMCs.
359 */
360
361 typedef uint32_t pmc_id_t;
362 typedef uint64_t pmc_value_t;
363
364 #define PMC_ID_INVALID (~ (pmc_id_t) 0)
365
366 /*
367 * PMC IDs have the following format:
368 *
369 * +--------+----------+-----------+-----------+
370 * | CPU | PMC MODE | PMC CLASS | ROW INDEX |
371 * +--------+----------+-----------+-----------+
372 *
373 * where each field is 8 bits wide. Field 'CPU' is set to the
374 * requested CPU for system-wide PMCs or PMC_CPU_ANY for process-mode
375 * PMCs. Field 'PMC MODE' is the allocated PMC mode. Field 'PMC
376 * CLASS' is the class of the PMC. Field 'ROW INDEX' is the row index
377 * for the PMC.
378 *
379 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total
380 * number of hardware PMCs on this cpu.
381 */
382
383
384 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF)
385 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8)
386 #define PMC_ID_TO_MODE(ID) (((ID) & 0xFF0000) >> 16)
387 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFF000000) >> 24)
388 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \
389 ((((CPU) & 0xFF) << 24) | (((MODE) & 0xFF) << 16) | \
390 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF))
391
392 /*
393 * Data structures for system calls supported by the pmc driver.
394 */
395
396 /*
397 * OP PMCALLOCATE
398 *
399 * Allocate a PMC on the named CPU.
400 */
401
402 #define PMC_CPU_ANY ~0
403
404 struct pmc_op_pmcallocate {
405 uint32_t pm_caps; /* PMC_CAP_* */
406 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */
407 enum pmc_class pm_class; /* class of PMC desired */
408 enum pmc_event pm_ev; /* [enum pmc_event] desired */
409 uint32_t pm_flags; /* additional modifiers PMC_F_* */
410 enum pmc_mode pm_mode; /* desired mode */
411 pmc_id_t pm_pmcid; /* [return] process pmc id */
412
413 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */
414 };
415
416 /*
417 * OP PMCADMIN
418 *
419 * Set the administrative state (i.e., whether enabled or disabled) of
420 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an
421 * absolute PMC number and need not have been first allocated by the
422 * calling process.
423 */
424
425 struct pmc_op_pmcadmin {
426 int pm_cpu; /* CPU# */
427 uint32_t pm_flags; /* flags */
428 int pm_pmc; /* PMC# */
429 enum pmc_state pm_state; /* desired state */
430 };
431
432 /*
433 * OP PMCATTACH / OP PMCDETACH
434 *
435 * Attach/detach a PMC and a process.
436 */
437
438 struct pmc_op_pmcattach {
439 pmc_id_t pm_pmc; /* PMC to attach to */
440 pid_t pm_pid; /* target process */
441 };
442
443 /*
444 * OP PMCSETCOUNT
445 *
446 * Set the sampling rate (i.e., the reload count) for statistical counters.
447 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE.
448 */
449
450 struct pmc_op_pmcsetcount {
451 pmc_value_t pm_count; /* initial/sample count */
452 pmc_id_t pm_pmcid; /* PMC id to set */
453 };
454
455
456 /*
457 * OP PMCRW
458 *
459 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs
460 * to have been previously allocated using PMCALLOCATE.
461 */
462
463
464 struct pmc_op_pmcrw {
465 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/
466 pmc_id_t pm_pmcid; /* pmc id */
467 pmc_value_t pm_value; /* new&returned value */
468 };
469
470
471 /*
472 * OP GETPMCINFO
473 *
474 * retrieve PMC state for a named CPU. The caller is expected to
475 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return
476 * values.
477 */
478
479 struct pmc_info {
480 char pm_name[PMC_NAME_MAX]; /* pmc name */
481 enum pmc_class pm_class; /* enum pmc_class */
482 int pm_enabled; /* whether enabled */
483 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */
484 pid_t pm_ownerpid; /* owner, or -1 */
485 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */
486 enum pmc_event pm_event; /* current event */
487 uint32_t pm_flags; /* current flags */
488 pmc_value_t pm_reloadcount; /* sampling counters only */
489 };
490
491 struct pmc_op_getpmcinfo {
492 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */
493 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */
494 };
495
496
497 /*
498 * OP GETCPUINFO
499 *
500 * Retrieve system CPU information.
501 */
502
503
504 struct pmc_classinfo {
505 enum pmc_class pm_class; /* class id */
506 uint32_t pm_caps; /* counter capabilities */
507 uint32_t pm_width; /* width of the PMC */
508 uint32_t pm_num; /* number of PMCs in class */
509 };
510
511 struct pmc_op_getcpuinfo {
512 enum pmc_cputype pm_cputype; /* what kind of CPU */
513 uint32_t pm_ncpu; /* max CPU number */
514 uint32_t pm_npmc; /* #PMCs per CPU */
515 uint32_t pm_nclass; /* #classes of PMCs */
516 struct pmc_classinfo pm_classes[PMC_CLASS_MAX];
517 };
518
519 /*
520 * OP CONFIGURELOG
521 *
522 * Configure a log file for writing system-wide statistics to.
523 */
524
525 struct pmc_op_configurelog {
526 int pm_flags;
527 int pm_logfd; /* logfile fd (or -1) */
528 };
529
530 /*
531 * OP GETDRIVERSTATS
532 *
533 * Retrieve pmc(4) driver-wide statistics.
534 */
535
536 struct pmc_op_getdriverstats {
537 unsigned int pm_intr_ignored; /* #interrupts ignored */
538 unsigned int pm_intr_processed; /* #interrupts processed */
539 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */
540 unsigned int pm_syscalls; /* #syscalls */
541 unsigned int pm_syscall_errors; /* #syscalls with errors */
542 unsigned int pm_buffer_requests; /* #buffer requests */
543 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */
544 unsigned int pm_log_sweeps; /* #sample buffer processing
545 passes */
546 };
547
548 /*
549 * OP RELEASE / OP START / OP STOP
550 *
551 * Simple operations on a PMC id.
552 */
553
554 struct pmc_op_simple {
555 pmc_id_t pm_pmcid;
556 };
557
558 /*
559 * OP WRITELOG
560 *
561 * Flush the current log buffer and write 4 bytes of user data to it.
562 */
563
564 struct pmc_op_writelog {
565 uint32_t pm_userdata;
566 };
567
568 /*
569 * OP GETMSR
570 *
571 * Retrieve the machine specific address assoicated with the allocated
572 * PMC. This number can be used subsequently with a read-performance-counter
573 * instruction.
574 */
575
576 struct pmc_op_getmsr {
577 uint32_t pm_msr; /* machine specific address */
578 pmc_id_t pm_pmcid; /* allocated pmc id */
579 };
580
581 /*
582 * OP GETDYNEVENTINFO
583 *
584 * Retrieve a PMC dynamic class events list.
585 */
586
587 struct pmc_dyn_event_descr {
588 char pm_ev_name[PMC_NAME_MAX];
589 enum pmc_event pm_ev_code;
590 };
591
592 struct pmc_op_getdyneventinfo {
593 enum pmc_class pm_class;
594 unsigned int pm_nevent;
595 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT];
596 };
597
598 #ifdef _KERNEL
599
600 #include <sys/malloc.h>
601 #include <sys/sysctl.h>
602 #include <sys/_cpuset.h>
603
604 #include <machine/frame.h>
605
606 #define PMC_HASH_SIZE 1024
607 #define PMC_MTXPOOL_SIZE 2048
608 #define PMC_LOG_BUFFER_SIZE 4
609 #define PMC_NLOGBUFFERS 1024
610 #define PMC_NSAMPLES 1024
611 #define PMC_CALLCHAIN_DEPTH 32
612
613 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "."
614
615 /*
616 * Locking keys
617 *
618 * (b) - pmc_bufferlist_mtx (spin lock)
619 * (k) - pmc_kthread_mtx (sleep lock)
620 * (o) - po->po_mtx (spin lock)
621 */
622
623 /*
624 * PMC commands
625 */
626
627 struct pmc_syscall_args {
628 register_t pmop_code; /* one of PMC_OP_* */
629 void *pmop_data; /* syscall parameter */
630 };
631
632 /*
633 * Interface to processor specific s1tuff
634 */
635
636 /*
637 * struct pmc_descr
638 *
639 * Machine independent (i.e., the common parts) of a human readable
640 * PMC description.
641 */
642
643 struct pmc_descr {
644 char pd_name[PMC_NAME_MAX]; /* name */
645 uint32_t pd_caps; /* capabilities */
646 enum pmc_class pd_class; /* class of the PMC */
647 uint32_t pd_width; /* width in bits */
648 };
649
650 /*
651 * struct pmc_target
652 *
653 * This structure records all the target processes associated with a
654 * PMC.
655 */
656
657 struct pmc_target {
658 LIST_ENTRY(pmc_target) pt_next;
659 struct pmc_process *pt_process; /* target descriptor */
660 };
661
662 /*
663 * struct pmc
664 *
665 * Describes each allocated PMC.
666 *
667 * Each PMC has precisely one owner, namely the process that allocated
668 * the PMC.
669 *
670 * A PMC may be attached to multiple target processes. The
671 * 'pm_targets' field links all the target processes being monitored
672 * by this PMC.
673 *
674 * The 'pm_savedvalue' field is protected by a mutex.
675 *
676 * On a multi-cpu machine, multiple target threads associated with a
677 * process-virtual PMC could be concurrently executing on different
678 * CPUs. The 'pm_runcount' field is atomically incremented every time
679 * the PMC gets scheduled on a CPU and atomically decremented when it
680 * get descheduled. Deletion of a PMC is only permitted when this
681 * field is ''.
682 *
683 */
684
685 struct pmc {
686 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */
687 LIST_ENTRY(pmc) pm_next; /* owner's list */
688
689 /*
690 * System-wide PMCs are allocated on a CPU and are not moved
691 * around. For system-wide PMCs we record the CPU the PMC was
692 * allocated on in the 'CPU' field of the pmc ID.
693 *
694 * Virtual PMCs run on whichever CPU is currently executing
695 * their targets' threads. For these PMCs we need to save
696 * their current PMC counter values when they are taken off
697 * CPU.
698 */
699
700 union {
701 pmc_value_t pm_savedvalue; /* Virtual PMCS */
702 } pm_gv;
703
704 /*
705 * For sampling mode PMCs, we keep track of the PMC's "reload
706 * count", which is the counter value to be loaded in when
707 * arming the PMC for the next counting session. For counting
708 * modes on PMCs that are read-only (e.g., the x86 TSC), we
709 * keep track of the initial value at the start of
710 * counting-mode operation.
711 */
712
713 union {
714 pmc_value_t pm_reloadcount; /* sampling PMC modes */
715 pmc_value_t pm_initial; /* counting PMC modes */
716 } pm_sc;
717
718 volatile cpuset_t pm_stalled; /* marks stalled sampling PMCs */
719 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */
720 uint32_t pm_caps; /* PMC capabilities */
721 enum pmc_event pm_event; /* event being measured */
722 uint32_t pm_flags; /* additional flags PMC_F_... */
723 struct pmc_owner *pm_owner; /* owner thread state */
724 int pm_runcount; /* #cpus currently on */
725 enum pmc_state pm_state; /* current PMC state */
726
727 /*
728 * The PMC ID field encodes the row-index for the PMC, its
729 * mode, class and the CPU# associated with the PMC.
730 */
731
732 pmc_id_t pm_id; /* allocated PMC id */
733
734 /* md extensions */
735 union pmc_md_pmc pm_md;
736 };
737
738 /*
739 * Accessor macros for 'struct pmc'
740 */
741
742 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id)
743 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id)
744 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id)
745 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id)
746
747
748 /*
749 * struct pmc_process
750 *
751 * Record a 'target' process being profiled.
752 *
753 * The target process being profiled could be different from the owner
754 * process which allocated the PMCs. Each target process descriptor
755 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a
756 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]'
757 * array. The size of this structure is thus PMC architecture
758 * dependent.
759 *
760 */
761
762 struct pmc_targetstate {
763 struct pmc *pp_pmc; /* target PMC */
764 pmc_value_t pp_pmcval; /* per-process value */
765 };
766
767 struct pmc_process {
768 LIST_ENTRY(pmc_process) pp_next; /* hash chain */
769 int pp_refcnt; /* reference count */
770 uint32_t pp_flags; /* flags PMC_PP_* */
771 struct proc *pp_proc; /* target thread */
772 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */
773 };
774
775 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001
776
777 /*
778 * struct pmc_owner
779 *
780 * We associate a PMC with an 'owner' process.
781 *
782 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its
783 * lifetime, where NCPUS is the numbers of CPUS in the system and
784 * NHWPMC is the number of hardware PMCs per CPU. These are
785 * maintained in the list headed by the 'po_pmcs' to save on space.
786 *
787 */
788
789 struct pmc_owner {
790 LIST_ENTRY(pmc_owner) po_next; /* hash chain */
791 LIST_ENTRY(pmc_owner) po_ssnext; /* list of SS PMC owners */
792 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */
793 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */
794 struct mtx po_mtx; /* spin lock for (o) */
795 struct proc *po_owner; /* owner proc */
796 uint32_t po_flags; /* (k) flags PMC_PO_* */
797 struct proc *po_kthread; /* (k) helper kthread */
798 struct pmclog_buffer *po_curbuf; /* current log buffer */
799 struct file *po_file; /* file reference */
800 int po_error; /* recorded error */
801 short po_sscount; /* # SS PMCs owned */
802 short po_logprocmaps; /* global mappings done */
803 };
804
805 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */
806 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */
807 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020
808
809 /*
810 * struct pmc_hw -- describe the state of the PMC hardware
811 *
812 * When in use, a HW PMC is associated with one allocated 'struct pmc'
813 * pointed to by field 'phw_pmc'. When inactive, this field is NULL.
814 *
815 * On an SMP box, one or more HW PMC's in process virtual mode with
816 * the same 'phw_pmc' could be executing on different CPUs. In order
817 * to handle this case correctly, we need to ensure that only
818 * incremental counts get added to the saved value in the associated
819 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC
820 * value at the time the hardware is started during this context
821 * switch (i.e., the difference between the new (hardware) count and
822 * the saved count is atomically added to the count field in 'struct
823 * pmc' at context switch time).
824 *
825 */
826
827 struct pmc_hw {
828 uint32_t phw_state; /* see PHW_* macros below */
829 struct pmc *phw_pmc; /* current thread PMC */
830 };
831
832 #define PMC_PHW_RI_MASK 0x000000FF
833 #define PMC_PHW_CPU_SHIFT 8
834 #define PMC_PHW_CPU_MASK 0x0000FF00
835 #define PMC_PHW_FLAGS_SHIFT 16
836 #define PMC_PHW_FLAGS_MASK 0xFFFF0000
837
838 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK)
839 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK)
840 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \
841 PMC_PHW_CPU_MASK)
842 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \
843 PMC_PHW_CPU_SHIFT)
844 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \
845 PMC_PHW_FLAGS_MASK)
846 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \
847 PMC_PHW_FLAGS_SHIFT)
848 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01))
849 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02))
850
851 /*
852 * struct pmc_sample
853 *
854 * Space for N (tunable) PC samples and associated control data.
855 */
856
857 struct pmc_sample {
858 uint16_t ps_nsamples; /* callchain depth */
859 uint8_t ps_cpu; /* cpu number */
860 uint8_t ps_flags; /* other flags */
861 pid_t ps_pid; /* process PID or -1 */
862 struct thread *ps_td; /* which thread */
863 struct pmc *ps_pmc; /* interrupting PMC */
864 uintptr_t *ps_pc; /* (const) callchain start */
865 };
866
867 #define PMC_SAMPLE_FREE ((uint16_t) 0)
868 #define PMC_SAMPLE_INUSE ((uint16_t) 0xFFFF)
869
870 struct pmc_samplebuffer {
871 struct pmc_sample * volatile ps_read; /* read pointer */
872 struct pmc_sample * volatile ps_write; /* write pointer */
873 uintptr_t *ps_callchains; /* all saved call chains */
874 struct pmc_sample *ps_fence; /* one beyond ps_samples[] */
875 struct pmc_sample ps_samples[]; /* array of sample entries */
876 };
877
878
879 /*
880 * struct pmc_cpustate
881 *
882 * A CPU is modelled as a collection of HW PMCs with space for additional
883 * flags.
884 */
885
886 struct pmc_cpu {
887 uint32_t pc_state; /* physical cpu number + flags */
888 struct pmc_samplebuffer *pc_sb[2]; /* space for samples */
889 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */
890 };
891
892 #define PMC_PCPU_CPU_MASK 0x000000FF
893 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00
894 #define PMC_PCPU_FLAGS_SHIFT 8
895 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK)
896 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT)
897 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK)
898 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK)
899 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1))
900
901 /*
902 * struct pmc_binding
903 *
904 * CPU binding information.
905 */
906
907 struct pmc_binding {
908 int pb_bound; /* is bound? */
909 int pb_cpu; /* if so, to which CPU */
910 };
911
912
913 struct pmc_mdep;
914
915 /*
916 * struct pmc_classdep
917 *
918 * PMC class-dependent operations.
919 */
920 struct pmc_classdep {
921 uint32_t pcd_caps; /* class capabilities */
922 enum pmc_class pcd_class; /* class id */
923 int pcd_num; /* number of PMCs */
924 int pcd_ri; /* row index of the first PMC in class */
925 int pcd_width; /* width of the PMC */
926
927 /* configuring/reading/writing the hardware PMCs */
928 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm);
929 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm);
930 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value);
931 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value);
932
933 /* pmc allocation/release */
934 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t,
935 const struct pmc_op_pmcallocate *_a);
936 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm);
937
938 /* starting and stopping PMCs */
939 int (*pcd_start_pmc)(int _cpu, int _ri);
940 int (*pcd_stop_pmc)(int _cpu, int _ri);
941
942 /* description */
943 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi,
944 struct pmc **_ppmc);
945
946 /* class-dependent initialization & finalization */
947 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
948 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
949
950 /* machine-specific interface */
951 int (*pcd_get_msr)(int _ri, uint32_t *_msr);
952 };
953
954 /*
955 * struct pmc_mdep
956 *
957 * Machine dependent bits needed per CPU type.
958 */
959
960 struct pmc_mdep {
961 uint32_t pmd_cputype; /* from enum pmc_cputype */
962 uint32_t pmd_npmc; /* number of PMCs per CPU */
963 uint32_t pmd_nclass; /* number of PMC classes present */
964
965 /*
966 * Machine dependent methods.
967 */
968
969 /* per-cpu initialization and finalization */
970 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
971 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
972
973 /* thread context switch in/out */
974 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp);
975 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp);
976
977 /* handle a PMC interrupt */
978 int (*pmd_intr)(int _cpu, struct trapframe *_tf);
979
980 /*
981 * PMC class dependent information.
982 */
983 struct pmc_classdep pmd_classdep[];
984 };
985
986 /*
987 * Per-CPU state. This is an array of 'mp_ncpu' pointers
988 * to struct pmc_cpu descriptors.
989 */
990
991 extern struct pmc_cpu **pmc_pcpu;
992
993 /* driver statistics */
994 extern struct pmc_op_getdriverstats pmc_stats;
995
996 #if defined(HWPMC_DEBUG)
997 #include <sys/ktr.h>
998
999 /* debug flags, major flag groups */
1000 struct pmc_debugflags {
1001 int pdb_CPU;
1002 int pdb_CSW;
1003 int pdb_LOG;
1004 int pdb_MDP;
1005 int pdb_MOD;
1006 int pdb_OWN;
1007 int pdb_PMC;
1008 int pdb_PRC;
1009 int pdb_SAM;
1010 };
1011
1012 extern struct pmc_debugflags pmc_debugflags;
1013
1014 #define KTR_PMC KTR_SUBSYS
1015
1016 #define PMC_DEBUG_STRSIZE 128
1017 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0 }
1018
1019 #define PMCDBG0(M, N, L, F) do { \
1020 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1021 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \
1022 } while (0)
1023 #define PMCDBG1(M, N, L, F, p1) do { \
1024 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1025 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \
1026 } while (0)
1027 #define PMCDBG2(M, N, L, F, p1, p2) do { \
1028 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1029 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \
1030 } while (0)
1031 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \
1032 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1033 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \
1034 } while (0)
1035 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \
1036 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1037 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\
1038 } while (0)
1039 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \
1040 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1041 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \
1042 p5); \
1043 } while (0)
1044 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \
1045 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1046 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \
1047 p5, p6); \
1048 } while (0)
1049
1050 /* Major numbers */
1051 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */
1052 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */
1053 #define PMC_DEBUG_MAJ_LOG 2 /* logging */
1054 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */
1055 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */
1056 #define PMC_DEBUG_MAJ_OWN 5 /* owner */
1057 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */
1058 #define PMC_DEBUG_MAJ_PRC 7 /* processes */
1059 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */
1060
1061 /* Minor numbers */
1062
1063 /* Common (8 bits) */
1064 #define PMC_DEBUG_MIN_ALL 0 /* allocation */
1065 #define PMC_DEBUG_MIN_REL 1 /* release */
1066 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */
1067 #define PMC_DEBUG_MIN_INI 3 /* init */
1068 #define PMC_DEBUG_MIN_FND 4 /* find */
1069
1070 /* MODULE */
1071 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */
1072 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */
1073
1074 /* OWN */
1075 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */
1076 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */
1077
1078 /* PROCESSES */
1079 #define PMC_DEBUG_MIN_TLK 8 /* link target */
1080 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */
1081 #define PMC_DEBUG_MIN_EXT 10 /* process exit */
1082 #define PMC_DEBUG_MIN_EXC 11 /* process exec */
1083 #define PMC_DEBUG_MIN_FRK 12 /* process fork */
1084 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */
1085 #define PMC_DEBUG_MIN_SIG 14 /* signalling */
1086
1087 /* CONTEXT SWITCHES */
1088 #define PMC_DEBUG_MIN_SWI 8 /* switch in */
1089 #define PMC_DEBUG_MIN_SWO 9 /* switch out */
1090
1091 /* PMC */
1092 #define PMC_DEBUG_MIN_REG 8 /* pmc register */
1093 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */
1094
1095 /* MACHINE DEPENDENT LAYER */
1096 #define PMC_DEBUG_MIN_REA 8 /* read */
1097 #define PMC_DEBUG_MIN_WRI 9 /* write */
1098 #define PMC_DEBUG_MIN_CFG 10 /* config */
1099 #define PMC_DEBUG_MIN_STA 11 /* start */
1100 #define PMC_DEBUG_MIN_STO 12 /* stop */
1101 #define PMC_DEBUG_MIN_INT 13 /* interrupts */
1102
1103 /* CPU */
1104 #define PMC_DEBUG_MIN_BND 8 /* bind */
1105 #define PMC_DEBUG_MIN_SEL 9 /* select */
1106
1107 /* LOG */
1108 #define PMC_DEBUG_MIN_GTB 8 /* get buf */
1109 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */
1110 #define PMC_DEBUG_MIN_FLS 10 /* flush */
1111 #define PMC_DEBUG_MIN_SAM 11 /* sample */
1112 #define PMC_DEBUG_MIN_CLO 12 /* close */
1113
1114 #else
1115 #define PMCDBG0(M, N, L, F) /* nothing */
1116 #define PMCDBG1(M, N, L, F, p1)
1117 #define PMCDBG2(M, N, L, F, p1, p2)
1118 #define PMCDBG3(M, N, L, F, p1, p2, p3)
1119 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4)
1120 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5)
1121 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6)
1122 #endif
1123
1124 /* declare a dedicated memory pool */
1125 MALLOC_DECLARE(M_PMC);
1126
1127 /*
1128 * Functions
1129 */
1130
1131 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */
1132 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */
1133 int pmc_getrowdisp(int _ri);
1134 int pmc_process_interrupt(int _cpu, int _soft, struct pmc *_pm,
1135 struct trapframe *_tf, int _inuserspace);
1136 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples,
1137 struct trapframe *_tf);
1138 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples,
1139 struct trapframe *_tf);
1140 struct pmc_mdep *pmc_mdep_alloc(int nclasses);
1141 void pmc_mdep_free(struct pmc_mdep *md);
1142 #endif /* _KERNEL */
1143 #endif /* _SYS_PMC_H_ */
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