FreeBSD/Linux Kernel Cross Reference
sys/sys/pmc.h
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2003-2008, Joseph Koshy
5 * Copyright (c) 2007 The FreeBSD Foundation
6 * All rights reserved.
7 *
8 * Portions of this software were developed by A. Joseph Koshy under
9 * sponsorship from the FreeBSD Foundation and Google, Inc.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34
35 #ifndef _SYS_PMC_H_
36 #define _SYS_PMC_H_
37
38 #include <dev/hwpmc/pmc_events.h>
39 #include <sys/proc.h>
40 #include <sys/counter.h>
41 #include <machine/pmc_mdep.h>
42 #include <machine/profile.h>
43 #ifdef _KERNEL
44 #include <sys/epoch.h>
45 #include <ck_queue.h>
46 #endif
47
48 #define PMC_MODULE_NAME "hwpmc"
49 #define PMC_NAME_MAX 64 /* HW counter name size */
50 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */
51
52 /*
53 * Kernel<->userland API version number [MMmmpppp]
54 *
55 * Major numbers are to be incremented when an incompatible change to
56 * the ABI occurs that older clients will not be able to handle.
57 *
58 * Minor numbers are incremented when a backwards compatible change
59 * occurs that allows older correct programs to run unchanged. For
60 * example, when support for a new PMC type is added.
61 *
62 * The patch version is incremented for every bug fix.
63 */
64 #define PMC_VERSION_MAJOR 0x09
65 #define PMC_VERSION_MINOR 0x03
66 #define PMC_VERSION_PATCH 0x0000
67
68 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \
69 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH)
70
71 #define PMC_CPUID_LEN 64
72 /* cpu model name for pmu lookup */
73 extern char pmc_cpuid[PMC_CPUID_LEN];
74
75 /*
76 * Kinds of CPUs known.
77 *
78 * We keep track of CPU variants that need to be distinguished in
79 * some way for PMC operations. CPU names are grouped by manufacturer
80 * and numbered sparsely in order to minimize changes to the ABI involved
81 * when new CPUs are added.
82 */
83
84 #define __PMC_CPUS() \
85 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \
86 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \
87 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \
88 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \
89 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \
90 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \
91 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \
92 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \
93 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \
94 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \
95 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \
96 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \
97 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \
98 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \
99 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \
100 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \
101 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \
102 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \
103 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \
104 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \
105 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \
106 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \
107 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \
108 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \
109 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \
110 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \
111 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \
112 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \
113 __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \
114 __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \
115 __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \
116 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \
117 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \
118 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \
119 __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \
120 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \
121 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \
122 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \
123 __PMC_CPU(GENERIC, 0x400, "Generic") \
124 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \
125 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \
126 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \
127 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \
128 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \
129 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \
130 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \
131 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57")
132
133 enum pmc_cputype {
134 #undef __PMC_CPU
135 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V,
136 __PMC_CPUS()
137 };
138
139 #define PMC_CPU_FIRST PMC_CPU_AMD_K7
140 #define PMC_CPU_LAST PMC_CPU_GENERIC
141
142 /*
143 * Classes of PMCs
144 */
145
146 #define __PMC_CLASSES() \
147 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \
148 __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \
149 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \
150 __PMC_CLASS(P5, 0x03, "Intel Pentium counters") \
151 __PMC_CLASS(P6, 0x04, "Intel Pentium Pro counters") \
152 __PMC_CLASS(P4, 0x05, "Intel Pentium-IV counters") \
153 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \
154 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \
155 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \
156 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \
157 __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \
158 __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \
159 __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \
160 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \
161 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \
162 __PMC_CLASS(SOFT, 0x0F, "Software events") \
163 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \
164 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \
165 __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \
166 __PMC_CLASS(E500, 0x13, "Freescale e500 class")
167
168 enum pmc_class {
169 #undef __PMC_CLASS
170 #define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V,
171 __PMC_CLASSES()
172 };
173
174 #define PMC_CLASS_FIRST PMC_CLASS_TSC
175 #define PMC_CLASS_LAST PMC_CLASS_E500
176
177 /*
178 * A PMC can be in the following states:
179 *
180 * Hardware states:
181 * DISABLED -- administratively prohibited from being used.
182 * FREE -- HW available for use
183 * Software states:
184 * ALLOCATED -- allocated
185 * STOPPED -- allocated, but not counting events
186 * RUNNING -- allocated, and in operation; 'pm_runcount'
187 * holds the number of CPUs using this PMC at
188 * a given instant
189 * DELETED -- being destroyed
190 */
191
192 #define __PMC_HWSTATES() \
193 __PMC_STATE(DISABLED) \
194 __PMC_STATE(FREE)
195
196 #define __PMC_SWSTATES() \
197 __PMC_STATE(ALLOCATED) \
198 __PMC_STATE(STOPPED) \
199 __PMC_STATE(RUNNING) \
200 __PMC_STATE(DELETED)
201
202 #define __PMC_STATES() \
203 __PMC_HWSTATES() \
204 __PMC_SWSTATES()
205
206 enum pmc_state {
207 #undef __PMC_STATE
208 #define __PMC_STATE(S) PMC_STATE_##S,
209 __PMC_STATES()
210 __PMC_STATE(MAX)
211 };
212
213 #define PMC_STATE_FIRST PMC_STATE_DISABLED
214 #define PMC_STATE_LAST PMC_STATE_DELETED
215
216 /*
217 * An allocated PMC may used as a 'global' counter or as a
218 * 'thread-private' one. Each such mode of use can be in either
219 * statistical sampling mode or in counting mode. Thus a PMC in use
220 *
221 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling
222 * SC i.e., SYSTEM COUNTER -- system-wide counting mode
223 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling
224 * TC i.e., THREAD COUNTER -- thread virtual, counting mode
225 *
226 * Statistical profiling modes rely on the PMC periodically delivering
227 * a interrupt to the CPU (when the configured number of events have
228 * been measured), so the PMC must have the ability to generate
229 * interrupts.
230 *
231 * In counting modes, the PMC counts its configured events, with the
232 * value of the PMC being read whenever needed by its owner process.
233 *
234 * The thread specific modes "virtualize" the PMCs -- the PMCs appear
235 * to be thread private and count events only when the profiled thread
236 * actually executes on the CPU.
237 *
238 * The system-wide "global" modes keep the PMCs running all the time
239 * and are used to measure the behaviour of the whole system.
240 */
241
242 #define __PMC_MODES() \
243 __PMC_MODE(SS, 0) \
244 __PMC_MODE(SC, 1) \
245 __PMC_MODE(TS, 2) \
246 __PMC_MODE(TC, 3)
247
248 enum pmc_mode {
249 #undef __PMC_MODE
250 #define __PMC_MODE(M,N) PMC_MODE_##M = N,
251 __PMC_MODES()
252 };
253
254 #define PMC_MODE_FIRST PMC_MODE_SS
255 #define PMC_MODE_LAST PMC_MODE_TC
256
257 #define PMC_IS_COUNTING_MODE(mode) \
258 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC)
259 #define PMC_IS_SYSTEM_MODE(mode) \
260 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC)
261 #define PMC_IS_SAMPLING_MODE(mode) \
262 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS)
263 #define PMC_IS_VIRTUAL_MODE(mode) \
264 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC)
265
266 /*
267 * PMC row disposition
268 */
269
270 #define __PMC_DISPOSITIONS(N) \
271 __PMC_DISP(STANDALONE) /* global/disabled counters */ \
272 __PMC_DISP(FREE) /* free/available */ \
273 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \
274 __PMC_DISP(UNKNOWN) /* sentinel */
275
276 enum pmc_disp {
277 #undef __PMC_DISP
278 #define __PMC_DISP(D) PMC_DISP_##D ,
279 __PMC_DISPOSITIONS()
280 };
281
282 #define PMC_DISP_FIRST PMC_DISP_STANDALONE
283 #define PMC_DISP_LAST PMC_DISP_THREAD
284
285 /*
286 * Counter capabilities
287 *
288 * __PMC_CAPS(NAME, VALUE, DESCRIPTION)
289 */
290
291 #define __PMC_CAPS() \
292 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \
293 __PMC_CAP(USER, 1, "count user-mode events") \
294 __PMC_CAP(SYSTEM, 2, "count system-mode events") \
295 __PMC_CAP(EDGE, 3, "do edge detection of events") \
296 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \
297 __PMC_CAP(READ, 5, "read PMC counter") \
298 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \
299 __PMC_CAP(INVERT, 7, "invert comparison sense") \
300 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \
301 __PMC_CAP(PRECISE, 9, "perform precise sampling") \
302 __PMC_CAP(TAGGING, 10, "tag upstream events") \
303 __PMC_CAP(CASCADE, 11, "cascade counters")
304
305 enum pmc_caps
306 {
307 #undef __PMC_CAP
308 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) ,
309 __PMC_CAPS()
310 };
311
312 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT
313 #define PMC_CAP_LAST PMC_CAP_CASCADE
314
315 /*
316 * PMC Event Numbers
317 *
318 * These are generated from the definitions in "dev/hwpmc/pmc_events.h".
319 */
320
321 enum pmc_event {
322 #undef __PMC_EV
323 #undef __PMC_EV_BLOCK
324 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 ,
325 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N ,
326 __PMC_EVENTS()
327 };
328
329 /*
330 * PMC SYSCALL INTERFACE
331 */
332
333 /*
334 * "PMC_OPS" -- these are the commands recognized by the kernel
335 * module, and are used when performing a system call from userland.
336 */
337 #define __PMC_OPS() \
338 __PMC_OP(CONFIGURELOG, "Set log file") \
339 __PMC_OP(FLUSHLOG, "Flush log file") \
340 __PMC_OP(GETCPUINFO, "Get system CPU information") \
341 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \
342 __PMC_OP(GETMODULEVERSION, "Get module version") \
343 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \
344 __PMC_OP(PMCADMIN, "Set PMC state") \
345 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \
346 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \
347 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \
348 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \
349 __PMC_OP(PMCRELEASE, "Release a PMC") \
350 __PMC_OP(PMCRW, "Read/Set a PMC") \
351 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \
352 __PMC_OP(PMCSTART, "Start a PMC") \
353 __PMC_OP(PMCSTOP, "Stop a PMC") \
354 __PMC_OP(WRITELOG, "Write a cookie to the log file") \
355 __PMC_OP(CLOSELOG, "Close log file") \
356 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list")
357
358
359 enum pmc_ops {
360 #undef __PMC_OP
361 #define __PMC_OP(N, D) PMC_OP_##N,
362 __PMC_OPS()
363 };
364
365
366 /*
367 * Flags used in operations on PMCs.
368 */
369
370 #define PMC_F_UNUSED1 0x00000001 /* unused */
371 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */
372 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */
373 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */
374 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */
375 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */
376
377 /* V2 API */
378 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */
379 #define PMC_F_USERCALLCHAIN 0x00000100 /*OP ALLOCATE use userspace stack */
380
381 /* internal flags */
382 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/
383 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */
384 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */
385
386 #define PMC_CALLCHAIN_DEPTH_MAX 512
387
388 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/
389
390 /*
391 * Cookies used to denote allocated PMCs, and the values of PMCs.
392 */
393
394 typedef uint32_t pmc_id_t;
395 typedef uint64_t pmc_value_t;
396
397 #define PMC_ID_INVALID (~ (pmc_id_t) 0)
398
399 /*
400 * PMC IDs have the following format:
401 *
402 * +-----------------------+-------+-----------+
403 * | CPU | PMC MODE | CLASS | ROW INDEX |
404 * +-----------------------+-------+-----------+
405 *
406 * where CPU is 12 bits, MODE 8, CLASS 4, and ROW INDEX 8 Field 'CPU'
407 * is set to the requested CPU for system-wide PMCs or PMC_CPU_ANY for
408 * process-mode PMCs. Field 'PMC MODE' is the allocated PMC mode.
409 * Field 'PMC CLASS' is the class of the PMC. Field 'ROW INDEX' is the
410 * row index for the PMC.
411 *
412 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total
413 * number of hardware PMCs on this cpu.
414 */
415
416
417 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF)
418 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xF00) >> 8)
419 #define PMC_ID_TO_MODE(ID) (((ID) & 0xFF000) >> 12)
420 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFFF00000) >> 20)
421 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \
422 ((((CPU) & 0xFFF) << 20) | (((MODE) & 0xFF) << 12) | \
423 (((CLASS) & 0xF) << 8) | ((ROWINDEX) & 0xFF))
424
425 /*
426 * Data structures for system calls supported by the pmc driver.
427 */
428
429 /*
430 * OP PMCALLOCATE
431 *
432 * Allocate a PMC on the named CPU.
433 */
434
435 #define PMC_CPU_ANY ~0
436
437 struct pmc_op_pmcallocate {
438 uint32_t pm_caps; /* PMC_CAP_* */
439 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */
440 enum pmc_class pm_class; /* class of PMC desired */
441 enum pmc_event pm_ev; /* [enum pmc_event] desired */
442 uint32_t pm_flags; /* additional modifiers PMC_F_* */
443 enum pmc_mode pm_mode; /* desired mode */
444 pmc_id_t pm_pmcid; /* [return] process pmc id */
445 pmc_value_t pm_count; /* initial/sample count */
446
447 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */
448 };
449
450 /*
451 * OP PMCADMIN
452 *
453 * Set the administrative state (i.e., whether enabled or disabled) of
454 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an
455 * absolute PMC number and need not have been first allocated by the
456 * calling process.
457 */
458
459 struct pmc_op_pmcadmin {
460 int pm_cpu; /* CPU# */
461 uint32_t pm_flags; /* flags */
462 int pm_pmc; /* PMC# */
463 enum pmc_state pm_state; /* desired state */
464 };
465
466 /*
467 * OP PMCATTACH / OP PMCDETACH
468 *
469 * Attach/detach a PMC and a process.
470 */
471
472 struct pmc_op_pmcattach {
473 pmc_id_t pm_pmc; /* PMC to attach to */
474 pid_t pm_pid; /* target process */
475 };
476
477 /*
478 * OP PMCSETCOUNT
479 *
480 * Set the sampling rate (i.e., the reload count) for statistical counters.
481 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE.
482 */
483
484 struct pmc_op_pmcsetcount {
485 pmc_value_t pm_count; /* initial/sample count */
486 pmc_id_t pm_pmcid; /* PMC id to set */
487 };
488
489
490 /*
491 * OP PMCRW
492 *
493 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs
494 * to have been previously allocated using PMCALLOCATE.
495 */
496
497
498 struct pmc_op_pmcrw {
499 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/
500 pmc_id_t pm_pmcid; /* pmc id */
501 pmc_value_t pm_value; /* new&returned value */
502 };
503
504
505 /*
506 * OP GETPMCINFO
507 *
508 * retrieve PMC state for a named CPU. The caller is expected to
509 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return
510 * values.
511 */
512
513 struct pmc_info {
514 char pm_name[PMC_NAME_MAX]; /* pmc name */
515 enum pmc_class pm_class; /* enum pmc_class */
516 int pm_enabled; /* whether enabled */
517 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */
518 pid_t pm_ownerpid; /* owner, or -1 */
519 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */
520 enum pmc_event pm_event; /* current event */
521 uint32_t pm_flags; /* current flags */
522 pmc_value_t pm_reloadcount; /* sampling counters only */
523 };
524
525 struct pmc_op_getpmcinfo {
526 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */
527 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */
528 };
529
530
531 /*
532 * OP GETCPUINFO
533 *
534 * Retrieve system CPU information.
535 */
536
537
538 struct pmc_classinfo {
539 enum pmc_class pm_class; /* class id */
540 uint32_t pm_caps; /* counter capabilities */
541 uint32_t pm_width; /* width of the PMC */
542 uint32_t pm_num; /* number of PMCs in class */
543 };
544
545 struct pmc_op_getcpuinfo {
546 enum pmc_cputype pm_cputype; /* what kind of CPU */
547 uint32_t pm_ncpu; /* max CPU number */
548 uint32_t pm_npmc; /* #PMCs per CPU */
549 uint32_t pm_nclass; /* #classes of PMCs */
550 struct pmc_classinfo pm_classes[PMC_CLASS_MAX];
551 };
552
553 /*
554 * OP CONFIGURELOG
555 *
556 * Configure a log file for writing system-wide statistics to.
557 */
558
559 struct pmc_op_configurelog {
560 int pm_flags;
561 int pm_logfd; /* logfile fd (or -1) */
562 };
563
564 /*
565 * OP GETDRIVERSTATS
566 *
567 * Retrieve pmc(4) driver-wide statistics.
568 */
569 #ifdef _KERNEL
570 struct pmc_driverstats {
571 counter_u64_t pm_intr_ignored; /* #interrupts ignored */
572 counter_u64_t pm_intr_processed; /* #interrupts processed */
573 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */
574 counter_u64_t pm_syscalls; /* #syscalls */
575 counter_u64_t pm_syscall_errors; /* #syscalls with errors */
576 counter_u64_t pm_buffer_requests; /* #buffer requests */
577 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */
578 counter_u64_t pm_log_sweeps; /* #sample buffer processing
579 passes */
580 counter_u64_t pm_merges; /* merged k+u */
581 counter_u64_t pm_overwrites; /* UR overwrites */
582 };
583 #endif
584
585 struct pmc_op_getdriverstats {
586 unsigned int pm_intr_ignored; /* #interrupts ignored */
587 unsigned int pm_intr_processed; /* #interrupts processed */
588 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */
589 unsigned int pm_syscalls; /* #syscalls */
590 unsigned int pm_syscall_errors; /* #syscalls with errors */
591 unsigned int pm_buffer_requests; /* #buffer requests */
592 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */
593 unsigned int pm_log_sweeps; /* #sample buffer processing
594 passes */
595 };
596
597 /*
598 * OP RELEASE / OP START / OP STOP
599 *
600 * Simple operations on a PMC id.
601 */
602
603 struct pmc_op_simple {
604 pmc_id_t pm_pmcid;
605 };
606
607 /*
608 * OP WRITELOG
609 *
610 * Flush the current log buffer and write 4 bytes of user data to it.
611 */
612
613 struct pmc_op_writelog {
614 uint32_t pm_userdata;
615 };
616
617 /*
618 * OP GETMSR
619 *
620 * Retrieve the machine specific address associated with the allocated
621 * PMC. This number can be used subsequently with a read-performance-counter
622 * instruction.
623 */
624
625 struct pmc_op_getmsr {
626 uint32_t pm_msr; /* machine specific address */
627 pmc_id_t pm_pmcid; /* allocated pmc id */
628 };
629
630 /*
631 * OP GETDYNEVENTINFO
632 *
633 * Retrieve a PMC dynamic class events list.
634 */
635
636 struct pmc_dyn_event_descr {
637 char pm_ev_name[PMC_NAME_MAX];
638 enum pmc_event pm_ev_code;
639 };
640
641 struct pmc_op_getdyneventinfo {
642 enum pmc_class pm_class;
643 unsigned int pm_nevent;
644 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT];
645 };
646
647 #ifdef _KERNEL
648
649 #include <sys/malloc.h>
650 #include <sys/sysctl.h>
651 #include <sys/_cpuset.h>
652
653 #include <machine/frame.h>
654
655 #define PMC_HASH_SIZE 1024
656 #define PMC_MTXPOOL_SIZE 2048
657 #define PMC_LOG_BUFFER_SIZE 256
658 #define PMC_NLOGBUFFERS_PCPU 32
659 #define PMC_NSAMPLES 256
660 #define PMC_CALLCHAIN_DEPTH 128
661 #define PMC_THREADLIST_MAX 128
662
663 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "."
664
665 /*
666 * Locking keys
667 *
668 * (b) - pmc_bufferlist_mtx (spin lock)
669 * (k) - pmc_kthread_mtx (sleep lock)
670 * (o) - po->po_mtx (spin lock)
671 * (g) - global_epoch_preempt (epoch)
672 * (p) - pmc_sx (sx)
673 */
674
675 /*
676 * PMC commands
677 */
678
679 struct pmc_syscall_args {
680 register_t pmop_code; /* one of PMC_OP_* */
681 void *pmop_data; /* syscall parameter */
682 };
683
684 /*
685 * Interface to processor specific s1tuff
686 */
687
688 /*
689 * struct pmc_descr
690 *
691 * Machine independent (i.e., the common parts) of a human readable
692 * PMC description.
693 */
694
695 struct pmc_descr {
696 char pd_name[PMC_NAME_MAX]; /* name */
697 uint32_t pd_caps; /* capabilities */
698 enum pmc_class pd_class; /* class of the PMC */
699 uint32_t pd_width; /* width in bits */
700 };
701
702 /*
703 * struct pmc_target
704 *
705 * This structure records all the target processes associated with a
706 * PMC.
707 */
708
709 struct pmc_target {
710 LIST_ENTRY(pmc_target) pt_next;
711 struct pmc_process *pt_process; /* target descriptor */
712 };
713
714 /*
715 * struct pmc
716 *
717 * Describes each allocated PMC.
718 *
719 * Each PMC has precisely one owner, namely the process that allocated
720 * the PMC.
721 *
722 * A PMC may be attached to multiple target processes. The
723 * 'pm_targets' field links all the target processes being monitored
724 * by this PMC.
725 *
726 * The 'pm_savedvalue' field is protected by a mutex.
727 *
728 * On a multi-cpu machine, multiple target threads associated with a
729 * process-virtual PMC could be concurrently executing on different
730 * CPUs. The 'pm_runcount' field is atomically incremented every time
731 * the PMC gets scheduled on a CPU and atomically decremented when it
732 * get descheduled. Deletion of a PMC is only permitted when this
733 * field is ''.
734 *
735 */
736 struct pmc_pcpu_state {
737 uint8_t pps_stalled;
738 uint8_t pps_cpustate;
739 } __aligned(CACHE_LINE_SIZE);
740 struct pmc {
741 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */
742 LIST_ENTRY(pmc) pm_next; /* owner's list */
743
744 /*
745 * System-wide PMCs are allocated on a CPU and are not moved
746 * around. For system-wide PMCs we record the CPU the PMC was
747 * allocated on in the 'CPU' field of the pmc ID.
748 *
749 * Virtual PMCs run on whichever CPU is currently executing
750 * their targets' threads. For these PMCs we need to save
751 * their current PMC counter values when they are taken off
752 * CPU.
753 */
754
755 union {
756 pmc_value_t pm_savedvalue; /* Virtual PMCS */
757 } pm_gv;
758
759 /*
760 * For sampling mode PMCs, we keep track of the PMC's "reload
761 * count", which is the counter value to be loaded in when
762 * arming the PMC for the next counting session. For counting
763 * modes on PMCs that are read-only (e.g., the x86 TSC), we
764 * keep track of the initial value at the start of
765 * counting-mode operation.
766 */
767
768 union {
769 pmc_value_t pm_reloadcount; /* sampling PMC modes */
770 pmc_value_t pm_initial; /* counting PMC modes */
771 } pm_sc;
772
773 struct pmc_pcpu_state *pm_pcpu_state;
774 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */
775 uint32_t pm_caps; /* PMC capabilities */
776 enum pmc_event pm_event; /* event being measured */
777 uint32_t pm_flags; /* additional flags PMC_F_... */
778 struct pmc_owner *pm_owner; /* owner thread state */
779 counter_u64_t pm_runcount; /* #cpus currently on */
780 enum pmc_state pm_state; /* current PMC state */
781 uint32_t pm_overflowcnt; /* count overflow interrupts */
782
783 /*
784 * The PMC ID field encodes the row-index for the PMC, its
785 * mode, class and the CPU# associated with the PMC.
786 */
787
788 pmc_id_t pm_id; /* allocated PMC id */
789 enum pmc_class pm_class;
790
791 /* md extensions */
792 union pmc_md_pmc pm_md;
793 };
794
795 /*
796 * Accessor macros for 'struct pmc'
797 */
798
799 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id)
800 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id)
801 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id)
802 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id)
803
804 /*
805 * struct pmc_threadpmcstate
806 *
807 * Record per-PMC, per-thread state.
808 */
809 struct pmc_threadpmcstate {
810 pmc_value_t pt_pmcval; /* per-thread reload count */
811 };
812
813 /*
814 * struct pmc_thread
815 *
816 * Record a 'target' thread being profiled.
817 */
818 struct pmc_thread {
819 LIST_ENTRY(pmc_thread) pt_next; /* linked list */
820 struct thread *pt_td; /* target thread */
821 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */
822 };
823
824 /*
825 * struct pmc_process
826 *
827 * Record a 'target' process being profiled.
828 *
829 * The target process being profiled could be different from the owner
830 * process which allocated the PMCs. Each target process descriptor
831 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a
832 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]'
833 * array. The size of this structure is thus PMC architecture
834 * dependent.
835 *
836 */
837
838 struct pmc_targetstate {
839 struct pmc *pp_pmc; /* target PMC */
840 pmc_value_t pp_pmcval; /* per-process value */
841 };
842
843 struct pmc_process {
844 LIST_ENTRY(pmc_process) pp_next; /* hash chain */
845 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */
846 struct mtx *pp_tdslock; /* lock on pp_tds thread list */
847 int pp_refcnt; /* reference count */
848 uint32_t pp_flags; /* flags PMC_PP_* */
849 struct proc *pp_proc; /* target process */
850 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */
851 };
852
853 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001
854
855 /*
856 * struct pmc_owner
857 *
858 * We associate a PMC with an 'owner' process.
859 *
860 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its
861 * lifetime, where NCPUS is the numbers of CPUS in the system and
862 * NHWPMC is the number of hardware PMCs per CPU. These are
863 * maintained in the list headed by the 'po_pmcs' to save on space.
864 *
865 */
866
867 struct pmc_owner {
868 LIST_ENTRY(pmc_owner) po_next; /* hash chain */
869 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* (g/p) list of SS PMC owners */
870 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */
871 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */
872 struct mtx po_mtx; /* spin lock for (o) */
873 struct proc *po_owner; /* owner proc */
874 uint32_t po_flags; /* (k) flags PMC_PO_* */
875 struct proc *po_kthread; /* (k) helper kthread */
876 struct file *po_file; /* file reference */
877 int po_error; /* recorded error */
878 short po_sscount; /* # SS PMCs owned */
879 short po_logprocmaps; /* global mappings done */
880 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */
881 };
882
883 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */
884 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */
885 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020
886
887 /*
888 * struct pmc_hw -- describe the state of the PMC hardware
889 *
890 * When in use, a HW PMC is associated with one allocated 'struct pmc'
891 * pointed to by field 'phw_pmc'. When inactive, this field is NULL.
892 *
893 * On an SMP box, one or more HW PMC's in process virtual mode with
894 * the same 'phw_pmc' could be executing on different CPUs. In order
895 * to handle this case correctly, we need to ensure that only
896 * incremental counts get added to the saved value in the associated
897 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC
898 * value at the time the hardware is started during this context
899 * switch (i.e., the difference between the new (hardware) count and
900 * the saved count is atomically added to the count field in 'struct
901 * pmc' at context switch time).
902 *
903 */
904
905 struct pmc_hw {
906 uint32_t phw_state; /* see PHW_* macros below */
907 struct pmc *phw_pmc; /* current thread PMC */
908 };
909
910 #define PMC_PHW_RI_MASK 0x000000FF
911 #define PMC_PHW_CPU_SHIFT 8
912 #define PMC_PHW_CPU_MASK 0x0000FF00
913 #define PMC_PHW_FLAGS_SHIFT 16
914 #define PMC_PHW_FLAGS_MASK 0xFFFF0000
915
916 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK)
917 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK)
918 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \
919 PMC_PHW_CPU_MASK)
920 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \
921 PMC_PHW_CPU_SHIFT)
922 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \
923 PMC_PHW_FLAGS_MASK)
924 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \
925 PMC_PHW_FLAGS_SHIFT)
926 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01))
927 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02))
928
929 /*
930 * struct pmc_sample
931 *
932 * Space for N (tunable) PC samples and associated control data.
933 */
934
935 struct pmc_sample {
936 uint16_t ps_nsamples; /* callchain depth */
937 uint16_t ps_nsamples_actual;
938 uint16_t ps_cpu; /* cpu number */
939 uint16_t ps_flags; /* other flags */
940 lwpid_t ps_tid; /* thread id */
941 pid_t ps_pid; /* process PID or -1 */
942 int ps_ticks; /* ticks at sample time */
943 /* pad */
944 struct thread *ps_td; /* which thread */
945 struct pmc *ps_pmc; /* interrupting PMC */
946 uintptr_t *ps_pc; /* (const) callchain start */
947 uint64_t ps_tsc; /* tsc value */
948 };
949
950 #define PMC_SAMPLE_FREE ((uint16_t) 0)
951 #define PMC_USER_CALLCHAIN_PENDING ((uint16_t) 0xFFFF)
952
953 struct pmc_samplebuffer {
954 volatile uint64_t ps_prodidx; /* producer index */
955 volatile uint64_t ps_considx; /* consumer index */
956 uintptr_t *ps_callchains; /* all saved call chains */
957 struct pmc_sample ps_samples[]; /* array of sample entries */
958 };
959
960 #define PMC_CONS_SAMPLE(psb) \
961 (&(psb)->ps_samples[(psb)->ps_considx & pmc_sample_mask])
962
963 #define PMC_CONS_SAMPLE_OFF(psb, off) \
964 (&(psb)->ps_samples[(off) & pmc_sample_mask])
965
966 #define PMC_PROD_SAMPLE(psb) \
967 (&(psb)->ps_samples[(psb)->ps_prodidx & pmc_sample_mask])
968
969 /*
970 * struct pmc_cpustate
971 *
972 * A CPU is modelled as a collection of HW PMCs with space for additional
973 * flags.
974 */
975
976 struct pmc_cpu {
977 uint32_t pc_state; /* physical cpu number + flags */
978 struct pmc_samplebuffer *pc_sb[3]; /* space for samples */
979 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */
980 };
981
982 #define PMC_PCPU_CPU_MASK 0x000000FF
983 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00
984 #define PMC_PCPU_FLAGS_SHIFT 8
985 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK)
986 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT)
987 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK)
988 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK)
989 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1))
990
991 /*
992 * struct pmc_binding
993 *
994 * CPU binding information.
995 */
996
997 struct pmc_binding {
998 int pb_bound; /* is bound? */
999 int pb_cpu; /* if so, to which CPU */
1000 };
1001
1002
1003 struct pmc_mdep;
1004
1005 /*
1006 * struct pmc_classdep
1007 *
1008 * PMC class-dependent operations.
1009 */
1010 struct pmc_classdep {
1011 uint32_t pcd_caps; /* class capabilities */
1012 enum pmc_class pcd_class; /* class id */
1013 int pcd_num; /* number of PMCs */
1014 int pcd_ri; /* row index of the first PMC in class */
1015 int pcd_width; /* width of the PMC */
1016
1017 /* configuring/reading/writing the hardware PMCs */
1018 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm);
1019 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm);
1020 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value);
1021 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value);
1022
1023 /* pmc allocation/release */
1024 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t,
1025 const struct pmc_op_pmcallocate *_a);
1026 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm);
1027
1028 /* starting and stopping PMCs */
1029 int (*pcd_start_pmc)(int _cpu, int _ri);
1030 int (*pcd_stop_pmc)(int _cpu, int _ri);
1031
1032 /* description */
1033 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi,
1034 struct pmc **_ppmc);
1035
1036 /* class-dependent initialization & finalization */
1037 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
1038 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
1039
1040 /* machine-specific interface */
1041 int (*pcd_get_msr)(int _ri, uint32_t *_msr);
1042 };
1043
1044 /*
1045 * struct pmc_mdep
1046 *
1047 * Machine dependent bits needed per CPU type.
1048 */
1049
1050 struct pmc_mdep {
1051 uint32_t pmd_cputype; /* from enum pmc_cputype */
1052 uint32_t pmd_npmc; /* number of PMCs per CPU */
1053 uint32_t pmd_nclass; /* number of PMC classes present */
1054
1055 /*
1056 * Machine dependent methods.
1057 */
1058
1059 /* per-cpu initialization and finalization */
1060 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu);
1061 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu);
1062
1063 /* thread context switch in/out */
1064 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp);
1065 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp);
1066
1067 /* handle a PMC interrupt */
1068 int (*pmd_intr)(struct trapframe *_tf);
1069
1070 /*
1071 * PMC class dependent information.
1072 */
1073 struct pmc_classdep pmd_classdep[];
1074 };
1075
1076 /*
1077 * Per-CPU state. This is an array of 'mp_ncpu' pointers
1078 * to struct pmc_cpu descriptors.
1079 */
1080
1081 extern struct pmc_cpu **pmc_pcpu;
1082
1083 /* driver statistics */
1084 extern struct pmc_driverstats pmc_stats;
1085
1086 #if defined(HWPMC_DEBUG)
1087 #include <sys/ktr.h>
1088
1089 /* debug flags, major flag groups */
1090 struct pmc_debugflags {
1091 int pdb_CPU;
1092 int pdb_CSW;
1093 int pdb_LOG;
1094 int pdb_MDP;
1095 int pdb_MOD;
1096 int pdb_OWN;
1097 int pdb_PMC;
1098 int pdb_PRC;
1099 int pdb_SAM;
1100 };
1101
1102 extern struct pmc_debugflags pmc_debugflags;
1103
1104 #define KTR_PMC KTR_SUBSYS
1105
1106 #define PMC_DEBUG_STRSIZE 128
1107 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1108
1109 #define PMCDBG0(M, N, L, F) do { \
1110 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1111 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \
1112 } while (0)
1113 #define PMCDBG1(M, N, L, F, p1) do { \
1114 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1115 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \
1116 } while (0)
1117 #define PMCDBG2(M, N, L, F, p1, p2) do { \
1118 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1119 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \
1120 } while (0)
1121 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \
1122 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1123 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \
1124 } while (0)
1125 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \
1126 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1127 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\
1128 } while (0)
1129 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \
1130 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1131 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \
1132 p5); \
1133 } while (0)
1134 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \
1135 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \
1136 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \
1137 p5, p6); \
1138 } while (0)
1139
1140 /* Major numbers */
1141 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */
1142 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */
1143 #define PMC_DEBUG_MAJ_LOG 2 /* logging */
1144 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */
1145 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */
1146 #define PMC_DEBUG_MAJ_OWN 5 /* owner */
1147 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */
1148 #define PMC_DEBUG_MAJ_PRC 7 /* processes */
1149 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */
1150
1151 /* Minor numbers */
1152
1153 /* Common (8 bits) */
1154 #define PMC_DEBUG_MIN_ALL 0 /* allocation */
1155 #define PMC_DEBUG_MIN_REL 1 /* release */
1156 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */
1157 #define PMC_DEBUG_MIN_INI 3 /* init */
1158 #define PMC_DEBUG_MIN_FND 4 /* find */
1159
1160 /* MODULE */
1161 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */
1162 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */
1163
1164 /* OWN */
1165 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */
1166 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */
1167
1168 /* PROCESSES */
1169 #define PMC_DEBUG_MIN_TLK 8 /* link target */
1170 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */
1171 #define PMC_DEBUG_MIN_EXT 10 /* process exit */
1172 #define PMC_DEBUG_MIN_EXC 11 /* process exec */
1173 #define PMC_DEBUG_MIN_FRK 12 /* process fork */
1174 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */
1175 #define PMC_DEBUG_MIN_SIG 14 /* signalling */
1176
1177 /* CONTEXT SWITCHES */
1178 #define PMC_DEBUG_MIN_SWI 8 /* switch in */
1179 #define PMC_DEBUG_MIN_SWO 9 /* switch out */
1180
1181 /* PMC */
1182 #define PMC_DEBUG_MIN_REG 8 /* pmc register */
1183 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */
1184
1185 /* MACHINE DEPENDENT LAYER */
1186 #define PMC_DEBUG_MIN_REA 8 /* read */
1187 #define PMC_DEBUG_MIN_WRI 9 /* write */
1188 #define PMC_DEBUG_MIN_CFG 10 /* config */
1189 #define PMC_DEBUG_MIN_STA 11 /* start */
1190 #define PMC_DEBUG_MIN_STO 12 /* stop */
1191 #define PMC_DEBUG_MIN_INT 13 /* interrupts */
1192
1193 /* CPU */
1194 #define PMC_DEBUG_MIN_BND 8 /* bind */
1195 #define PMC_DEBUG_MIN_SEL 9 /* select */
1196
1197 /* LOG */
1198 #define PMC_DEBUG_MIN_GTB 8 /* get buf */
1199 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */
1200 #define PMC_DEBUG_MIN_FLS 10 /* flush */
1201 #define PMC_DEBUG_MIN_SAM 11 /* sample */
1202 #define PMC_DEBUG_MIN_CLO 12 /* close */
1203
1204 #else
1205 #define PMCDBG0(M, N, L, F) /* nothing */
1206 #define PMCDBG1(M, N, L, F, p1)
1207 #define PMCDBG2(M, N, L, F, p1, p2)
1208 #define PMCDBG3(M, N, L, F, p1, p2, p3)
1209 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4)
1210 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5)
1211 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6)
1212 #endif
1213
1214 /* declare a dedicated memory pool */
1215 MALLOC_DECLARE(M_PMC);
1216
1217 /*
1218 * Functions
1219 */
1220
1221 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */
1222 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */
1223 int pmc_getrowdisp(int _ri);
1224 int pmc_process_interrupt(int _ring, struct pmc *_pm, struct trapframe *_tf);
1225 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples,
1226 struct trapframe *_tf);
1227 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples,
1228 struct trapframe *_tf);
1229 struct pmc_mdep *pmc_mdep_alloc(int nclasses);
1230 void pmc_mdep_free(struct pmc_mdep *md);
1231 uint64_t pmc_rdtsc(void);
1232 #endif /* _KERNEL */
1233 #endif /* _SYS_PMC_H_ */
Cache object: 30091231043c0398e498a836ae822dd5
|