Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/x86/cpufreq/est.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004 Colin Percival 5 * Copyright (c) 2005 Nate Lawson 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted providing that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 19 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 21 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/cpu.h> 36 #include <sys/kernel.h> 37 #include <sys/malloc.h> 38 #include <sys/module.h> 39 #include <sys/smp.h> 40 #include <sys/systm.h> 41 42 #include "cpufreq_if.h" 43 #include <machine/clock.h> 44 #include <machine/cputypes.h> 45 #include <machine/md_var.h> 46 #include <machine/specialreg.h> 47 48 #include <contrib/dev/acpica/include/acpi.h> 49 50 #include <dev/acpica/acpivar.h> 51 #include "acpi_if.h" 52 53 #include <x86/cpufreq/hwpstate_intel_internal.h> 54 55 /* Status/control registers (from the IA-32 System Programming Guide). */ 56 #define MSR_PERF_STATUS 0x198 57 #define MSR_PERF_CTL 0x199 58 59 /* Register and bit for enabling SpeedStep. */ 60 #define MSR_MISC_ENABLE 0x1a0 61 #define MSR_SS_ENABLE (1<<16) 62 63 /* Frequency and MSR control values. */ 64 typedef struct { 65 uint16_t freq; 66 uint16_t volts; 67 uint16_t id16; 68 int power; 69 } freq_info; 70 71 /* Identifying characteristics of a processor and supported frequencies. */ 72 typedef struct { 73 const u_int vendor_id; 74 uint32_t id32; 75 freq_info *freqtab; 76 size_t tablen; 77 } cpu_info; 78 79 struct est_softc { 80 device_t dev; 81 int acpi_settings; 82 int msr_settings; 83 freq_info *freq_list; 84 size_t flist_len; 85 }; 86 87 /* Convert MHz and mV into IDs for passing to the MSR. */ 88 #define ID16(MHz, mV, bus_clk) \ 89 (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 90 #define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 91 ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 92 93 /* Format for storing IDs in our table. */ 94 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 95 { MHz, mV, ID16(MHz, mV, bus_clk), mW } 96 #define FREQ_INFO(MHz, mV, bus_clk) \ 97 FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 98 #define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 99 { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab, nitems(tab) } 100 #define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 101 { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab, nitems(tab) } 102 103 static int msr_info_enabled = 0; 104 TUNABLE_INT("hw.est.msr_info", &msr_info_enabled); 105 static int strict = -1; 106 TUNABLE_INT("hw.est.strict", &strict); 107 108 /* Default bus clock value for Centrino processors. */ 109 #define INTEL_BUS_CLK 100 110 111 /* XXX Update this if new CPUs have more settings. */ 112 #define EST_MAX_SETTINGS 10 113 CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 114 115 /* Estimate in microseconds of latency for performing a transition. */ 116 #define EST_TRANS_LAT 1000 117 118 /* 119 * Frequency (MHz) and voltage (mV) settings. 120 * 121 * Dothan processors have multiple VID#s with different settings for 122 * each VID#. Since we can't uniquely identify this info 123 * without undisclosed methods from Intel, we can't support newer 124 * processors with this table method. If ACPI Px states are supported, 125 * we get info from them. 126 * 127 * Data from the "Intel Pentium M Processor Datasheet", 128 * Order Number 252612-003, Table 5. 129 */ 130 static freq_info PM17_130[] = { 131 /* 130nm 1.70GHz Pentium M */ 132 FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 133 FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 134 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 135 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 136 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 137 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 138 }; 139 static freq_info PM16_130[] = { 140 /* 130nm 1.60GHz Pentium M */ 141 FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 142 FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 143 FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 144 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 145 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 146 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 147 }; 148 static freq_info PM15_130[] = { 149 /* 130nm 1.50GHz Pentium M */ 150 FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 151 FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 152 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 153 FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 154 FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 155 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 156 }; 157 static freq_info PM14_130[] = { 158 /* 130nm 1.40GHz Pentium M */ 159 FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 160 FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 161 FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 162 FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 163 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 164 }; 165 static freq_info PM13_130[] = { 166 /* 130nm 1.30GHz Pentium M */ 167 FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 168 FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 169 FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 170 FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 171 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 172 }; 173 static freq_info PM13_LV_130[] = { 174 /* 130nm 1.30GHz Low Voltage Pentium M */ 175 FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 176 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 177 FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 178 FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 179 FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 180 FREQ_INFO( 800, 988, INTEL_BUS_CLK), 181 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 182 }; 183 static freq_info PM12_LV_130[] = { 184 /* 130 nm 1.20GHz Low Voltage Pentium M */ 185 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 186 FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 187 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 188 FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 189 FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 190 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 191 }; 192 static freq_info PM11_LV_130[] = { 193 /* 130 nm 1.10GHz Low Voltage Pentium M */ 194 FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 195 FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 196 FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 197 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 198 FREQ_INFO( 600, 956, INTEL_BUS_CLK), 199 }; 200 static freq_info PM11_ULV_130[] = { 201 /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 202 FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 203 FREQ_INFO(1000, 988, INTEL_BUS_CLK), 204 FREQ_INFO( 900, 972, INTEL_BUS_CLK), 205 FREQ_INFO( 800, 956, INTEL_BUS_CLK), 206 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 207 }; 208 static freq_info PM10_ULV_130[] = { 209 /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 210 FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 211 FREQ_INFO( 900, 988, INTEL_BUS_CLK), 212 FREQ_INFO( 800, 972, INTEL_BUS_CLK), 213 FREQ_INFO( 600, 844, INTEL_BUS_CLK), 214 }; 215 216 /* 217 * Data from "Intel Pentium M Processor on 90nm Process with 218 * 2-MB L2 Cache Datasheet", Order Number 302189-008, Table 5. 219 */ 220 static freq_info PM_765A_90[] = { 221 /* 90 nm 2.10GHz Pentium M, VID #A */ 222 FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 223 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 224 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 225 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 226 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 227 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 228 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 229 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 230 }; 231 static freq_info PM_765B_90[] = { 232 /* 90 nm 2.10GHz Pentium M, VID #B */ 233 FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 234 FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 235 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 236 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 237 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 238 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 239 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 240 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 241 }; 242 static freq_info PM_765C_90[] = { 243 /* 90 nm 2.10GHz Pentium M, VID #C */ 244 FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 245 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 246 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 247 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 248 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 249 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 250 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 251 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 252 }; 253 static freq_info PM_765E_90[] = { 254 /* 90 nm 2.10GHz Pentium M, VID #E */ 255 FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 256 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 257 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 258 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 259 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 260 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 261 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 262 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 263 }; 264 static freq_info PM_755A_90[] = { 265 /* 90 nm 2.00GHz Pentium M, VID #A */ 266 FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 267 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 268 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 269 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 270 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 271 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 272 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 273 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 274 }; 275 static freq_info PM_755B_90[] = { 276 /* 90 nm 2.00GHz Pentium M, VID #B */ 277 FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 278 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 279 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 280 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 281 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 282 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 283 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 284 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 285 }; 286 static freq_info PM_755C_90[] = { 287 /* 90 nm 2.00GHz Pentium M, VID #C */ 288 FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 289 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 290 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 291 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 292 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 293 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 294 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 295 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 296 }; 297 static freq_info PM_755D_90[] = { 298 /* 90 nm 2.00GHz Pentium M, VID #D */ 299 FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 300 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 301 FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 302 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 303 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 304 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 305 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 306 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 307 }; 308 static freq_info PM_745A_90[] = { 309 /* 90 nm 1.80GHz Pentium M, VID #A */ 310 FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 311 FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 312 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 313 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 314 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 315 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 316 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 317 }; 318 static freq_info PM_745B_90[] = { 319 /* 90 nm 1.80GHz Pentium M, VID #B */ 320 FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 321 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 322 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 323 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 324 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 325 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 326 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 327 }; 328 static freq_info PM_745C_90[] = { 329 /* 90 nm 1.80GHz Pentium M, VID #C */ 330 FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 331 FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 332 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 333 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 334 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 335 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 336 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 337 }; 338 static freq_info PM_745D_90[] = { 339 /* 90 nm 1.80GHz Pentium M, VID #D */ 340 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 341 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 342 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 343 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 344 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 345 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 346 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 347 }; 348 static freq_info PM_735A_90[] = { 349 /* 90 nm 1.70GHz Pentium M, VID #A */ 350 FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 351 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 352 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 353 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 354 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 355 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 356 }; 357 static freq_info PM_735B_90[] = { 358 /* 90 nm 1.70GHz Pentium M, VID #B */ 359 FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 360 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 361 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 362 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 363 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 364 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 365 }; 366 static freq_info PM_735C_90[] = { 367 /* 90 nm 1.70GHz Pentium M, VID #C */ 368 FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 369 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 370 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 371 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 372 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 373 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 374 }; 375 static freq_info PM_735D_90[] = { 376 /* 90 nm 1.70GHz Pentium M, VID #D */ 377 FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 378 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 379 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 380 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 381 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 382 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 383 }; 384 static freq_info PM_725A_90[] = { 385 /* 90 nm 1.60GHz Pentium M, VID #A */ 386 FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 387 FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 388 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 389 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 390 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 391 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 392 }; 393 static freq_info PM_725B_90[] = { 394 /* 90 nm 1.60GHz Pentium M, VID #B */ 395 FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 396 FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 397 FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 398 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 399 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 400 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 401 }; 402 static freq_info PM_725C_90[] = { 403 /* 90 nm 1.60GHz Pentium M, VID #C */ 404 FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 405 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 406 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 407 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 408 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 409 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 410 }; 411 static freq_info PM_725D_90[] = { 412 /* 90 nm 1.60GHz Pentium M, VID #D */ 413 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 414 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 415 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 416 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 417 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 418 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 419 }; 420 static freq_info PM_715A_90[] = { 421 /* 90 nm 1.50GHz Pentium M, VID #A */ 422 FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 423 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 424 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 425 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 426 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 427 }; 428 static freq_info PM_715B_90[] = { 429 /* 90 nm 1.50GHz Pentium M, VID #B */ 430 FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 431 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 432 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 433 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 434 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 435 }; 436 static freq_info PM_715C_90[] = { 437 /* 90 nm 1.50GHz Pentium M, VID #C */ 438 FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 439 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 440 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 441 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 442 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 443 }; 444 static freq_info PM_715D_90[] = { 445 /* 90 nm 1.50GHz Pentium M, VID #D */ 446 FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 447 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 448 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 449 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 450 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 451 }; 452 static freq_info PM_778_90[] = { 453 /* 90 nm 1.60GHz Low Voltage Pentium M */ 454 FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 455 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 456 FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 457 FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 458 FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 459 FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 460 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 461 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 462 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 463 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 464 }; 465 static freq_info PM_758_90[] = { 466 /* 90 nm 1.50GHz Low Voltage Pentium M */ 467 FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 468 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 469 FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 470 FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 471 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 472 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 473 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 474 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 475 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 476 }; 477 static freq_info PM_738_90[] = { 478 /* 90 nm 1.40GHz Low Voltage Pentium M */ 479 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 480 FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 481 FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 482 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 483 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 484 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 485 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 486 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 487 }; 488 static freq_info PM_773G_90[] = { 489 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 490 FREQ_INFO(1300, 956, INTEL_BUS_CLK), 491 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 492 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 493 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 494 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 495 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 496 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 497 }; 498 static freq_info PM_773H_90[] = { 499 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 500 FREQ_INFO(1300, 940, INTEL_BUS_CLK), 501 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 502 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 503 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 504 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 505 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 506 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 507 }; 508 static freq_info PM_773I_90[] = { 509 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 510 FREQ_INFO(1300, 924, INTEL_BUS_CLK), 511 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 512 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 513 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 514 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 515 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 516 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 517 }; 518 static freq_info PM_773J_90[] = { 519 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 520 FREQ_INFO(1300, 908, INTEL_BUS_CLK), 521 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 522 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 523 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 524 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 525 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 526 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 527 }; 528 static freq_info PM_773K_90[] = { 529 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 530 FREQ_INFO(1300, 892, INTEL_BUS_CLK), 531 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 532 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 533 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 534 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 535 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 536 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 537 }; 538 static freq_info PM_773L_90[] = { 539 /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 540 FREQ_INFO(1300, 876, INTEL_BUS_CLK), 541 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 542 FREQ_INFO(1100, 860, INTEL_BUS_CLK), 543 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 544 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 545 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 546 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 547 }; 548 static freq_info PM_753G_90[] = { 549 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 550 FREQ_INFO(1200, 956, INTEL_BUS_CLK), 551 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 552 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 553 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 554 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 555 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 556 }; 557 static freq_info PM_753H_90[] = { 558 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 559 FREQ_INFO(1200, 940, INTEL_BUS_CLK), 560 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 561 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 562 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 563 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 564 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 565 }; 566 static freq_info PM_753I_90[] = { 567 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 568 FREQ_INFO(1200, 924, INTEL_BUS_CLK), 569 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 570 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 571 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 572 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 573 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 574 }; 575 static freq_info PM_753J_90[] = { 576 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 577 FREQ_INFO(1200, 908, INTEL_BUS_CLK), 578 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 579 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 580 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 581 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 582 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 583 }; 584 static freq_info PM_753K_90[] = { 585 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 586 FREQ_INFO(1200, 892, INTEL_BUS_CLK), 587 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 588 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 589 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 590 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 591 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 592 }; 593 static freq_info PM_753L_90[] = { 594 /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 595 FREQ_INFO(1200, 876, INTEL_BUS_CLK), 596 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 597 FREQ_INFO(1000, 860, INTEL_BUS_CLK), 598 FREQ_INFO( 900, 844, INTEL_BUS_CLK), 599 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 600 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 601 }; 602 603 static freq_info PM_733JG_90[] = { 604 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 605 FREQ_INFO(1100, 956, INTEL_BUS_CLK), 606 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 607 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 608 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 609 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 610 }; 611 static freq_info PM_733JH_90[] = { 612 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 613 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 614 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 615 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 616 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 617 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 618 }; 619 static freq_info PM_733JI_90[] = { 620 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 621 FREQ_INFO(1100, 924, INTEL_BUS_CLK), 622 FREQ_INFO(1000, 908, INTEL_BUS_CLK), 623 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 624 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 625 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 626 }; 627 static freq_info PM_733JJ_90[] = { 628 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 629 FREQ_INFO(1100, 908, INTEL_BUS_CLK), 630 FREQ_INFO(1000, 892, INTEL_BUS_CLK), 631 FREQ_INFO( 900, 876, INTEL_BUS_CLK), 632 FREQ_INFO( 800, 860, INTEL_BUS_CLK), 633 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 634 }; 635 static freq_info PM_733JK_90[] = { 636 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 637 FREQ_INFO(1100, 892, INTEL_BUS_CLK), 638 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 639 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 640 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 641 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 642 }; 643 static freq_info PM_733JL_90[] = { 644 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 645 FREQ_INFO(1100, 876, INTEL_BUS_CLK), 646 FREQ_INFO(1000, 876, INTEL_BUS_CLK), 647 FREQ_INFO( 900, 860, INTEL_BUS_CLK), 648 FREQ_INFO( 800, 844, INTEL_BUS_CLK), 649 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 650 }; 651 static freq_info PM_733_90[] = { 652 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 653 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 654 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 655 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 656 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 657 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 658 }; 659 static freq_info PM_723_90[] = { 660 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 661 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 662 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 663 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 664 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 665 }; 666 667 /* 668 * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 669 * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 670 */ 671 static freq_info C7M_795[] = { 672 /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 673 FREQ_INFO_PWR(2000, 1148, 133, 20000), 674 FREQ_INFO_PWR(1867, 1132, 133, 18000), 675 FREQ_INFO_PWR(1600, 1100, 133, 15000), 676 FREQ_INFO_PWR(1467, 1052, 133, 13000), 677 FREQ_INFO_PWR(1200, 1004, 133, 10000), 678 FREQ_INFO_PWR( 800, 844, 133, 7000), 679 FREQ_INFO_PWR( 667, 844, 133, 6000), 680 FREQ_INFO_PWR( 533, 844, 133, 5000), 681 }; 682 static freq_info C7M_785[] = { 683 /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 684 FREQ_INFO_PWR(1867, 1148, 133, 18000), 685 FREQ_INFO_PWR(1600, 1100, 133, 15000), 686 FREQ_INFO_PWR(1467, 1052, 133, 13000), 687 FREQ_INFO_PWR(1200, 1004, 133, 10000), 688 FREQ_INFO_PWR( 800, 844, 133, 7000), 689 FREQ_INFO_PWR( 667, 844, 133, 6000), 690 FREQ_INFO_PWR( 533, 844, 133, 5000), 691 }; 692 static freq_info C7M_765[] = { 693 /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 694 FREQ_INFO_PWR(1600, 1084, 133, 15000), 695 FREQ_INFO_PWR(1467, 1052, 133, 13000), 696 FREQ_INFO_PWR(1200, 1004, 133, 10000), 697 FREQ_INFO_PWR( 800, 844, 133, 7000), 698 FREQ_INFO_PWR( 667, 844, 133, 6000), 699 FREQ_INFO_PWR( 533, 844, 133, 5000), 700 }; 701 702 static freq_info C7M_794[] = { 703 /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 704 FREQ_INFO_PWR(2000, 1148, 100, 20000), 705 FREQ_INFO_PWR(1800, 1132, 100, 18000), 706 FREQ_INFO_PWR(1600, 1100, 100, 15000), 707 FREQ_INFO_PWR(1400, 1052, 100, 13000), 708 FREQ_INFO_PWR(1000, 1004, 100, 10000), 709 FREQ_INFO_PWR( 800, 844, 100, 7000), 710 FREQ_INFO_PWR( 600, 844, 100, 6000), 711 FREQ_INFO_PWR( 400, 844, 100, 5000), 712 }; 713 static freq_info C7M_784[] = { 714 /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 715 FREQ_INFO_PWR(1800, 1148, 100, 18000), 716 FREQ_INFO_PWR(1600, 1100, 100, 15000), 717 FREQ_INFO_PWR(1400, 1052, 100, 13000), 718 FREQ_INFO_PWR(1000, 1004, 100, 10000), 719 FREQ_INFO_PWR( 800, 844, 100, 7000), 720 FREQ_INFO_PWR( 600, 844, 100, 6000), 721 FREQ_INFO_PWR( 400, 844, 100, 5000), 722 }; 723 static freq_info C7M_764[] = { 724 /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 725 FREQ_INFO_PWR(1600, 1084, 100, 15000), 726 FREQ_INFO_PWR(1400, 1052, 100, 13000), 727 FREQ_INFO_PWR(1000, 1004, 100, 10000), 728 FREQ_INFO_PWR( 800, 844, 100, 7000), 729 FREQ_INFO_PWR( 600, 844, 100, 6000), 730 FREQ_INFO_PWR( 400, 844, 100, 5000), 731 }; 732 static freq_info C7M_754[] = { 733 /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 734 FREQ_INFO_PWR(1500, 1004, 100, 12000), 735 FREQ_INFO_PWR(1400, 988, 100, 11000), 736 FREQ_INFO_PWR(1000, 940, 100, 9000), 737 FREQ_INFO_PWR( 800, 844, 100, 7000), 738 FREQ_INFO_PWR( 600, 844, 100, 6000), 739 FREQ_INFO_PWR( 400, 844, 100, 5000), 740 }; 741 static freq_info C7M_771[] = { 742 /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 743 FREQ_INFO_PWR(1200, 860, 100, 7000), 744 FREQ_INFO_PWR(1000, 860, 100, 6000), 745 FREQ_INFO_PWR( 800, 844, 100, 5500), 746 FREQ_INFO_PWR( 600, 844, 100, 5000), 747 FREQ_INFO_PWR( 400, 844, 100, 4000), 748 }; 749 750 static freq_info C7M_775_ULV[] = { 751 /* 1.50GHz Centaur C7-M ULV */ 752 FREQ_INFO_PWR(1500, 956, 100, 7500), 753 FREQ_INFO_PWR(1400, 940, 100, 6000), 754 FREQ_INFO_PWR(1000, 860, 100, 5000), 755 FREQ_INFO_PWR( 800, 828, 100, 2800), 756 FREQ_INFO_PWR( 600, 796, 100, 2500), 757 FREQ_INFO_PWR( 400, 796, 100, 2000), 758 }; 759 static freq_info C7M_772_ULV[] = { 760 /* 1.20GHz Centaur C7-M ULV */ 761 FREQ_INFO_PWR(1200, 844, 100, 5000), 762 FREQ_INFO_PWR(1000, 844, 100, 4000), 763 FREQ_INFO_PWR( 800, 828, 100, 2800), 764 FREQ_INFO_PWR( 600, 796, 100, 2500), 765 FREQ_INFO_PWR( 400, 796, 100, 2000), 766 }; 767 static freq_info C7M_779_ULV[] = { 768 /* 1.00GHz Centaur C7-M ULV */ 769 FREQ_INFO_PWR(1000, 796, 100, 3500), 770 FREQ_INFO_PWR( 800, 796, 100, 2800), 771 FREQ_INFO_PWR( 600, 796, 100, 2500), 772 FREQ_INFO_PWR( 400, 796, 100, 2000), 773 }; 774 static freq_info C7M_770_ULV[] = { 775 /* 1.00GHz Centaur C7-M ULV */ 776 FREQ_INFO_PWR(1000, 844, 100, 5000), 777 FREQ_INFO_PWR( 800, 796, 100, 2800), 778 FREQ_INFO_PWR( 600, 796, 100, 2500), 779 FREQ_INFO_PWR( 400, 796, 100, 2000), 780 }; 781 782 static cpu_info ESTprocs[] = { 783 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 784 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 785 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 786 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 787 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 788 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 789 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 790 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 791 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 792 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 793 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 794 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 795 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 796 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 797 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 798 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 799 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 800 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 801 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 802 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 803 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 804 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 805 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 806 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 807 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 808 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 809 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 810 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 811 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 812 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 813 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 814 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 815 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 816 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 817 INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 818 INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 819 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 820 INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 821 INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 822 INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 823 INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 824 INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 825 INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 826 INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 827 INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 828 INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 829 INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 830 INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 831 INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 832 INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 833 INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 834 INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 835 INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 836 INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 837 INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 838 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 839 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 840 841 CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 842 CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 843 CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 844 CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 845 CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 846 CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 847 CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 848 CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 849 CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 850 CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 851 CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 852 CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 853 { 0, 0, NULL }, 854 }; 855 856 static void est_identify(driver_t *driver, device_t parent); 857 static int est_features(driver_t *driver, u_int *features); 858 static int est_probe(device_t parent); 859 static int est_attach(device_t parent); 860 static int est_detach(device_t parent); 861 static int est_get_info(device_t dev); 862 static int est_acpi_info(device_t dev, freq_info **freqs, 863 size_t *freqslen); 864 static int est_table_info(device_t dev, uint64_t msr, freq_info **freqs, 865 size_t *freqslen); 866 static int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs, 867 size_t *freqslen); 868 static freq_info *est_get_current(freq_info *freq_list, size_t tablen); 869 static int est_settings(device_t dev, struct cf_setting *sets, int *count); 870 static int est_set(device_t dev, const struct cf_setting *set); 871 static int est_get(device_t dev, struct cf_setting *set); 872 static int est_type(device_t dev, int *type); 873 static int est_set_id16(device_t dev, uint16_t id16, int need_check); 874 static void est_get_id16(uint16_t *id16_p); 875 876 static device_method_t est_methods[] = { 877 /* Device interface */ 878 DEVMETHOD(device_identify, est_identify), 879 DEVMETHOD(device_probe, est_probe), 880 DEVMETHOD(device_attach, est_attach), 881 DEVMETHOD(device_detach, est_detach), 882 883 /* cpufreq interface */ 884 DEVMETHOD(cpufreq_drv_set, est_set), 885 DEVMETHOD(cpufreq_drv_get, est_get), 886 DEVMETHOD(cpufreq_drv_type, est_type), 887 DEVMETHOD(cpufreq_drv_settings, est_settings), 888 889 /* ACPI interface */ 890 DEVMETHOD(acpi_get_features, est_features), 891 {0, 0} 892 }; 893 894 static driver_t est_driver = { 895 "est", 896 est_methods, 897 sizeof(struct est_softc), 898 }; 899 900 DRIVER_MODULE(est, cpu, est_driver, 0, 0); 901 MODULE_DEPEND(est, hwpstate_intel, 1, 1, 1); 902 903 static int 904 est_features(driver_t *driver, u_int *features) 905 { 906 907 /* 908 * Notify the ACPI CPU that we support direct access to MSRs. 909 * XXX C1 "I/O then Halt" seems necessary for some broken BIOS. 910 */ 911 *features = ACPI_CAP_PERF_MSRS | ACPI_CAP_C1_IO_HALT; 912 return (0); 913 } 914 915 static void 916 est_identify(driver_t *driver, device_t parent) 917 { 918 device_t child; 919 920 /* 921 * Defer to hwpstate if it is present. This priority logic 922 * should be replaced with normal newbus probing in the 923 * future. 924 */ 925 intel_hwpstate_identify(NULL, parent); 926 if (device_find_child(parent, "hwpstate_intel", -1) != NULL) 927 return; 928 929 /* Make sure we're not being doubly invoked. */ 930 if (device_find_child(parent, "est", -1) != NULL) 931 return; 932 933 /* Check that CPUID is supported and the vendor is Intel.*/ 934 if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL && 935 cpu_vendor_id != CPU_VENDOR_CENTAUR)) 936 return; 937 938 /* 939 * Check if the CPU supports EST. 940 */ 941 if (!(cpu_feature2 & CPUID2_EST)) 942 return; 943 944 /* 945 * We add a child for each CPU since settings must be performed 946 * on each CPU in the SMP case. 947 */ 948 child = BUS_ADD_CHILD(parent, 10, "est", device_get_unit(parent)); 949 if (child == NULL) 950 device_printf(parent, "add est child failed\n"); 951 } 952 953 static int 954 est_probe(device_t dev) 955 { 956 device_t perf_dev; 957 uint64_t msr; 958 int error, type; 959 960 if (resource_disabled("est", 0)) 961 return (ENXIO); 962 963 /* 964 * If the ACPI perf driver has attached and is not just offering 965 * info, let it manage things. 966 */ 967 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 968 if (perf_dev && device_is_attached(perf_dev)) { 969 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 970 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 971 return (ENXIO); 972 } 973 974 /* Attempt to enable SpeedStep if not currently enabled. */ 975 msr = rdmsr(MSR_MISC_ENABLE); 976 if ((msr & MSR_SS_ENABLE) == 0) { 977 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 978 if (bootverbose) 979 device_printf(dev, "enabling SpeedStep\n"); 980 981 /* Check if the enable failed. */ 982 msr = rdmsr(MSR_MISC_ENABLE); 983 if ((msr & MSR_SS_ENABLE) == 0) { 984 device_printf(dev, "failed to enable SpeedStep\n"); 985 return (ENXIO); 986 } 987 } 988 989 device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 990 return (0); 991 } 992 993 static int 994 est_attach(device_t dev) 995 { 996 struct est_softc *sc; 997 998 sc = device_get_softc(dev); 999 sc->dev = dev; 1000 1001 /* On SMP system we can't guarantie independent freq setting. */ 1002 if (strict == -1 && mp_ncpus > 1) 1003 strict = 0; 1004 /* Check CPU for supported settings. */ 1005 if (est_get_info(dev)) 1006 return (ENXIO); 1007 1008 cpufreq_register(dev); 1009 return (0); 1010 } 1011 1012 static int 1013 est_detach(device_t dev) 1014 { 1015 struct est_softc *sc; 1016 int error; 1017 1018 error = cpufreq_unregister(dev); 1019 if (error) 1020 return (error); 1021 1022 sc = device_get_softc(dev); 1023 if (sc->acpi_settings || sc->msr_settings) 1024 free(sc->freq_list, M_DEVBUF); 1025 return (0); 1026 } 1027 1028 /* 1029 * Probe for supported CPU settings. First, check our static table of 1030 * settings. If no match, try using the ones offered by acpi_perf 1031 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1032 * series) export both legacy SMM IO-based access and direct MSR access 1033 * but the direct access specifies invalid values for _PSS. 1034 */ 1035 static int 1036 est_get_info(device_t dev) 1037 { 1038 struct est_softc *sc; 1039 uint64_t msr; 1040 int error; 1041 1042 sc = device_get_softc(dev); 1043 msr = rdmsr(MSR_PERF_STATUS); 1044 error = est_table_info(dev, msr, &sc->freq_list, &sc->flist_len); 1045 if (error) 1046 error = est_acpi_info(dev, &sc->freq_list, &sc->flist_len); 1047 if (error) 1048 error = est_msr_info(dev, msr, &sc->freq_list, &sc->flist_len); 1049 1050 if (error) { 1051 printf( 1052 "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1053 "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1054 return (ENXIO); 1055 } 1056 1057 return (0); 1058 } 1059 1060 static int 1061 est_acpi_info(device_t dev, freq_info **freqs, size_t *freqslen) 1062 { 1063 struct est_softc *sc; 1064 struct cf_setting *sets; 1065 freq_info *table; 1066 device_t perf_dev; 1067 int count, error, i, j; 1068 uint16_t saved_id16; 1069 1070 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1071 if (perf_dev == NULL || !device_is_attached(perf_dev)) 1072 return (ENXIO); 1073 1074 /* Fetch settings from acpi_perf. */ 1075 sc = device_get_softc(dev); 1076 table = NULL; 1077 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1078 if (sets == NULL) 1079 return (ENOMEM); 1080 count = MAX_SETTINGS; 1081 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1082 if (error) 1083 goto out; 1084 1085 /* Parse settings into our local table format. */ 1086 table = malloc(count * sizeof(*table), M_DEVBUF, M_NOWAIT); 1087 if (table == NULL) { 1088 error = ENOMEM; 1089 goto out; 1090 } 1091 est_get_id16(&saved_id16); 1092 for (i = 0, j = 0; i < count; i++) { 1093 /* 1094 * Confirm id16 value is correct. 1095 */ 1096 if (sets[i].freq > 0) { 1097 error = est_set_id16(dev, sets[i].spec[0], strict); 1098 if (error != 0) { 1099 if (bootverbose) 1100 device_printf(dev, "Invalid freq %u, " 1101 "ignored.\n", sets[i].freq); 1102 continue; 1103 } 1104 table[j].freq = sets[i].freq; 1105 table[j].volts = sets[i].volts; 1106 table[j].id16 = sets[i].spec[0]; 1107 table[j].power = sets[i].power; 1108 ++j; 1109 } 1110 } 1111 /* restore saved setting */ 1112 est_set_id16(dev, saved_id16, 0); 1113 1114 sc->acpi_settings = TRUE; 1115 *freqs = table; 1116 *freqslen = j; 1117 error = 0; 1118 1119 out: 1120 if (sets) 1121 free(sets, M_TEMP); 1122 if (error && table) 1123 free(table, M_DEVBUF); 1124 return (error); 1125 } 1126 1127 static int 1128 est_table_info(device_t dev, uint64_t msr, freq_info **freqs, size_t *freqslen) 1129 { 1130 cpu_info *p; 1131 uint32_t id; 1132 1133 /* Find a table which matches (vendor, id32). */ 1134 id = msr >> 32; 1135 for (p = ESTprocs; p->id32 != 0; p++) { 1136 if (p->vendor_id == cpu_vendor_id && p->id32 == id) 1137 break; 1138 } 1139 if (p->id32 == 0) 1140 return (EOPNOTSUPP); 1141 1142 /* Make sure the current setpoint is valid. */ 1143 if (est_get_current(p->freqtab, p->tablen) == NULL) { 1144 device_printf(dev, "current setting not found in table\n"); 1145 return (EOPNOTSUPP); 1146 } 1147 1148 *freqs = p->freqtab; 1149 *freqslen = p->tablen; 1150 return (0); 1151 } 1152 1153 static int 1154 bus_speed_ok(int bus) 1155 { 1156 1157 switch (bus) { 1158 case 100: 1159 case 133: 1160 case 333: 1161 return (1); 1162 default: 1163 return (0); 1164 } 1165 } 1166 1167 /* 1168 * Flesh out a simple rate table containing the high and low frequencies 1169 * based on the current clock speed and the upper 32 bits of the MSR. 1170 */ 1171 static int 1172 est_msr_info(device_t dev, uint64_t msr, freq_info **freqs, size_t *freqslen) 1173 { 1174 struct est_softc *sc; 1175 freq_info *fp; 1176 int bus, freq, volts; 1177 uint16_t id; 1178 1179 if (!msr_info_enabled) 1180 return (EOPNOTSUPP); 1181 1182 /* Figure out the bus clock. */ 1183 freq = atomic_load_acq_64(&tsc_freq) / 1000000; 1184 id = msr >> 32; 1185 bus = freq / (id >> 8); 1186 device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus); 1187 if (!bus_speed_ok(bus)) { 1188 /* We may be running on the low frequency. */ 1189 id = msr >> 48; 1190 bus = freq / (id >> 8); 1191 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus); 1192 if (!bus_speed_ok(bus)) 1193 return (EOPNOTSUPP); 1194 1195 /* Calculate high frequency. */ 1196 id = msr >> 32; 1197 freq = ((id >> 8) & 0xff) * bus; 1198 } 1199 1200 /* Fill out a new freq table containing just the high and low freqs. */ 1201 sc = device_get_softc(dev); 1202 fp = malloc(sizeof(freq_info) * 2, M_DEVBUF, M_WAITOK | M_ZERO); 1203 1204 /* First, the high frequency. */ 1205 volts = id & 0xff; 1206 if (volts != 0) { 1207 volts <<= 4; 1208 volts += 700; 1209 } 1210 fp[0].freq = freq; 1211 fp[0].volts = volts; 1212 fp[0].id16 = id; 1213 fp[0].power = CPUFREQ_VAL_UNKNOWN; 1214 device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq, 1215 volts); 1216 1217 /* Second, the low frequency. */ 1218 id = msr >> 48; 1219 freq = ((id >> 8) & 0xff) * bus; 1220 volts = id & 0xff; 1221 if (volts != 0) { 1222 volts <<= 4; 1223 volts += 700; 1224 } 1225 fp[1].freq = freq; 1226 fp[1].volts = volts; 1227 fp[1].id16 = id; 1228 fp[1].power = CPUFREQ_VAL_UNKNOWN; 1229 device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq, 1230 volts); 1231 1232 /* Table is already terminated due to M_ZERO. */ 1233 sc->msr_settings = TRUE; 1234 *freqs = fp; 1235 *freqslen = 2; 1236 return (0); 1237 } 1238 1239 static void 1240 est_get_id16(uint16_t *id16_p) 1241 { 1242 *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1243 } 1244 1245 static int 1246 est_set_id16(device_t dev, uint16_t id16, int need_check) 1247 { 1248 uint64_t msr; 1249 uint16_t new_id16; 1250 int ret = 0; 1251 1252 /* Read the current register, mask out the old, set the new id. */ 1253 msr = rdmsr(MSR_PERF_CTL); 1254 msr = (msr & ~0xffff) | id16; 1255 wrmsr(MSR_PERF_CTL, msr); 1256 1257 if (need_check) { 1258 /* Wait a short while and read the new status. */ 1259 DELAY(EST_TRANS_LAT); 1260 est_get_id16(&new_id16); 1261 if (new_id16 != id16) { 1262 if (bootverbose) 1263 device_printf(dev, "Invalid id16 (set, cur) " 1264 "= (%u, %u)\n", id16, new_id16); 1265 ret = ENXIO; 1266 } 1267 } 1268 return (ret); 1269 } 1270 1271 static freq_info * 1272 est_get_current(freq_info *freq_list, size_t tablen) 1273 { 1274 freq_info *f; 1275 int i; 1276 uint16_t id16; 1277 1278 /* 1279 * Try a few times to get a valid value. Sometimes, if the CPU 1280 * is in the middle of an asynchronous transition (i.e., P4TCC), 1281 * we get a temporary invalid result. 1282 */ 1283 for (i = 0; i < 5; i++) { 1284 est_get_id16(&id16); 1285 for (f = freq_list; f < freq_list + tablen; f++) { 1286 if (f->id16 == id16) 1287 return (f); 1288 } 1289 DELAY(100); 1290 } 1291 return (NULL); 1292 } 1293 1294 static int 1295 est_settings(device_t dev, struct cf_setting *sets, int *count) 1296 { 1297 struct est_softc *sc; 1298 freq_info *f; 1299 int i; 1300 1301 sc = device_get_softc(dev); 1302 if (*count < EST_MAX_SETTINGS) 1303 return (E2BIG); 1304 1305 i = 0; 1306 for (f = sc->freq_list; f < sc->freq_list + sc->flist_len; f++, i++) { 1307 sets[i].freq = f->freq; 1308 sets[i].volts = f->volts; 1309 sets[i].power = f->power; 1310 sets[i].lat = EST_TRANS_LAT; 1311 sets[i].dev = dev; 1312 } 1313 *count = i; 1314 1315 return (0); 1316 } 1317 1318 static int 1319 est_set(device_t dev, const struct cf_setting *set) 1320 { 1321 struct est_softc *sc; 1322 freq_info *f; 1323 1324 /* Find the setting matching the requested one. */ 1325 sc = device_get_softc(dev); 1326 for (f = sc->freq_list; f < sc->freq_list + sc->flist_len; f++) { 1327 if (f->freq == set->freq) 1328 break; 1329 } 1330 if (f->freq == 0) 1331 return (EINVAL); 1332 1333 /* Read the current register, mask out the old, set the new id. */ 1334 est_set_id16(dev, f->id16, 0); 1335 1336 return (0); 1337 } 1338 1339 static int 1340 est_get(device_t dev, struct cf_setting *set) 1341 { 1342 struct est_softc *sc; 1343 freq_info *f; 1344 1345 sc = device_get_softc(dev); 1346 f = est_get_current(sc->freq_list, sc->flist_len); 1347 if (f == NULL) 1348 return (ENXIO); 1349 1350 set->freq = f->freq; 1351 set->volts = f->volts; 1352 set->power = f->power; 1353 set->lat = EST_TRANS_LAT; 1354 set->dev = dev; 1355 return (0); 1356 } 1357 1358 static int 1359 est_type(device_t dev, int *type) 1360 { 1361 1362 if (type == NULL) 1363 return (EINVAL); 1364 1365 *type = CPUFREQ_TYPE_ABSOLUTE; 1366 return (0); 1367 }
Cache object: 543b6e2279c4dda7ea790c74470636e1
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