The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/x86/cpufreq/est.c

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    1 /*-
    2  * Copyright (c) 2004 Colin Percival
    3  * Copyright (c) 2005 Nate Lawson
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted providing that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
   17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 
   19  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
   24  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 
   25  * POSSIBILITY OF SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: releng/10.4/sys/x86/cpufreq/est.c 260473 2014-01-09 10:44:27Z mav $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/bus.h>
   33 #include <sys/cpu.h>
   34 #include <sys/kernel.h>
   35 #include <sys/malloc.h>
   36 #include <sys/module.h>
   37 #include <sys/smp.h>
   38 #include <sys/systm.h>
   39 
   40 #include "cpufreq_if.h"
   41 #include <machine/clock.h>
   42 #include <machine/cputypes.h>
   43 #include <machine/md_var.h>
   44 #include <machine/specialreg.h>
   45 
   46 #include <contrib/dev/acpica/include/acpi.h>
   47 
   48 #include <dev/acpica/acpivar.h>
   49 #include "acpi_if.h"
   50 
   51 /* Status/control registers (from the IA-32 System Programming Guide). */
   52 #define MSR_PERF_STATUS         0x198
   53 #define MSR_PERF_CTL            0x199
   54 
   55 /* Register and bit for enabling SpeedStep. */
   56 #define MSR_MISC_ENABLE         0x1a0
   57 #define MSR_SS_ENABLE           (1<<16)
   58 
   59 /* Frequency and MSR control values. */
   60 typedef struct {
   61         uint16_t        freq;
   62         uint16_t        volts;
   63         uint16_t        id16;
   64         int             power;
   65 } freq_info;
   66 
   67 /* Identifying characteristics of a processor and supported frequencies. */
   68 typedef struct {
   69         const u_int     vendor_id;
   70         uint32_t        id32;
   71         freq_info       *freqtab;
   72 } cpu_info;
   73 
   74 struct est_softc {
   75         device_t        dev;
   76         int             acpi_settings;
   77         int             msr_settings;
   78         freq_info       *freq_list;
   79 };
   80 
   81 /* Convert MHz and mV into IDs for passing to the MSR. */
   82 #define ID16(MHz, mV, bus_clk)                          \
   83         (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
   84 #define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk)     \
   85         ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
   86 
   87 /* Format for storing IDs in our table. */
   88 #define FREQ_INFO_PWR(MHz, mV, bus_clk, mW)             \
   89         { MHz, mV, ID16(MHz, mV, bus_clk), mW }
   90 #define FREQ_INFO(MHz, mV, bus_clk)                     \
   91         FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
   92 #define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk)         \
   93         { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
   94 #define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk)       \
   95         { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
   96 
   97 static int msr_info_enabled = 0;
   98 TUNABLE_INT("hw.est.msr_info", &msr_info_enabled);
   99 static int strict = -1;
  100 TUNABLE_INT("hw.est.strict", &strict);
  101 
  102 /* Default bus clock value for Centrino processors. */
  103 #define INTEL_BUS_CLK           100
  104 
  105 /* XXX Update this if new CPUs have more settings. */
  106 #define EST_MAX_SETTINGS        10
  107 CTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS);
  108 
  109 /* Estimate in microseconds of latency for performing a transition. */
  110 #define EST_TRANS_LAT           1000
  111 
  112 /*
  113  * Frequency (MHz) and voltage (mV) settings.
  114  *
  115  * Dothan processors have multiple VID#s with different settings for
  116  * each VID#.  Since we can't uniquely identify this info
  117  * without undisclosed methods from Intel, we can't support newer
  118  * processors with this table method.  If ACPI Px states are supported,
  119  * we get info from them.
  120  *
  121  * Data from the "Intel Pentium M Processor Datasheet",
  122  * Order Number 252612-003, Table 5.
  123  */
  124 static freq_info PM17_130[] = {
  125         /* 130nm 1.70GHz Pentium M */
  126         FREQ_INFO(1700, 1484, INTEL_BUS_CLK),
  127         FREQ_INFO(1400, 1308, INTEL_BUS_CLK),
  128         FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
  129         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  130         FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
  131         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  132         FREQ_INFO(   0,    0, 1),
  133 };
  134 static freq_info PM16_130[] = {
  135         /* 130nm 1.60GHz Pentium M */
  136         FREQ_INFO(1600, 1484, INTEL_BUS_CLK),
  137         FREQ_INFO(1400, 1420, INTEL_BUS_CLK),
  138         FREQ_INFO(1200, 1276, INTEL_BUS_CLK),
  139         FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
  140         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  141         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  142         FREQ_INFO(   0,    0, 1),
  143 };
  144 static freq_info PM15_130[] = {
  145         /* 130nm 1.50GHz Pentium M */
  146         FREQ_INFO(1500, 1484, INTEL_BUS_CLK),
  147         FREQ_INFO(1400, 1452, INTEL_BUS_CLK),
  148         FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
  149         FREQ_INFO(1000, 1228, INTEL_BUS_CLK),
  150         FREQ_INFO( 800, 1116, INTEL_BUS_CLK),
  151         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  152         FREQ_INFO(   0,    0, 1),
  153 };
  154 static freq_info PM14_130[] = {
  155         /* 130nm 1.40GHz Pentium M */
  156         FREQ_INFO(1400, 1484, INTEL_BUS_CLK),
  157         FREQ_INFO(1200, 1436, INTEL_BUS_CLK),
  158         FREQ_INFO(1000, 1308, INTEL_BUS_CLK),
  159         FREQ_INFO( 800, 1180, INTEL_BUS_CLK),
  160         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  161         FREQ_INFO(   0,    0, 1),
  162 };
  163 static freq_info PM13_130[] = {
  164         /* 130nm 1.30GHz Pentium M */
  165         FREQ_INFO(1300, 1388, INTEL_BUS_CLK),
  166         FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
  167         FREQ_INFO(1000, 1292, INTEL_BUS_CLK),
  168         FREQ_INFO( 800, 1260, INTEL_BUS_CLK),
  169         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  170         FREQ_INFO(   0,    0, 1),
  171 };
  172 static freq_info PM13_LV_130[] = {
  173         /* 130nm 1.30GHz Low Voltage Pentium M */
  174         FREQ_INFO(1300, 1180, INTEL_BUS_CLK),
  175         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  176         FREQ_INFO(1100, 1100, INTEL_BUS_CLK),
  177         FREQ_INFO(1000, 1020, INTEL_BUS_CLK),
  178         FREQ_INFO( 900, 1004, INTEL_BUS_CLK),
  179         FREQ_INFO( 800,  988, INTEL_BUS_CLK),
  180         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  181         FREQ_INFO(   0,    0, 1),
  182 };
  183 static freq_info PM12_LV_130[] = {
  184         /* 130 nm 1.20GHz Low Voltage Pentium M */
  185         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  186         FREQ_INFO(1100, 1164, INTEL_BUS_CLK),
  187         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  188         FREQ_INFO( 900, 1020, INTEL_BUS_CLK),
  189         FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
  190         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  191         FREQ_INFO(   0,    0, 1),
  192 };
  193 static freq_info PM11_LV_130[] = {
  194         /* 130 nm 1.10GHz Low Voltage Pentium M */
  195         FREQ_INFO(1100, 1180, INTEL_BUS_CLK),
  196         FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
  197         FREQ_INFO( 900, 1100, INTEL_BUS_CLK),
  198         FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
  199         FREQ_INFO( 600,  956, INTEL_BUS_CLK),
  200         FREQ_INFO(   0,    0, 1),
  201 };
  202 static freq_info PM11_ULV_130[] = {
  203         /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */
  204         FREQ_INFO(1100, 1004, INTEL_BUS_CLK),
  205         FREQ_INFO(1000,  988, INTEL_BUS_CLK),
  206         FREQ_INFO( 900,  972, INTEL_BUS_CLK),
  207         FREQ_INFO( 800,  956, INTEL_BUS_CLK),
  208         FREQ_INFO( 600,  844, INTEL_BUS_CLK),
  209         FREQ_INFO(   0,    0, 1),
  210 };
  211 static freq_info PM10_ULV_130[] = {
  212         /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */
  213         FREQ_INFO(1000, 1004, INTEL_BUS_CLK),
  214         FREQ_INFO( 900,  988, INTEL_BUS_CLK),
  215         FREQ_INFO( 800,  972, INTEL_BUS_CLK),
  216         FREQ_INFO( 600,  844, INTEL_BUS_CLK),
  217         FREQ_INFO(   0,    0, 1),
  218 };
  219 
  220 /*
  221  * Data from "Intel Pentium M Processor on 90nm Process with
  222  * 2-MB L2 Cache Datasheet", Order Number 302189-008, Table 5.
  223  */
  224 static freq_info PM_765A_90[] = {
  225         /* 90 nm 2.10GHz Pentium M, VID #A */
  226         FREQ_INFO(2100, 1340, INTEL_BUS_CLK),
  227         FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
  228         FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
  229         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  230         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  231         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  232         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  233         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  234         FREQ_INFO(   0,    0, 1),
  235 };
  236 static freq_info PM_765B_90[] = {
  237         /* 90 nm 2.10GHz Pentium M, VID #B */
  238         FREQ_INFO(2100, 1324, INTEL_BUS_CLK),
  239         FREQ_INFO(1800, 1260, INTEL_BUS_CLK),
  240         FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
  241         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  242         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  243         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  244         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  245         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  246         FREQ_INFO(   0,    0, 1),
  247 };
  248 static freq_info PM_765C_90[] = {
  249         /* 90 nm 2.10GHz Pentium M, VID #C */
  250         FREQ_INFO(2100, 1308, INTEL_BUS_CLK),
  251         FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
  252         FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
  253         FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
  254         FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
  255         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  256         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  257         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  258         FREQ_INFO(   0,    0, 1),
  259 };
  260 static freq_info PM_765E_90[] = {
  261         /* 90 nm 2.10GHz Pentium M, VID #E */
  262         FREQ_INFO(2100, 1356, INTEL_BUS_CLK),
  263         FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
  264         FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
  265         FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
  266         FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
  267         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  268         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  269         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  270         FREQ_INFO(   0,    0, 1),
  271 };
  272 static freq_info PM_755A_90[] = {
  273         /* 90 nm 2.00GHz Pentium M, VID #A */
  274         FREQ_INFO(2000, 1340, INTEL_BUS_CLK),
  275         FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
  276         FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
  277         FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
  278         FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
  279         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  280         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  281         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  282         FREQ_INFO(   0,    0, 1),
  283 };
  284 static freq_info PM_755B_90[] = {
  285         /* 90 nm 2.00GHz Pentium M, VID #B */
  286         FREQ_INFO(2000, 1324, INTEL_BUS_CLK),
  287         FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
  288         FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
  289         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  290         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  291         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  292         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  293         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  294         FREQ_INFO(   0,    0, 1),
  295 };
  296 static freq_info PM_755C_90[] = {
  297         /* 90 nm 2.00GHz Pentium M, VID #C */
  298         FREQ_INFO(2000, 1308, INTEL_BUS_CLK),
  299         FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
  300         FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
  301         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  302         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  303         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  304         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  305         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  306         FREQ_INFO(   0,    0, 1),
  307 };
  308 static freq_info PM_755D_90[] = {
  309         /* 90 nm 2.00GHz Pentium M, VID #D */
  310         FREQ_INFO(2000, 1276, INTEL_BUS_CLK),
  311         FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
  312         FREQ_INFO(1600, 1196, INTEL_BUS_CLK),
  313         FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
  314         FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
  315         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  316         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  317         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  318         FREQ_INFO(   0,    0, 1),
  319 };
  320 static freq_info PM_745A_90[] = {
  321         /* 90 nm 1.80GHz Pentium M, VID #A */
  322         FREQ_INFO(1800, 1340, INTEL_BUS_CLK),
  323         FREQ_INFO(1600, 1292, INTEL_BUS_CLK),
  324         FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
  325         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  326         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  327         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  328         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  329         FREQ_INFO(   0,    0, 1),
  330 };
  331 static freq_info PM_745B_90[] = {
  332         /* 90 nm 1.80GHz Pentium M, VID #B */
  333         FREQ_INFO(1800, 1324, INTEL_BUS_CLK),
  334         FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
  335         FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
  336         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  337         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  338         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  339         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  340         FREQ_INFO(   0,    0, 1),
  341 };
  342 static freq_info PM_745C_90[] = {
  343         /* 90 nm 1.80GHz Pentium M, VID #C */
  344         FREQ_INFO(1800, 1308, INTEL_BUS_CLK),
  345         FREQ_INFO(1600, 1260, INTEL_BUS_CLK),
  346         FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
  347         FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
  348         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  349         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  350         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  351         FREQ_INFO(   0,    0, 1),
  352 };
  353 static freq_info PM_745D_90[] = {
  354         /* 90 nm 1.80GHz Pentium M, VID #D */
  355         FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
  356         FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
  357         FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
  358         FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
  359         FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
  360         FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
  361         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  362         FREQ_INFO(   0,    0, 1),
  363 };
  364 static freq_info PM_735A_90[] = {
  365         /* 90 nm 1.70GHz Pentium M, VID #A */
  366         FREQ_INFO(1700, 1340, INTEL_BUS_CLK),
  367         FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
  368         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  369         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  370         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  371         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  372         FREQ_INFO(   0,    0, 1),
  373 };
  374 static freq_info PM_735B_90[] = {
  375         /* 90 nm 1.70GHz Pentium M, VID #B */
  376         FREQ_INFO(1700, 1324, INTEL_BUS_CLK),
  377         FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
  378         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  379         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  380         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  381         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  382         FREQ_INFO(   0,    0, 1),
  383 };
  384 static freq_info PM_735C_90[] = {
  385         /* 90 nm 1.70GHz Pentium M, VID #C */
  386         FREQ_INFO(1700, 1308, INTEL_BUS_CLK),
  387         FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
  388         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  389         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  390         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  391         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  392         FREQ_INFO(   0,    0, 1),
  393 };
  394 static freq_info PM_735D_90[] = {
  395         /* 90 nm 1.70GHz Pentium M, VID #D */
  396         FREQ_INFO(1700, 1276, INTEL_BUS_CLK),
  397         FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
  398         FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
  399         FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
  400         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  401         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  402         FREQ_INFO(   0,    0, 1),
  403 };
  404 static freq_info PM_725A_90[] = {
  405         /* 90 nm 1.60GHz Pentium M, VID #A */
  406         FREQ_INFO(1600, 1340, INTEL_BUS_CLK),
  407         FREQ_INFO(1400, 1276, INTEL_BUS_CLK),
  408         FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
  409         FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
  410         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  411         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  412         FREQ_INFO(   0,    0, 1),
  413 };
  414 static freq_info PM_725B_90[] = {
  415         /* 90 nm 1.60GHz Pentium M, VID #B */
  416         FREQ_INFO(1600, 1324, INTEL_BUS_CLK),
  417         FREQ_INFO(1400, 1260, INTEL_BUS_CLK),
  418         FREQ_INFO(1200, 1196, INTEL_BUS_CLK),
  419         FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
  420         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  421         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  422         FREQ_INFO(   0,    0, 1),
  423 };
  424 static freq_info PM_725C_90[] = {
  425         /* 90 nm 1.60GHz Pentium M, VID #C */
  426         FREQ_INFO(1600, 1308, INTEL_BUS_CLK),
  427         FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
  428         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  429         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  430         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  431         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  432         FREQ_INFO(   0,    0, 1),
  433 };
  434 static freq_info PM_725D_90[] = {
  435         /* 90 nm 1.60GHz Pentium M, VID #D */
  436         FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
  437         FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
  438         FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
  439         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  440         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  441         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  442         FREQ_INFO(   0,    0, 1),
  443 };
  444 static freq_info PM_715A_90[] = {
  445         /* 90 nm 1.50GHz Pentium M, VID #A */
  446         FREQ_INFO(1500, 1340, INTEL_BUS_CLK),
  447         FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
  448         FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
  449         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  450         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  451         FREQ_INFO(   0,    0, 1),
  452 };
  453 static freq_info PM_715B_90[] = {
  454         /* 90 nm 1.50GHz Pentium M, VID #B */
  455         FREQ_INFO(1500, 1324, INTEL_BUS_CLK),
  456         FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
  457         FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
  458         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  459         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  460         FREQ_INFO(   0,    0, 1),
  461 };
  462 static freq_info PM_715C_90[] = {
  463         /* 90 nm 1.50GHz Pentium M, VID #C */
  464         FREQ_INFO(1500, 1308, INTEL_BUS_CLK),
  465         FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
  466         FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
  467         FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
  468         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  469         FREQ_INFO(   0,    0, 1),
  470 };
  471 static freq_info PM_715D_90[] = {
  472         /* 90 nm 1.50GHz Pentium M, VID #D */
  473         FREQ_INFO(1500, 1276, INTEL_BUS_CLK),
  474         FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
  475         FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
  476         FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
  477         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  478         FREQ_INFO(   0,    0, 1),
  479 };
  480 static freq_info PM_778_90[] = {
  481         /* 90 nm 1.60GHz Low Voltage Pentium M */
  482         FREQ_INFO(1600, 1116, INTEL_BUS_CLK),
  483         FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
  484         FREQ_INFO(1400, 1100, INTEL_BUS_CLK),
  485         FREQ_INFO(1300, 1084, INTEL_BUS_CLK),
  486         FREQ_INFO(1200, 1068, INTEL_BUS_CLK),
  487         FREQ_INFO(1100, 1052, INTEL_BUS_CLK),
  488         FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
  489         FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
  490         FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
  491         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  492         FREQ_INFO(   0,    0, 1),
  493 };
  494 static freq_info PM_758_90[] = {
  495         /* 90 nm 1.50GHz Low Voltage Pentium M */
  496         FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
  497         FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
  498         FREQ_INFO(1300, 1100, INTEL_BUS_CLK),
  499         FREQ_INFO(1200, 1084, INTEL_BUS_CLK),
  500         FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
  501         FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
  502         FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
  503         FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
  504         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  505         FREQ_INFO(   0,    0, 1),
  506 };
  507 static freq_info PM_738_90[] = {
  508         /* 90 nm 1.40GHz Low Voltage Pentium M */
  509         FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
  510         FREQ_INFO(1300, 1116, INTEL_BUS_CLK),
  511         FREQ_INFO(1200, 1100, INTEL_BUS_CLK),
  512         FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
  513         FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
  514         FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
  515         FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
  516         FREQ_INFO( 600,  988, INTEL_BUS_CLK),
  517         FREQ_INFO(   0,    0, 1),
  518 };
  519 static freq_info PM_773G_90[] = {
  520         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */
  521         FREQ_INFO(1300,  956, INTEL_BUS_CLK),
  522         FREQ_INFO(1200,  940, INTEL_BUS_CLK),
  523         FREQ_INFO(1100,  924, INTEL_BUS_CLK),
  524         FREQ_INFO(1000,  908, INTEL_BUS_CLK),
  525         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  526         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  527         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  528 };
  529 static freq_info PM_773H_90[] = {
  530         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */
  531         FREQ_INFO(1300,  940, INTEL_BUS_CLK),
  532         FREQ_INFO(1200,  924, INTEL_BUS_CLK),
  533         FREQ_INFO(1100,  908, INTEL_BUS_CLK),
  534         FREQ_INFO(1000,  892, INTEL_BUS_CLK),
  535         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  536         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  537         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  538 };
  539 static freq_info PM_773I_90[] = {
  540         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */
  541         FREQ_INFO(1300,  924, INTEL_BUS_CLK),
  542         FREQ_INFO(1200,  908, INTEL_BUS_CLK),
  543         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  544         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  545         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  546         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  547         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  548 };
  549 static freq_info PM_773J_90[] = {
  550         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */
  551         FREQ_INFO(1300,  908, INTEL_BUS_CLK),
  552         FREQ_INFO(1200,  908, INTEL_BUS_CLK),
  553         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  554         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  555         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  556         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  557         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  558 };
  559 static freq_info PM_773K_90[] = {
  560         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */
  561         FREQ_INFO(1300,  892, INTEL_BUS_CLK),
  562         FREQ_INFO(1200,  892, INTEL_BUS_CLK),
  563         FREQ_INFO(1100,  876, INTEL_BUS_CLK),
  564         FREQ_INFO(1000,  860, INTEL_BUS_CLK),
  565         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  566         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  567         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  568 };
  569 static freq_info PM_773L_90[] = {
  570         /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */
  571         FREQ_INFO(1300,  876, INTEL_BUS_CLK),
  572         FREQ_INFO(1200,  876, INTEL_BUS_CLK),
  573         FREQ_INFO(1100,  860, INTEL_BUS_CLK),
  574         FREQ_INFO(1000,  860, INTEL_BUS_CLK),
  575         FREQ_INFO( 900,  844, INTEL_BUS_CLK),
  576         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  577         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  578 };
  579 static freq_info PM_753G_90[] = {
  580         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */
  581         FREQ_INFO(1200,  956, INTEL_BUS_CLK),
  582         FREQ_INFO(1100,  940, INTEL_BUS_CLK),
  583         FREQ_INFO(1000,  908, INTEL_BUS_CLK),
  584         FREQ_INFO( 900,  892, INTEL_BUS_CLK),
  585         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  586         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  587 };
  588 static freq_info PM_753H_90[] = {
  589         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */
  590         FREQ_INFO(1200,  940, INTEL_BUS_CLK),
  591         FREQ_INFO(1100,  924, INTEL_BUS_CLK),
  592         FREQ_INFO(1000,  908, INTEL_BUS_CLK),
  593         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  594         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  595         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  596 };
  597 static freq_info PM_753I_90[] = {
  598         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */
  599         FREQ_INFO(1200,  924, INTEL_BUS_CLK),
  600         FREQ_INFO(1100,  908, INTEL_BUS_CLK),
  601         FREQ_INFO(1000,  892, INTEL_BUS_CLK),
  602         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  603         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  604         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  605 };
  606 static freq_info PM_753J_90[] = {
  607         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */
  608         FREQ_INFO(1200,  908, INTEL_BUS_CLK),
  609         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  610         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  611         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  612         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  613         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  614 };
  615 static freq_info PM_753K_90[] = {
  616         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */
  617         FREQ_INFO(1200,  892, INTEL_BUS_CLK),
  618         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  619         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  620         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  621         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  622         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  623 };
  624 static freq_info PM_753L_90[] = {
  625         /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */
  626         FREQ_INFO(1200,  876, INTEL_BUS_CLK),
  627         FREQ_INFO(1100,  876, INTEL_BUS_CLK),
  628         FREQ_INFO(1000,  860, INTEL_BUS_CLK),
  629         FREQ_INFO( 900,  844, INTEL_BUS_CLK),
  630         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  631         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  632 };
  633 
  634 static freq_info PM_733JG_90[] = {
  635         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */
  636         FREQ_INFO(1100,  956, INTEL_BUS_CLK),
  637         FREQ_INFO(1000,  940, INTEL_BUS_CLK),
  638         FREQ_INFO( 900,  908, INTEL_BUS_CLK),
  639         FREQ_INFO( 800,  876, INTEL_BUS_CLK),
  640         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  641 };
  642 static freq_info PM_733JH_90[] = {
  643         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */
  644         FREQ_INFO(1100,  940, INTEL_BUS_CLK),
  645         FREQ_INFO(1000,  924, INTEL_BUS_CLK),
  646         FREQ_INFO( 900,  892, INTEL_BUS_CLK),
  647         FREQ_INFO( 800,  876, INTEL_BUS_CLK),
  648         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  649 };
  650 static freq_info PM_733JI_90[] = {
  651         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */
  652         FREQ_INFO(1100,  924, INTEL_BUS_CLK),
  653         FREQ_INFO(1000,  908, INTEL_BUS_CLK),
  654         FREQ_INFO( 900,  892, INTEL_BUS_CLK),
  655         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  656         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  657 };
  658 static freq_info PM_733JJ_90[] = {
  659         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */
  660         FREQ_INFO(1100,  908, INTEL_BUS_CLK),
  661         FREQ_INFO(1000,  892, INTEL_BUS_CLK),
  662         FREQ_INFO( 900,  876, INTEL_BUS_CLK),
  663         FREQ_INFO( 800,  860, INTEL_BUS_CLK),
  664         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  665 };
  666 static freq_info PM_733JK_90[] = {
  667         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */
  668         FREQ_INFO(1100,  892, INTEL_BUS_CLK),
  669         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  670         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  671         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  672         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  673 };
  674 static freq_info PM_733JL_90[] = {
  675         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */
  676         FREQ_INFO(1100,  876, INTEL_BUS_CLK),
  677         FREQ_INFO(1000,  876, INTEL_BUS_CLK),
  678         FREQ_INFO( 900,  860, INTEL_BUS_CLK),
  679         FREQ_INFO( 800,  844, INTEL_BUS_CLK),
  680         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  681 };
  682 static freq_info PM_733_90[] = {
  683         /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */
  684         FREQ_INFO(1100,  940, INTEL_BUS_CLK),
  685         FREQ_INFO(1000,  924, INTEL_BUS_CLK),
  686         FREQ_INFO( 900,  892, INTEL_BUS_CLK),
  687         FREQ_INFO( 800,  876, INTEL_BUS_CLK),
  688         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  689         FREQ_INFO(   0,    0, 1),
  690 };
  691 static freq_info PM_723_90[] = {
  692         /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
  693         FREQ_INFO(1000,  940, INTEL_BUS_CLK),
  694         FREQ_INFO( 900,  908, INTEL_BUS_CLK),
  695         FREQ_INFO( 800,  876, INTEL_BUS_CLK),
  696         FREQ_INFO( 600,  812, INTEL_BUS_CLK),
  697         FREQ_INFO(   0,    0, 1),
  698 };
  699 
  700 /*
  701  * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
  702  * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
  703  */
  704 static freq_info C7M_795[] = {
  705         /* 2.00GHz Centaur C7-M 533 Mhz FSB */
  706         FREQ_INFO_PWR(2000, 1148, 133, 20000),
  707         FREQ_INFO_PWR(1867, 1132, 133, 18000),
  708         FREQ_INFO_PWR(1600, 1100, 133, 15000),
  709         FREQ_INFO_PWR(1467, 1052, 133, 13000),
  710         FREQ_INFO_PWR(1200, 1004, 133, 10000),
  711         FREQ_INFO_PWR( 800,  844, 133,  7000),
  712         FREQ_INFO_PWR( 667,  844, 133,  6000),
  713         FREQ_INFO_PWR( 533,  844, 133,  5000),
  714         FREQ_INFO(0, 0, 1),
  715 };
  716 static freq_info C7M_785[] = {
  717         /* 1.80GHz Centaur C7-M 533 Mhz FSB */
  718         FREQ_INFO_PWR(1867, 1148, 133, 18000),
  719         FREQ_INFO_PWR(1600, 1100, 133, 15000),
  720         FREQ_INFO_PWR(1467, 1052, 133, 13000),
  721         FREQ_INFO_PWR(1200, 1004, 133, 10000),
  722         FREQ_INFO_PWR( 800,  844, 133,  7000),
  723         FREQ_INFO_PWR( 667,  844, 133,  6000),
  724         FREQ_INFO_PWR( 533,  844, 133,  5000),
  725         FREQ_INFO(0, 0, 1),
  726 };
  727 static freq_info C7M_765[] = {
  728         /* 1.60GHz Centaur C7-M 533 Mhz FSB */
  729         FREQ_INFO_PWR(1600, 1084, 133, 15000),
  730         FREQ_INFO_PWR(1467, 1052, 133, 13000),
  731         FREQ_INFO_PWR(1200, 1004, 133, 10000),
  732         FREQ_INFO_PWR( 800,  844, 133,  7000),
  733         FREQ_INFO_PWR( 667,  844, 133,  6000),
  734         FREQ_INFO_PWR( 533,  844, 133,  5000),
  735         FREQ_INFO(0, 0, 1),
  736 };
  737 
  738 static freq_info C7M_794[] = {
  739         /* 2.00GHz Centaur C7-M 400 Mhz FSB */
  740         FREQ_INFO_PWR(2000, 1148, 100, 20000),
  741         FREQ_INFO_PWR(1800, 1132, 100, 18000),
  742         FREQ_INFO_PWR(1600, 1100, 100, 15000),
  743         FREQ_INFO_PWR(1400, 1052, 100, 13000),
  744         FREQ_INFO_PWR(1000, 1004, 100, 10000),
  745         FREQ_INFO_PWR( 800,  844, 100,  7000),
  746         FREQ_INFO_PWR( 600,  844, 100,  6000),
  747         FREQ_INFO_PWR( 400,  844, 100,  5000),
  748         FREQ_INFO(0, 0, 1),
  749 };
  750 static freq_info C7M_784[] = {
  751         /* 1.80GHz Centaur C7-M 400 Mhz FSB */
  752         FREQ_INFO_PWR(1800, 1148, 100, 18000),
  753         FREQ_INFO_PWR(1600, 1100, 100, 15000),
  754         FREQ_INFO_PWR(1400, 1052, 100, 13000),
  755         FREQ_INFO_PWR(1000, 1004, 100, 10000),
  756         FREQ_INFO_PWR( 800,  844, 100,  7000),
  757         FREQ_INFO_PWR( 600,  844, 100,  6000),
  758         FREQ_INFO_PWR( 400,  844, 100,  5000),
  759         FREQ_INFO(0, 0, 1),
  760 };
  761 static freq_info C7M_764[] = {
  762         /* 1.60GHz Centaur C7-M 400 Mhz FSB */
  763         FREQ_INFO_PWR(1600, 1084, 100, 15000),
  764         FREQ_INFO_PWR(1400, 1052, 100, 13000),
  765         FREQ_INFO_PWR(1000, 1004, 100, 10000),
  766         FREQ_INFO_PWR( 800,  844, 100,  7000),
  767         FREQ_INFO_PWR( 600,  844, 100,  6000),
  768         FREQ_INFO_PWR( 400,  844, 100,  5000),
  769         FREQ_INFO(0, 0, 1),
  770 };
  771 static freq_info C7M_754[] = {
  772         /* 1.50GHz Centaur C7-M 400 Mhz FSB */
  773         FREQ_INFO_PWR(1500, 1004, 100, 12000),
  774         FREQ_INFO_PWR(1400,  988, 100, 11000),
  775         FREQ_INFO_PWR(1000,  940, 100,  9000),
  776         FREQ_INFO_PWR( 800,  844, 100,  7000),
  777         FREQ_INFO_PWR( 600,  844, 100,  6000),
  778         FREQ_INFO_PWR( 400,  844, 100,  5000),
  779         FREQ_INFO(0, 0, 1),
  780 };
  781 static freq_info C7M_771[] = {
  782         /* 1.20GHz Centaur C7-M 400 Mhz FSB */
  783         FREQ_INFO_PWR(1200,  860, 100,  7000),
  784         FREQ_INFO_PWR(1000,  860, 100,  6000),
  785         FREQ_INFO_PWR( 800,  844, 100,  5500),
  786         FREQ_INFO_PWR( 600,  844, 100,  5000),
  787         FREQ_INFO_PWR( 400,  844, 100,  4000),
  788         FREQ_INFO(0, 0, 1),
  789 };
  790 
  791 static freq_info C7M_775_ULV[] = {
  792         /* 1.50GHz Centaur C7-M ULV */
  793         FREQ_INFO_PWR(1500,  956, 100,  7500),
  794         FREQ_INFO_PWR(1400,  940, 100,  6000),
  795         FREQ_INFO_PWR(1000,  860, 100,  5000),
  796         FREQ_INFO_PWR( 800,  828, 100,  2800),
  797         FREQ_INFO_PWR( 600,  796, 100,  2500),
  798         FREQ_INFO_PWR( 400,  796, 100,  2000),
  799         FREQ_INFO(0, 0, 1),
  800 };
  801 static freq_info C7M_772_ULV[] = {
  802         /* 1.20GHz Centaur C7-M ULV */
  803         FREQ_INFO_PWR(1200,  844, 100,  5000),
  804         FREQ_INFO_PWR(1000,  844, 100,  4000),
  805         FREQ_INFO_PWR( 800,  828, 100,  2800),
  806         FREQ_INFO_PWR( 600,  796, 100,  2500),
  807         FREQ_INFO_PWR( 400,  796, 100,  2000),
  808         FREQ_INFO(0, 0, 1),
  809 };
  810 static freq_info C7M_779_ULV[] = {
  811         /* 1.00GHz Centaur C7-M ULV */
  812         FREQ_INFO_PWR(1000,  796, 100,  3500),
  813         FREQ_INFO_PWR( 800,  796, 100,  2800),
  814         FREQ_INFO_PWR( 600,  796, 100,  2500),
  815         FREQ_INFO_PWR( 400,  796, 100,  2000),
  816         FREQ_INFO(0, 0, 1),
  817 };
  818 static freq_info C7M_770_ULV[] = {
  819         /* 1.00GHz Centaur C7-M ULV */
  820         FREQ_INFO_PWR(1000,  844, 100,  5000),
  821         FREQ_INFO_PWR( 800,  796, 100,  2800),
  822         FREQ_INFO_PWR( 600,  796, 100,  2500),
  823         FREQ_INFO_PWR( 400,  796, 100,  2000),
  824         FREQ_INFO(0, 0, 1),
  825 };
  826 
  827 static cpu_info ESTprocs[] = {
  828         INTEL(PM17_130,         1700, 1484, 600, 956, INTEL_BUS_CLK),
  829         INTEL(PM16_130,         1600, 1484, 600, 956, INTEL_BUS_CLK),
  830         INTEL(PM15_130,         1500, 1484, 600, 956, INTEL_BUS_CLK),
  831         INTEL(PM14_130,         1400, 1484, 600, 956, INTEL_BUS_CLK),
  832         INTEL(PM13_130,         1300, 1388, 600, 956, INTEL_BUS_CLK),
  833         INTEL(PM13_LV_130,      1300, 1180, 600, 956, INTEL_BUS_CLK),
  834         INTEL(PM12_LV_130,      1200, 1180, 600, 956, INTEL_BUS_CLK),
  835         INTEL(PM11_LV_130,      1100, 1180, 600, 956, INTEL_BUS_CLK),
  836         INTEL(PM11_ULV_130,     1100, 1004, 600, 844, INTEL_BUS_CLK),
  837         INTEL(PM10_ULV_130,     1000, 1004, 600, 844, INTEL_BUS_CLK),
  838         INTEL(PM_765A_90,       2100, 1340, 600, 988, INTEL_BUS_CLK),
  839         INTEL(PM_765B_90,       2100, 1324, 600, 988, INTEL_BUS_CLK),
  840         INTEL(PM_765C_90,       2100, 1308, 600, 988, INTEL_BUS_CLK),
  841         INTEL(PM_765E_90,       2100, 1356, 600, 988, INTEL_BUS_CLK),
  842         INTEL(PM_755A_90,       2000, 1340, 600, 988, INTEL_BUS_CLK),
  843         INTEL(PM_755B_90,       2000, 1324, 600, 988, INTEL_BUS_CLK),
  844         INTEL(PM_755C_90,       2000, 1308, 600, 988, INTEL_BUS_CLK),
  845         INTEL(PM_755D_90,       2000, 1276, 600, 988, INTEL_BUS_CLK),
  846         INTEL(PM_745A_90,       1800, 1340, 600, 988, INTEL_BUS_CLK),
  847         INTEL(PM_745B_90,       1800, 1324, 600, 988, INTEL_BUS_CLK),
  848         INTEL(PM_745C_90,       1800, 1308, 600, 988, INTEL_BUS_CLK),
  849         INTEL(PM_745D_90,       1800, 1276, 600, 988, INTEL_BUS_CLK),
  850         INTEL(PM_735A_90,       1700, 1340, 600, 988, INTEL_BUS_CLK),
  851         INTEL(PM_735B_90,       1700, 1324, 600, 988, INTEL_BUS_CLK),
  852         INTEL(PM_735C_90,       1700, 1308, 600, 988, INTEL_BUS_CLK),
  853         INTEL(PM_735D_90,       1700, 1276, 600, 988, INTEL_BUS_CLK),
  854         INTEL(PM_725A_90,       1600, 1340, 600, 988, INTEL_BUS_CLK),
  855         INTEL(PM_725B_90,       1600, 1324, 600, 988, INTEL_BUS_CLK),
  856         INTEL(PM_725C_90,       1600, 1308, 600, 988, INTEL_BUS_CLK),
  857         INTEL(PM_725D_90,       1600, 1276, 600, 988, INTEL_BUS_CLK),
  858         INTEL(PM_715A_90,       1500, 1340, 600, 988, INTEL_BUS_CLK),
  859         INTEL(PM_715B_90,       1500, 1324, 600, 988, INTEL_BUS_CLK),
  860         INTEL(PM_715C_90,       1500, 1308, 600, 988, INTEL_BUS_CLK),
  861         INTEL(PM_715D_90,       1500, 1276, 600, 988, INTEL_BUS_CLK),
  862         INTEL(PM_778_90,        1600, 1116, 600, 988, INTEL_BUS_CLK),
  863         INTEL(PM_758_90,        1500, 1116, 600, 988, INTEL_BUS_CLK),
  864         INTEL(PM_738_90,        1400, 1116, 600, 988, INTEL_BUS_CLK),
  865         INTEL(PM_773G_90,       1300,  956, 600, 812, INTEL_BUS_CLK),
  866         INTEL(PM_773H_90,       1300,  940, 600, 812, INTEL_BUS_CLK),
  867         INTEL(PM_773I_90,       1300,  924, 600, 812, INTEL_BUS_CLK),
  868         INTEL(PM_773J_90,       1300,  908, 600, 812, INTEL_BUS_CLK),
  869         INTEL(PM_773K_90,       1300,  892, 600, 812, INTEL_BUS_CLK),
  870         INTEL(PM_773L_90,       1300,  876, 600, 812, INTEL_BUS_CLK),
  871         INTEL(PM_753G_90,       1200,  956, 600, 812, INTEL_BUS_CLK),
  872         INTEL(PM_753H_90,       1200,  940, 600, 812, INTEL_BUS_CLK),
  873         INTEL(PM_753I_90,       1200,  924, 600, 812, INTEL_BUS_CLK),
  874         INTEL(PM_753J_90,       1200,  908, 600, 812, INTEL_BUS_CLK),
  875         INTEL(PM_753K_90,       1200,  892, 600, 812, INTEL_BUS_CLK),
  876         INTEL(PM_753L_90,       1200,  876, 600, 812, INTEL_BUS_CLK),
  877         INTEL(PM_733JG_90,      1100,  956, 600, 812, INTEL_BUS_CLK),
  878         INTEL(PM_733JH_90,      1100,  940, 600, 812, INTEL_BUS_CLK),
  879         INTEL(PM_733JI_90,      1100,  924, 600, 812, INTEL_BUS_CLK),
  880         INTEL(PM_733JJ_90,      1100,  908, 600, 812, INTEL_BUS_CLK),
  881         INTEL(PM_733JK_90,      1100,  892, 600, 812, INTEL_BUS_CLK),
  882         INTEL(PM_733JL_90,      1100,  876, 600, 812, INTEL_BUS_CLK),
  883         INTEL(PM_733_90,        1100,  940, 600, 812, INTEL_BUS_CLK),
  884         INTEL(PM_723_90,        1000,  940, 600, 812, INTEL_BUS_CLK),
  885 
  886         CENTAUR(C7M_795,        2000, 1148, 533, 844, 133),
  887         CENTAUR(C7M_794,        2000, 1148, 400, 844, 100),
  888         CENTAUR(C7M_785,        1867, 1148, 533, 844, 133),
  889         CENTAUR(C7M_784,        1800, 1148, 400, 844, 100),
  890         CENTAUR(C7M_765,        1600, 1084, 533, 844, 133),
  891         CENTAUR(C7M_764,        1600, 1084, 400, 844, 100),
  892         CENTAUR(C7M_754,        1500, 1004, 400, 844, 100),
  893         CENTAUR(C7M_775_ULV,    1500,  956, 400, 796, 100),
  894         CENTAUR(C7M_771,        1200,  860, 400, 844, 100),
  895         CENTAUR(C7M_772_ULV,    1200,  844, 400, 796, 100),
  896         CENTAUR(C7M_779_ULV,    1000,  796, 400, 796, 100),
  897         CENTAUR(C7M_770_ULV,    1000,  844, 400, 796, 100),
  898         { 0, 0, NULL },
  899 };
  900 
  901 static void     est_identify(driver_t *driver, device_t parent);
  902 static int      est_features(driver_t *driver, u_int *features);
  903 static int      est_probe(device_t parent);
  904 static int      est_attach(device_t parent);
  905 static int      est_detach(device_t parent);
  906 static int      est_get_info(device_t dev);
  907 static int      est_acpi_info(device_t dev, freq_info **freqs);
  908 static int      est_table_info(device_t dev, uint64_t msr, freq_info **freqs);
  909 static int      est_msr_info(device_t dev, uint64_t msr, freq_info **freqs);
  910 static freq_info *est_get_current(freq_info *freq_list);
  911 static int      est_settings(device_t dev, struct cf_setting *sets, int *count);
  912 static int      est_set(device_t dev, const struct cf_setting *set);
  913 static int      est_get(device_t dev, struct cf_setting *set);
  914 static int      est_type(device_t dev, int *type);
  915 static int      est_set_id16(device_t dev, uint16_t id16, int need_check);
  916 static void     est_get_id16(uint16_t *id16_p);
  917 
  918 static device_method_t est_methods[] = {
  919         /* Device interface */
  920         DEVMETHOD(device_identify,      est_identify),
  921         DEVMETHOD(device_probe,         est_probe),
  922         DEVMETHOD(device_attach,        est_attach),
  923         DEVMETHOD(device_detach,        est_detach),
  924 
  925         /* cpufreq interface */
  926         DEVMETHOD(cpufreq_drv_set,      est_set),
  927         DEVMETHOD(cpufreq_drv_get,      est_get),
  928         DEVMETHOD(cpufreq_drv_type,     est_type),
  929         DEVMETHOD(cpufreq_drv_settings, est_settings),
  930 
  931         /* ACPI interface */
  932         DEVMETHOD(acpi_get_features,    est_features),
  933 
  934         {0, 0}
  935 };
  936 
  937 static driver_t est_driver = {
  938         "est",
  939         est_methods,
  940         sizeof(struct est_softc),
  941 };
  942 
  943 static devclass_t est_devclass;
  944 DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0);
  945 
  946 static int
  947 est_features(driver_t *driver, u_int *features)
  948 {
  949 
  950         /*
  951          * Notify the ACPI CPU that we support direct access to MSRs.
  952          * XXX C1 "I/O then Halt" seems necessary for some broken BIOS.
  953          */
  954         *features = ACPI_CAP_PERF_MSRS | ACPI_CAP_C1_IO_HALT;
  955         return (0);
  956 }
  957 
  958 static void
  959 est_identify(driver_t *driver, device_t parent)
  960 {
  961         device_t child;
  962 
  963         /* Make sure we're not being doubly invoked. */
  964         if (device_find_child(parent, "est", -1) != NULL)
  965                 return;
  966 
  967         /* Check that CPUID is supported and the vendor is Intel.*/
  968         if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL &&
  969             cpu_vendor_id != CPU_VENDOR_CENTAUR))
  970                 return;
  971 
  972         /*
  973          * Check if the CPU supports EST.
  974          */
  975         if (!(cpu_feature2 & CPUID2_EST))
  976                 return;
  977 
  978         /*
  979          * We add a child for each CPU since settings must be performed
  980          * on each CPU in the SMP case.
  981          */
  982         child = BUS_ADD_CHILD(parent, 10, "est", -1);
  983         if (child == NULL)
  984                 device_printf(parent, "add est child failed\n");
  985 }
  986 
  987 static int
  988 est_probe(device_t dev)
  989 {
  990         device_t perf_dev;
  991         uint64_t msr;
  992         int error, type;
  993 
  994         if (resource_disabled("est", 0))
  995                 return (ENXIO);
  996 
  997         /*
  998          * If the ACPI perf driver has attached and is not just offering
  999          * info, let it manage things.
 1000          */
 1001         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
 1002         if (perf_dev && device_is_attached(perf_dev)) {
 1003                 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
 1004                 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
 1005                         return (ENXIO);
 1006         }
 1007 
 1008         /* Attempt to enable SpeedStep if not currently enabled. */
 1009         msr = rdmsr(MSR_MISC_ENABLE);
 1010         if ((msr & MSR_SS_ENABLE) == 0) {
 1011                 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE);
 1012                 if (bootverbose)
 1013                         device_printf(dev, "enabling SpeedStep\n");
 1014 
 1015                 /* Check if the enable failed. */
 1016                 msr = rdmsr(MSR_MISC_ENABLE);
 1017                 if ((msr & MSR_SS_ENABLE) == 0) {
 1018                         device_printf(dev, "failed to enable SpeedStep\n");
 1019                         return (ENXIO);
 1020                 }
 1021         }
 1022 
 1023         device_set_desc(dev, "Enhanced SpeedStep Frequency Control");
 1024         return (0);
 1025 }
 1026 
 1027 static int
 1028 est_attach(device_t dev)
 1029 {
 1030         struct est_softc *sc;
 1031 
 1032         sc = device_get_softc(dev);
 1033         sc->dev = dev;
 1034 
 1035         /* On SMP system we can't guarantie independent freq setting. */
 1036         if (strict == -1 && mp_ncpus > 1)
 1037                 strict = 0;
 1038         /* Check CPU for supported settings. */
 1039         if (est_get_info(dev))
 1040                 return (ENXIO);
 1041 
 1042         cpufreq_register(dev);
 1043         return (0);
 1044 }
 1045 
 1046 static int
 1047 est_detach(device_t dev)
 1048 {
 1049         struct est_softc *sc;
 1050         int error;
 1051 
 1052         error = cpufreq_unregister(dev);
 1053         if (error)
 1054                 return (error);
 1055 
 1056         sc = device_get_softc(dev);
 1057         if (sc->acpi_settings || sc->msr_settings)
 1058                 free(sc->freq_list, M_DEVBUF);
 1059         return (0);
 1060 }
 1061 
 1062 /*
 1063  * Probe for supported CPU settings.  First, check our static table of
 1064  * settings.  If no match, try using the ones offered by acpi_perf
 1065  * (i.e., _PSS).  We use ACPI second because some systems (IBM R/T40
 1066  * series) export both legacy SMM IO-based access and direct MSR access
 1067  * but the direct access specifies invalid values for _PSS.
 1068  */
 1069 static int
 1070 est_get_info(device_t dev)
 1071 {
 1072         struct est_softc *sc;
 1073         uint64_t msr;
 1074         int error;
 1075 
 1076         sc = device_get_softc(dev);
 1077         msr = rdmsr(MSR_PERF_STATUS);
 1078         error = est_table_info(dev, msr, &sc->freq_list);
 1079         if (error)
 1080                 error = est_acpi_info(dev, &sc->freq_list);
 1081         if (error)
 1082                 error = est_msr_info(dev, msr, &sc->freq_list);
 1083 
 1084         if (error) {
 1085                 printf(
 1086         "est: CPU supports Enhanced Speedstep, but is not recognized.\n"
 1087         "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr);
 1088                 return (ENXIO);
 1089         }
 1090 
 1091         return (0);
 1092 }
 1093 
 1094 static int
 1095 est_acpi_info(device_t dev, freq_info **freqs)
 1096 {
 1097         struct est_softc *sc;
 1098         struct cf_setting *sets;
 1099         freq_info *table;
 1100         device_t perf_dev;
 1101         int count, error, i, j;
 1102         uint16_t saved_id16;
 1103 
 1104         perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
 1105         if (perf_dev == NULL || !device_is_attached(perf_dev))
 1106                 return (ENXIO);
 1107 
 1108         /* Fetch settings from acpi_perf. */
 1109         sc = device_get_softc(dev);
 1110         table = NULL;
 1111         sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT);
 1112         if (sets == NULL)
 1113                 return (ENOMEM);
 1114         count = MAX_SETTINGS;
 1115         error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count);
 1116         if (error)
 1117                 goto out;
 1118 
 1119         /* Parse settings into our local table format. */
 1120         table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT);
 1121         if (table == NULL) {
 1122                 error = ENOMEM;
 1123                 goto out;
 1124         }
 1125         est_get_id16(&saved_id16);
 1126         for (i = 0, j = 0; i < count; i++) {
 1127                 /*
 1128                  * Confirm id16 value is correct.
 1129                  */
 1130                 if (sets[i].freq > 0) {
 1131                         error = est_set_id16(dev, sets[i].spec[0], strict);
 1132                         if (error != 0) {
 1133                                 if (bootverbose)
 1134                                         device_printf(dev, "Invalid freq %u, "
 1135                                             "ignored.\n", sets[i].freq);
 1136                                 continue;
 1137                         }
 1138                         table[j].freq = sets[i].freq;
 1139                         table[j].volts = sets[i].volts;
 1140                         table[j].id16 = sets[i].spec[0];
 1141                         table[j].power = sets[i].power;
 1142                         ++j;
 1143                 }
 1144         }
 1145         /* restore saved setting */
 1146         est_set_id16(dev, saved_id16, 0);
 1147 
 1148         /* Mark end of table with a terminator. */
 1149         bzero(&table[j], sizeof(freq_info));
 1150 
 1151         sc->acpi_settings = TRUE;
 1152         *freqs = table;
 1153         error = 0;
 1154 
 1155 out:
 1156         if (sets)
 1157                 free(sets, M_TEMP);
 1158         if (error && table)
 1159                 free(table, M_DEVBUF);
 1160         return (error);
 1161 }
 1162 
 1163 static int
 1164 est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
 1165 {
 1166         cpu_info *p;
 1167         uint32_t id;
 1168 
 1169         /* Find a table which matches (vendor, id32). */
 1170         id = msr >> 32;
 1171         for (p = ESTprocs; p->id32 != 0; p++) {
 1172                 if (p->vendor_id == cpu_vendor_id && p->id32 == id)
 1173                         break;
 1174         }
 1175         if (p->id32 == 0)
 1176                 return (EOPNOTSUPP);
 1177 
 1178         /* Make sure the current setpoint is valid. */
 1179         if (est_get_current(p->freqtab) == NULL) {
 1180                 device_printf(dev, "current setting not found in table\n");
 1181                 return (EOPNOTSUPP);
 1182         }
 1183 
 1184         *freqs = p->freqtab;
 1185         return (0);
 1186 }
 1187 
 1188 static int
 1189 bus_speed_ok(int bus)
 1190 {
 1191 
 1192         switch (bus) {
 1193         case 100:
 1194         case 133:
 1195         case 333:
 1196                 return (1);
 1197         default:
 1198                 return (0);
 1199         }
 1200 }
 1201 
 1202 /*
 1203  * Flesh out a simple rate table containing the high and low frequencies
 1204  * based on the current clock speed and the upper 32 bits of the MSR.
 1205  */
 1206 static int
 1207 est_msr_info(device_t dev, uint64_t msr, freq_info **freqs)
 1208 {
 1209         struct est_softc *sc;
 1210         freq_info *fp;
 1211         int bus, freq, volts;
 1212         uint16_t id;
 1213 
 1214         if (!msr_info_enabled)
 1215                 return (EOPNOTSUPP);
 1216 
 1217         /* Figure out the bus clock. */
 1218         freq = atomic_load_acq_64(&tsc_freq) / 1000000;
 1219         id = msr >> 32;
 1220         bus = freq / (id >> 8);
 1221         device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus);
 1222         if (!bus_speed_ok(bus)) {
 1223                 /* We may be running on the low frequency. */
 1224                 id = msr >> 48;
 1225                 bus = freq / (id >> 8);
 1226                 device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus);
 1227                 if (!bus_speed_ok(bus))
 1228                         return (EOPNOTSUPP);
 1229 
 1230                 /* Calculate high frequency. */
 1231                 id = msr >> 32;
 1232                 freq = ((id >> 8) & 0xff) * bus;
 1233         }
 1234 
 1235         /* Fill out a new freq table containing just the high and low freqs. */
 1236         sc = device_get_softc(dev);
 1237         fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO);
 1238 
 1239         /* First, the high frequency. */
 1240         volts = id & 0xff;
 1241         if (volts != 0) {
 1242                 volts <<= 4;
 1243                 volts += 700;
 1244         }
 1245         fp[0].freq = freq;
 1246         fp[0].volts = volts;
 1247         fp[0].id16 = id;
 1248         fp[0].power = CPUFREQ_VAL_UNKNOWN;
 1249         device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq,
 1250             volts);
 1251 
 1252         /* Second, the low frequency. */
 1253         id = msr >> 48;
 1254         freq = ((id >> 8) & 0xff) * bus;
 1255         volts = id & 0xff;
 1256         if (volts != 0) {
 1257                 volts <<= 4;
 1258                 volts += 700;
 1259         }
 1260         fp[1].freq = freq;
 1261         fp[1].volts = volts;
 1262         fp[1].id16 = id;
 1263         fp[1].power = CPUFREQ_VAL_UNKNOWN;
 1264         device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq,
 1265             volts);
 1266 
 1267         /* Table is already terminated due to M_ZERO. */
 1268         sc->msr_settings = TRUE;
 1269         *freqs = fp;
 1270         return (0);
 1271 }
 1272 
 1273 static void
 1274 est_get_id16(uint16_t *id16_p)
 1275 {
 1276         *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff;
 1277 }
 1278 
 1279 static int
 1280 est_set_id16(device_t dev, uint16_t id16, int need_check)
 1281 {
 1282         uint64_t msr;
 1283         uint16_t new_id16;
 1284         int ret = 0;
 1285 
 1286         /* Read the current register, mask out the old, set the new id. */
 1287         msr = rdmsr(MSR_PERF_CTL);
 1288         msr = (msr & ~0xffff) | id16;
 1289         wrmsr(MSR_PERF_CTL, msr);
 1290 
 1291         if  (need_check) {
 1292                 /* Wait a short while and read the new status. */
 1293                 DELAY(EST_TRANS_LAT);
 1294                 est_get_id16(&new_id16);
 1295                 if (new_id16 != id16) {
 1296                         if (bootverbose)
 1297                                 device_printf(dev, "Invalid id16 (set, cur) "
 1298                                     "= (%u, %u)\n", id16, new_id16);
 1299                         ret = ENXIO;
 1300                 }
 1301         }
 1302         return (ret);
 1303 }
 1304 
 1305 static freq_info *
 1306 est_get_current(freq_info *freq_list)
 1307 {
 1308         freq_info *f;
 1309         int i;
 1310         uint16_t id16;
 1311 
 1312         /*
 1313          * Try a few times to get a valid value.  Sometimes, if the CPU
 1314          * is in the middle of an asynchronous transition (i.e., P4TCC),
 1315          * we get a temporary invalid result.
 1316          */
 1317         for (i = 0; i < 5; i++) {
 1318                 est_get_id16(&id16);
 1319                 for (f = freq_list; f->id16 != 0; f++) {
 1320                         if (f->id16 == id16)
 1321                                 return (f);
 1322                 }
 1323                 DELAY(100);
 1324         }
 1325         return (NULL);
 1326 }
 1327 
 1328 static int
 1329 est_settings(device_t dev, struct cf_setting *sets, int *count)
 1330 {
 1331         struct est_softc *sc;
 1332         freq_info *f;
 1333         int i;
 1334 
 1335         sc = device_get_softc(dev);
 1336         if (*count < EST_MAX_SETTINGS)
 1337                 return (E2BIG);
 1338 
 1339         i = 0;
 1340         for (f = sc->freq_list; f->freq != 0; f++, i++) {
 1341                 sets[i].freq = f->freq;
 1342                 sets[i].volts = f->volts;
 1343                 sets[i].power = f->power;
 1344                 sets[i].lat = EST_TRANS_LAT;
 1345                 sets[i].dev = dev;
 1346         }
 1347         *count = i;
 1348 
 1349         return (0);
 1350 }
 1351 
 1352 static int
 1353 est_set(device_t dev, const struct cf_setting *set)
 1354 {
 1355         struct est_softc *sc;
 1356         freq_info *f;
 1357 
 1358         /* Find the setting matching the requested one. */
 1359         sc = device_get_softc(dev);
 1360         for (f = sc->freq_list; f->freq != 0; f++) {
 1361                 if (f->freq == set->freq)
 1362                         break;
 1363         }
 1364         if (f->freq == 0)
 1365                 return (EINVAL);
 1366 
 1367         /* Read the current register, mask out the old, set the new id. */
 1368         est_set_id16(dev, f->id16, 0);
 1369 
 1370         return (0);
 1371 }
 1372 
 1373 static int
 1374 est_get(device_t dev, struct cf_setting *set)
 1375 {
 1376         struct est_softc *sc;
 1377         freq_info *f;
 1378 
 1379         sc = device_get_softc(dev);
 1380         f = est_get_current(sc->freq_list);
 1381         if (f == NULL)
 1382                 return (ENXIO);
 1383 
 1384         set->freq = f->freq;
 1385         set->volts = f->volts;
 1386         set->power = f->power;
 1387         set->lat = EST_TRANS_LAT;
 1388         set->dev = dev;
 1389         return (0);
 1390 }
 1391 
 1392 static int
 1393 est_type(device_t dev, int *type)
 1394 {
 1395 
 1396         if (type == NULL)
 1397                 return (EINVAL);
 1398 
 1399         *type = CPUFREQ_TYPE_ABSOLUTE;
 1400         return (0);
 1401 }

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